Portapack-Carnage
xpc56el.h
1 /****************************************************************************\
2  * PROJECT : MPC5643L
3  * FILE : mpc5643l.h
4  *
5  * DESCRIPTION : This is the header file describing the register
6  * set for the named projects.
7  *
8  * COPYRIGHT : (c) 2009, Freescale Semiconductor & ST Microelectronics
9  *
10  * VERSION : 1.01
11  * DATE : Thu Oct 8 13:53:51 CEST 2009
12  * AUTHOR : generated from IP-XACT database
13  * HISTORY : Preliminary release.
14 \****************************************************************************/
15 
16 /* >>>> NOTE! this file is auto-generated please do not edit it! <<<< */
17 
18 /****************************************************************************\
19  * Example instantiation and use:
20  *
21  * <MODULE>.<REGISTER>.B.<BIT> = 1;
22  * <MODULE>.<REGISTER>.R = 0x10000000;
23  *
24 \****************************************************************************/
25 
26 
27 #ifndef _leopard_H_ /* prevents multiple inclusions of this file */
28 #define _leopard_H_
29 
30 #include "typedefs.h"
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
36 #ifdef __MWERKS__
37 #pragma push
38 #pragma ANSI_strict off
39 #endif
40 
41 /* #define USE_FIELD_ALIASES_CFLASH */
42 /* #define USE_FIELD_ALIASES_SIUL */
43 /* #define USE_FIELD_ALIASES_SSCM */
44 /* #define USE_FIELD_ALIASES_ME */
45 /* #define USE_FIELD_ALIASES_RGM */
46 /* #define USE_FIELD_ALIASES_ADC */
47 /* #define USE_FIELD_ALIASES_CTU */
48 /* #define USE_FIELD_ALIASES_mcTIMER */
49 /* #define USE_FIELD_ALIASES_mcPWM */
50 /* #define USE_FIELD_ALIASES_LINFLEX */
51 /* #define USE_FIELD_ALIASES_SPP_MCM */
52 /* #define USE_FIELD_ALIASES_INTC */
53 /* #define USE_FIELD_ALIASES_DSPI */
54 /* #define USE_FIELD_ALIASES_FLEXCAN */
55 /* #define USE_FIELD_ALIASES_FR */
56 
57 /****************************************************************/
58 /* */
59 /* Global definitions and aliases */
60 /* */
61 /****************************************************************/
62 
63 /*
64  Platform blocks that are only accessible by the second core (core 1) when
65  the device is in DPM mode. The block definition is equivalent to the one
66  for the first core (core 0) and reuses the related block structure.
67 
68  NOTE: the <block_name>_1 defines are the preferred method for programming
69  */
70 #define AIPS_1 (*(volatile struct AIPS_tag*) 0x8FF00000UL)
71 #define MAX_1 (*(volatile struct MAX_tag*) 0x8FF04000UL)
72 #define MPU_1 (*(volatile struct MPU_tag*) 0x8FF10000UL)
73 #define SEMA4_1 (*(volatile struct SEMA4_tag*) 0x8FF24000UL)
74 #define SWT_1 (*(volatile struct SWT_tag*) 0x8FF38000UL)
75 #define STM_1 (*(volatile struct STM_tag*) 0x8FF3C000UL)
76 #define SPP_MCM_1 (*(volatile struct SPP_MCM_tag*) 0x8FF40000UL)
77 #define SPP_DMA2_1 (*(volatile struct SPP_DMA2_tag*) 0x8FF44000UL)
78 #define INTC_1 (*(volatile struct INTC_tag*) 0x8FF48000UL)
79 
80 /*
81  Platform blocks that are only accessible by the second core (core 1) when
82  the device is in DPM mode. The block definition is equivalent to the one
83  for the first core (core 0) and reuses the related block structure.
84 
85  NOTE: the <block_name>_DPM defines are deprecated, use <block_name>_1 for
86  programming the corresponding blocks for new code instead.
87  */
88 #define AIPS_DPM AIPS_1
89 #define MAX_DPM MAX_1
90 #define MPU_DPM MPU_1
91 #define SEMA4_DPM SEMA4_1
92 #define SWT_DPM SWT_1
93 #define STM_DPM STM_1
94 #define SPP_MCM_DPM SPP_MCM_1
95 #define SPP_DMA2_DPM SPP_DMA2_1
96 #define INTC_DPM INTC_1
97 
98 /* Aliases for Pictus Module names */
99 #define CAN_0 FLEXCAN_A
100 #define CAN_1 FLEXCAN_B
101 #define CTU_0 CTU
102 #define DFLASH CRC
103 #define DMAMUX DMA_CH_MUX
104 #define DSPI_0 DSPI_A
105 #define DSPI_1 DSPI_B
106 #define DSPI_2 DSPI_C
107 #define EDMA SPP_DMA2
108 #define ETIMER_0 mcTIMER0
109 #define ETIMER_1 mcTIMER1
110 #define FLEXPWM_0 mcPWM_A
111 #define FLEXPWM_1 mcPWM_B
112 #define LINFLEX_0 LINFLEX0
113 #define LINFLEX_1 LINFLEX1
114 #define MCM_ SPP_MCM
115 #define PIT PIT_RTI
116 #define SIU SIUL
117 #define WKUP WKPU
118 /****************************************************************/
119 /* */
120 /* Module: CFLASH_SHADOW */
121 /* */
122 /****************************************************************/
123 
124 
125  /* Register layout for all registers NVPWD... */
126 
127  typedef union { /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */
128  vuint32_t R;
129  struct {
130  vuint32_t PWD:32; /* PassWorD */
131  } B;
132  } CFLASH_SHADOW_NVPWD_32B_tag;
133 
134 
135  /* Register layout for all registers NVSCI... */
136 
137  typedef union { /* NVSCI - Non Volatile System Censoring Information Register */
138  vuint32_t R;
139  struct {
140  vuint32_t SC:16; /* Serial Censorship Control Word */
141  vuint32_t CW:16; /* Censorship Control Word */
142  } B;
143  } CFLASH_SHADOW_NVSCI_32B_tag;
144 
145  typedef union { /* Non Volatile LML Default Value */
146  vuint32_t R;
147  } CFLASH_SHADOW_NVLML_32B_tag;
148 
149  typedef union { /* Non Volatile HBL Default Value */
150  vuint32_t R;
151  } CFLASH_SHADOW_NVHBL_32B_tag;
152 
153  typedef union { /* Non Volatile SLL Default Value */
154  vuint32_t R;
155  } CFLASH_SHADOW_NVSLL_32B_tag;
156 
157 
158  /* Register layout for all registers NVBIU... */
159 
160  typedef union { /* Non Volatile Bus Interface Unit Register */
161  vuint32_t R;
162  struct {
163  vuint32_t BI:32; /* Bus interface Unit */
164  } B;
165  } CFLASH_SHADOW_NVBIU_32B_tag;
166 
167  typedef union { /* NVUSRO - Non Volatile USeR Options Register */
168  vuint32_t R;
169  struct {
170  vuint32_t UO:32; /* User Options */
171  } B;
172  } CFLASH_SHADOW_NVUSRO_32B_tag;
173 
174 
175  typedef struct CFLASH_SHADOW_BIU_DEFAULTS_struct_tag {
176 
177  /* Non Volatile Bus Interface Unit Register */
178  CFLASH_SHADOW_NVBIU_32B_tag NVBIU; /* relative offset: 0x0000 */
179  int8_t CFLASH_SHADOW_BIU_DEFAULTS_reserved_0004[4];
180 
181  } CFLASH_SHADOW_BIU_DEFAULTS_tag;
182 
183 
184  typedef struct CFLASH_SHADOW_struct_tag { /* start of CFLASH_SHADOW_tag */
185  int8_t CFLASH_SHADOW_reserved_0000_C[15832];
186  union {
187  /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */
188  CFLASH_SHADOW_NVPWD_32B_tag NVPWD[2]; /* offset: 0x3DD8 (0x0004 x 2) */
189 
190  struct {
191  /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */
192  CFLASH_SHADOW_NVPWD_32B_tag NVPWD0; /* offset: 0x3DD8 size: 32 bit */
193  CFLASH_SHADOW_NVPWD_32B_tag NVPWD1; /* offset: 0x3DDC size: 32 bit */
194  };
195 
196  };
197  union {
198  /* NVSCI - Non Volatile System Censoring Information Register */
199  CFLASH_SHADOW_NVSCI_32B_tag NVSCI[2]; /* offset: 0x3DE0 (0x0004 x 2) */
200 
201  struct {
202  /* NVSCI - Non Volatile System Censoring Information Register */
203  CFLASH_SHADOW_NVSCI_32B_tag NVSCI0; /* offset: 0x3DE0 size: 32 bit */
204  CFLASH_SHADOW_NVSCI_32B_tag NVSCI1; /* offset: 0x3DE4 size: 32 bit */
205  };
206 
207  };
208  /* Non Volatile LML Default Value */
209  CFLASH_SHADOW_NVLML_32B_tag NVLML; /* offset: 0x3DE8 size: 32 bit */
210  int8_t CFLASH_SHADOW_reserved_3DEC[4];
211  /* Non Volatile HBL Default Value */
212  CFLASH_SHADOW_NVHBL_32B_tag NVHBL; /* offset: 0x3DF0 size: 32 bit */
213  int8_t CFLASH_SHADOW_reserved_3DF4[4];
214  /* Non Volatile SLL Default Value */
215  CFLASH_SHADOW_NVSLL_32B_tag NVSLL; /* offset: 0x3DF8 size: 32 bit */
216  int8_t CFLASH_SHADOW_reserved_3DFC_C[4];
217  union {
218  /* Register set BIU_DEFAULTS */
219  CFLASH_SHADOW_BIU_DEFAULTS_tag BIU_DEFAULTS[3]; /* offset: 0x3E00 (0x0008 x 3) */
220 
221  struct {
222  /* Non Volatile Bus Interface Unit Register */
223  CFLASH_SHADOW_NVBIU_32B_tag NVBIU2; /* offset: 0x3E00 size: 32 bit */
224  int8_t CFLASH_SHADOW_reserved_3E04_I1[4];
225  CFLASH_SHADOW_NVBIU_32B_tag NVBIU3; /* offset: 0x3E08 size: 32 bit */
226  int8_t CFLASH_SHADOW_reserved_3E0C_I1[4];
227  CFLASH_SHADOW_NVBIU_32B_tag NVBIU4; /* offset: 0x3E10 size: 32 bit */
228  int8_t CFLASH_SHADOW_reserved_3E14_E1[4];
229  };
230 
231  };
232  /* NVUSRO - Non Volatile USeR Options Register */
233  CFLASH_SHADOW_NVUSRO_32B_tag NVUSRO; /* offset: 0x3E18 size: 32 bit */
234  } CFLASH_SHADOW_tag;
235 
236 
237 #define CFLASH_SHADOW (*(volatile CFLASH_SHADOW_tag *) 0x00F00000UL)
238 
239 
240 
241 /****************************************************************/
242 /* */
243 /* Module: CFLASH */
244 /* */
245 /****************************************************************/
246 
247  typedef union { /* MCR - Module Configuration Register */
248  vuint32_t R;
249  struct {
250  vuint32_t:5;
251  vuint32_t SIZE:3; /* Array Space Size */
252  vuint32_t:1;
253  vuint32_t LAS:3; /* Low Address Space */
254  vuint32_t:3;
255  vuint32_t MAS:1; /* Mid Address Space Configuration */
256  vuint32_t EER:1; /* ECC Event Error */
257  vuint32_t RWE:1; /* Read-while-Write Event Error */
258  vuint32_t SBC:1; /* Single Bit Correction */
259  vuint32_t:1;
260  vuint32_t PEAS:1; /* Program/Erase Access Space */
261  vuint32_t DONE:1; /* modify operation DONE */
262  vuint32_t PEG:1; /* Program/Erase Good */
263  vuint32_t:4;
264  vuint32_t PGM:1; /* Program Bit */
265  vuint32_t PSUS:1; /* Program Suspend */
266  vuint32_t ERS:1; /* Erase Bit */
267  vuint32_t ESUS:1; /* Erase Suspend */
268  vuint32_t EHV:1; /* Enable High Voltage */
269  } B;
270  } CFLASH_MCR_32B_tag;
271 
272  typedef union { /* LML - Low/Mid Address Space Block Locking Register */
273  vuint32_t R;
274  struct {
275  vuint32_t LME:1; /* Low/Mid Address Space Block Enable */
276  vuint32_t:10;
277 #ifndef USE_FIELD_ALIASES_CFLASH
278  vuint32_t SLOCK:1; /* Shadow Address Space Block Lock */
279 #else
280  vuint32_t TSLK:1; /* deprecated name - please avoid */
281 #endif
282  vuint32_t:2;
283 #ifndef USE_FIELD_ALIASES_CFLASH
284  vuint32_t MLOCK:2; /* Mid Address Space Block Lock */
285 #else
286  vuint32_t MLK:2; /* deprecated name - please avoid */
287 #endif
288  vuint32_t:6;
289  vuint32_t LLOCK:10; /* Low Address Space Block Lock */
290  } B;
291  } CFLASH_LML_32B_tag;
292 
293  typedef union { /* HBL - High Address Space Block Locking Register */
294  vuint32_t R;
295  struct {
296  vuint32_t HBE:1; /* High Address Space Block Enable */
297  vuint32_t:25;
298  vuint32_t HLOCK:6; /* High Address Space Block Lock */
299  } B;
300  } CFLASH_HBL_32B_tag;
301 
302  typedef union { /* SLL - Secondary Low/Mid Address Space Block Locking Register */
303  vuint32_t R;
304  struct {
305  vuint32_t SLE:1; /* Secondary Low/Mid Address Space Block Enable */
306  vuint32_t:10;
307 #ifndef USE_FIELD_ALIASES_CFLASH
308  vuint32_t SSLOCK:1; /* Secondary Shadow Address Space Block Lock */
309 #else
310  vuint32_t STSLK:1; /* deprecated name - please avoid */
311 #endif
312  vuint32_t:2;
313 #ifndef USE_FIELD_ALIASES_CFLASH
314  vuint32_t SMLOCK:2; /* Secondary Mid Address Space Block Lock */
315 #else
316  vuint32_t SMK:2; /* deprecated name - please avoid */
317 #endif
318  vuint32_t:6;
319  vuint32_t SLLOCK:10; /* Secondary Low Address Space Block Lock */
320  } B;
321  } CFLASH_SLL_32B_tag;
322 
323  typedef union { /* LMS - Low/Mid Address Space Block Select Register */
324  vuint32_t R;
325  struct {
326  vuint32_t:14;
327  vuint32_t MSL:2; /* Mid Address Space Block Select */
328  vuint32_t:6;
329  vuint32_t LSL:10; /* Low Address Space Block Select */
330  } B;
331  } CFLASH_LMS_32B_tag;
332 
333  typedef union { /* HBS - High Address Space Block Select Register */
334  vuint32_t R;
335  struct {
336  vuint32_t:26;
337  vuint32_t HSL:6; /* High Address Space Block Select */
338  } B;
339  } CFLASH_HBS_32B_tag;
340 
341  typedef union { /* ADR - Address Register */
342  vuint32_t R;
343  struct {
344  vuint32_t SAD:1; /* Shadow Address */
345  vuint32_t:10;
346  vuint32_t ADDR:18; /* Address */
347  vuint32_t:3;
348  } B;
349  } CFLASH_ADR_32B_tag;
350 
351  typedef union { /* PFLASH2P_LCA_PFCR0 - Platform Flash Configuration Register 0 */
352  vuint32_t R;
353  struct {
354 #ifndef USE_FIELD_ALIASES_CFLASH
355  vuint32_t B02_APC:5; /* Bank0+2 Address Pipelining Control */
356 #else
357  vuint32_t BK0_APC:5; /* deprecated name - please avoid */
358 #endif
359 #ifndef USE_FIELD_ALIASES_CFLASH
360  vuint32_t B02_WWSC:5; /* Bank0+2 Write Wait State Control */
361 #else
362  vuint32_t BK0_WWSC:5; /* deprecated name - please avoid */
363 #endif
364 #ifndef USE_FIELD_ALIASES_CFLASH
365  vuint32_t B02_RWSC:5; /* Bank0+2 Read Wait State Control */
366 #else
367  vuint32_t BK0_RWSC:5; /* deprecated name - please avoid */
368 #endif
369 #ifndef USE_FIELD_ALIASES_CFLASH
370  vuint32_t B02_RWWC2:1; /* Bank 0+2 Read While Write Control, bit 2 */
371 #else
372  vuint32_t BK0_RWWC2:1; /* deprecated name - please avoid */
373 #endif
374 #ifndef USE_FIELD_ALIASES_CFLASH
375  vuint32_t B02_RWWC1:1; /* Bank 0+2 Read While Write Control, bit 1 */
376 #else
377  vuint32_t BK0_RWWC1:1; /* deprecated name - please avoid */
378 #endif
379 #ifndef USE_FIELD_ALIASES_CFLASH
380  vuint32_t B02_P1_BCFG:2; /* Bank0+2 Port 1 Page Buffer Configuration */
381 #else
382  vuint32_t B0_P1_BCFG:2; /* deprecated name - please avoid */
383 #endif
384 #ifndef USE_FIELD_ALIASES_CFLASH
385  vuint32_t B02_P1_DPFE:1; /* Bank0+2 Port 1 Data Prefetch Enable */
386 #else
387  vuint32_t B0_P1_DPFE:1; /* deprecated name - please avoid */
388 #endif
389 #ifndef USE_FIELD_ALIASES_CFLASH
390  vuint32_t B02_P1_IPFE:1; /* Bank0+2 Port 1 Inst Prefetch Enable */
391 #else
392  vuint32_t B0_P1_IPFE:1; /* deprecated name - please avoid */
393 #endif
394 #ifndef USE_FIELD_ALIASES_CFLASH
395  vuint32_t B02_P1_PFLM:2; /* Bank0+2 Port 1 Prefetch Limit */
396 #else
397  vuint32_t B0_P1_PFLM:2; /* deprecated name - please avoid */
398 #endif
399 #ifndef USE_FIELD_ALIASES_CFLASH
400  vuint32_t B02_P1_BFE:1; /* Bank0+2 Port 1 Buffer Enable */
401 #else
402  vuint32_t B0_P1_BFE:1; /* deprecated name - please avoid */
403 #endif
404 #ifndef USE_FIELD_ALIASES_CFLASH
405  vuint32_t B02_RWWC0:1; /* Bank 0+2 Read While Write Control, bit 0 */
406 #else
407  vuint32_t BK0_RWWC0:1; /* deprecated name - please avoid */
408 #endif
409 #ifndef USE_FIELD_ALIASES_CFLASH
410  vuint32_t B02_P0_BCFG:2; /* Bank0+2 Port 0 Page Buffer Configuration */
411 #else
412  vuint32_t B0_P0_BCFG:2; /* deprecated name - please avoid */
413 #endif
414 #ifndef USE_FIELD_ALIASES_CFLASH
415  vuint32_t B02_P0_DPFE:1; /* Bank0+2 Port 0 Data Prefetch Enable */
416 #else
417  vuint32_t B0_P0_DPFE:1; /* deprecated name - please avoid */
418 #endif
419 #ifndef USE_FIELD_ALIASES_CFLASH
420  vuint32_t B02_P0_IPFE:1; /* Bank0+2 Port 0 Inst Prefetch Enable */
421 #else
422  vuint32_t B0_P0_IPFE:1; /* deprecated name - please avoid */
423 #endif
424 #ifndef USE_FIELD_ALIASES_CFLASH
425  vuint32_t B02_P0_PFLM:2; /* Bank0+2 Port 0 Prefetch Limit */
426 #else
427  vuint32_t B0_P0_PFLM:2; /* deprecated name - please avoid */
428 #endif
429 #ifndef USE_FIELD_ALIASES_CFLASH
430  vuint32_t B02_P0_BFE:1; /* Bank0+2 Port 0 Buffer Enable */
431 #else
432  vuint32_t B0_P0_BFE:1; /* deprecated name - please avoid */
433 #endif
434  } B;
435  } CFLASH_PFCR0_32B_tag;
436 
437 
438  /* Register layout for all registers BIU... */
439 
440  typedef union { /* Bus Interface Unit Register */
441  vuint32_t R;
442  } CFLASH_BIU_32B_tag;
443 
444  typedef union { /* PFLASH2P_LCA_PFCR1 - Platform Flash Configuration Register 1 */
445  vuint32_t R;
446  struct {
447 #ifndef USE_FIELD_ALIASES_CFLASH
448  vuint32_t B1_APC:5; /* Bank 1 Address Pipelining Control */
449  vuint32_t B1_WWSC:5; /* Bank 1 Write Wait State Control */
450  vuint32_t B1_RWSC:5; /* Bank 1 Read Wait State Control */
451  vuint32_t B1_RWWC2:1; /* Bank1 Read While Write Control, bit 2 */
452  vuint32_t B1_RWWC1:1; /* Bank1 Read While Write Control, bit 1 */
453  vuint32_t:6;
454  vuint32_t B1_P1_BFE:1; /* Bank 1 Port 1 Buffer Enable */
455  vuint32_t B1_RWWC0:1; /* Bank1 Read While Write Control, bit 0 */
456  vuint32_t:6;
457  vuint32_t B1_P0_BFE:1; /* Bank 1 Port 0 Buffer Enable */
458 #else
459  vuint32_t BK1_APC:5;
460  vuint32_t BK1_WWSC:5;
461  vuint32_t BK1_RWSC:5;
462  vuint32_t BK1_RWWC2:1;
463  vuint32_t BK1_RWWC1:1;
464  vuint32_t:6;
465  vuint32_t B0_P1_BFE:1;
466  vuint32_t BK1_RWWC0:1;
467  vuint32_t:6;
468  vuint32_t B1_P0_BFE:1;
469 #endif
470  } B;
471  } CFLASH_PFCR1_32B_tag;
472 
473  typedef union { /* PFLASH2P_LCA_PFAPR - Platform Flash Access Protection Register */
474  vuint32_t R;
475  struct {
476  vuint32_t:6;
477  vuint32_t ARBM:2; /* Arbitration Mode */
478  vuint32_t M7PFD:1; /* Master x Prefetch Disable */
479  vuint32_t M6PFD:1; /* Master x Prefetch Disable */
480  vuint32_t M5PFD:1; /* Master x Prefetch Disable */
481  vuint32_t M4PFD:1; /* Master x Prefetch Disable */
482  vuint32_t M3PFD:1; /* Master x Prefetch Disable */
483  vuint32_t M2PFD:1; /* Master x Prefetch Disable */
484  vuint32_t M1PFD:1; /* Master x Prefetch Disable */
485  vuint32_t M0PFD:1; /* Master x Prefetch Disable */
486  vuint32_t M7AP:2; /* Master 7 Access Protection */
487  vuint32_t M6AP:2; /* Master 6 Access Protection */
488  vuint32_t M5AP:2; /* Master 5 Access Protection */
489  vuint32_t M4AP:2; /* Master 4 Access Protection */
490  vuint32_t M3AP:2; /* Master 3 Access Protection */
491  vuint32_t M2AP:2; /* Master 2 Access Protection */
492  vuint32_t M1AP:2; /* Master 1 Access Protection */
493  vuint32_t M0AP:2; /* Master 0 Access Protection */
494  } B;
495  } CFLASH_PFAPR_32B_tag;
496 
497  typedef union { /* UT0 - User Test Register */
498  vuint32_t R;
499  struct {
500  vuint32_t UTE:1; /* User Test Enable */
501  vuint32_t SBCE:1; /* Single Bit Correction Enable */
502  vuint32_t:6;
503  vuint32_t DSI:8; /* Data Syndrome Input */
504  vuint32_t:10;
505  vuint32_t MRE:1; /* Margin Read Enable */
506  vuint32_t MRV:1; /* Margin Read Value */
507  vuint32_t EIE:1; /* ECC Data Input Enable */
508  vuint32_t AIS:1; /* Array Integrity Sequence */
509  vuint32_t AIE:1; /* Array Integrity Enable */
510  vuint32_t AID:1; /* Array Integrity Done */
511  } B;
512  } CFLASH_UT0_32B_tag;
513 
514  typedef union { /* UT1 - User Test Register */
515  vuint32_t R;
516  } CFLASH_UT1_32B_tag;
517 
518  typedef union { /* UT2 - User Test Register */
519  vuint32_t R;
520  } CFLASH_UT2_32B_tag;
521 
522 
523  /* Register layout for all registers UM... */
524 
525  typedef union { /* UM - User Multiple Input Signature Register */
526  vuint32_t R;
527  struct {
528 #ifndef USE_FIELD_ALIASES_CFLASH
529  vuint32_t MISR:32; /* Multiple Input Signature */
530 #else
531  vuint32_t MS:32; /* deprecated - please avoid */
532 #endif
533  } B;
534  } CFLASH_UM_32B_tag;
535 
536 
537  /* Register layout for generated register(s) UT... */
538 
539  typedef union { /* */
540  vuint32_t R;
541  } CFLASH_UT_32B_tag;
542 
543 
544  /* Register layout for generated register(s) PFCR... */
545 
546  typedef union { /* */
547  vuint32_t R;
548  } CFLASH_PFCR_32B_tag;
549 
550 
551 
552  typedef struct CFLASH_struct_tag { /* start of CFLASH_tag */
553  /* MCR - Module Configuration Register */
554  CFLASH_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */
555  /* LML - Low/Mid Address Space Block Locking Register */
556  CFLASH_LML_32B_tag LML; /* offset: 0x0004 size: 32 bit */
557  /* HBL - High Address Space Block Locking Register */
558  CFLASH_HBL_32B_tag HBL; /* offset: 0x0008 size: 32 bit */
559  /* SLL - Secondary Low/Mid Address Space Block Locking Register */
560  CFLASH_SLL_32B_tag SLL; /* offset: 0x000C size: 32 bit */
561  /* LMS - Low/Mid Address Space Block Select Register */
562  CFLASH_LMS_32B_tag LMS; /* offset: 0x0010 size: 32 bit */
563  /* HBS - High Address Space Block Select Register */
564  CFLASH_HBS_32B_tag HBS; /* offset: 0x0014 size: 32 bit */
565  /* ADR - Address Register */
566  CFLASH_ADR_32B_tag ADR; /* offset: 0x0018 size: 32 bit */
567  union {
568  struct {
569  /* */
570  CFLASH_PFCR_32B_tag PFCR[2]; /* offset: 0x001C (0x0004 x 2) */
571  int8_t CFLASH_reserved_0024_E0[12];
572  };
573 
574  /* Bus Interface Unit Register */
575  CFLASH_BIU_32B_tag BIU[5]; /* offset: 0x001C (0x0004 x 5) */
576 
577  struct {
578  /* Bus Interface Unit Register */
579  CFLASH_BIU_32B_tag BIU0; /* offset: 0x001C size: 32 bit */
580  CFLASH_BIU_32B_tag BIU1; /* offset: 0x0020 size: 32 bit */
581  CFLASH_BIU_32B_tag BIU2; /* offset: 0x0024 size: 32 bit */
582  CFLASH_BIU_32B_tag BIU3; /* offset: 0x0028 size: 32 bit */
583  CFLASH_BIU_32B_tag BIU4; /* offset: 0x002C size: 32 bit */
584  };
585 
586  struct {
587  int8_t CFLASH_reserved_001C_I3[8];
588  CFLASH_PFAPR_32B_tag FAPR; /* deprecated - please avoid */
589  int8_t CFLASH_reserved_0028_E3[8];
590  };
591 
592  struct {
593  /* PFLASH2P_LCA_PFCR0 - Platform Flash Configuration Register 0 */
594  CFLASH_PFCR0_32B_tag PFCR0; /* offset: 0x001C size: 32 bit */
595  /* PFLASH2P_LCA_PFCR1 - Platform Flash Configuration Register 1 */
596  CFLASH_PFCR1_32B_tag PFCR1; /* offset: 0x0020 size: 32 bit */
597  /* PFLASH2P_LCA_PFAPR - Platform Flash Access Protection Register */
598  CFLASH_PFAPR_32B_tag PFAPR; /* offset: 0x0024 size: 32 bit */
599  int8_t CFLASH_reserved_0028_E4[8];
600  };
601 
602  };
603  int8_t CFLASH_reserved_0030_C[12];
604  union {
605  CFLASH_UT_32B_tag UT[3]; /* offset: 0x003C (0x0004 x 3) */
606 
607  struct {
608  /* UT0 - User Test Register */
609  CFLASH_UT0_32B_tag UT0; /* offset: 0x003C size: 32 bit */
610  /* UT1 - User Test Register */
611  CFLASH_UT1_32B_tag UT1; /* offset: 0x0040 size: 32 bit */
612  /* UT2 - User Test Register */
613  CFLASH_UT2_32B_tag UT2; /* offset: 0x0044 size: 32 bit */
614  };
615 
616  };
617  union {
618  CFLASH_UM_32B_tag UMISR[5]; /* offset: 0x0048 (0x0004 x 5) */
619 
620  /* UM - User Multiple Input Signature Register */
621  CFLASH_UM_32B_tag UM[5]; /* offset: 0x0048 (0x0004 x 5) */
622 
623  struct {
624  /* UM - User Multiple Input Signature Register */
625  CFLASH_UM_32B_tag UM0; /* offset: 0x0048 size: 32 bit */
626  CFLASH_UM_32B_tag UM1; /* offset: 0x004C size: 32 bit */
627  CFLASH_UM_32B_tag UM2; /* offset: 0x0050 size: 32 bit */
628  CFLASH_UM_32B_tag UM3; /* offset: 0x0054 size: 32 bit */
629  CFLASH_UM_32B_tag UM4; /* offset: 0x0058 size: 32 bit */
630  };
631 
632  };
633  } CFLASH_tag;
634 
635 
636 #define CFLASH (*(volatile CFLASH_tag *) 0xC3F88000UL)
637 
638 
639 
640 /****************************************************************/
641 /* */
642 /* Module: SIUL */
643 /* */
644 /****************************************************************/
645 
646  typedef union { /* MIDR1 - MCU ID Register #1 */
647  vuint32_t R;
648  struct {
649  vuint32_t PARTNUM:16; /* MCU Part Number */
650  vuint32_t CSP:1; /* CSP Package */
651  vuint32_t PKG:5; /* Package Settings */
652  vuint32_t:2;
653 #ifndef USE_FIELD_ALIASES_SIUL
654  vuint32_t MAJOR_MASK:4; /* Major Mask Revision */
655 #else
656  vuint32_t MAJORMASK:4; /* deprecated name - please avoid */
657 #endif
658 #ifndef USE_FIELD_ALIASES_SIUL
659  vuint32_t MINOR_MASK:4; /* Minor Mask Revision */
660 #else
661  vuint32_t MINORMASK:4; /* deprecated name - please avoid */
662 #endif
663  } B;
664  } SIUL_MIDR1_32B_tag;
665 
666  typedef union { /* MIDR2 - MCU ID Register #2 */
667  vuint32_t R;
668  struct {
669  vuint32_t SF:1; /* Manufacturer */
670  vuint32_t FLASH_SIZE_1:4; /* Coarse Flash Memory Size */
671  vuint32_t FLASH_SIZE_2:4; /* Fine Flash Memory Size */
672  vuint32_t:7;
673 #ifndef USE_FIELD_ALIASES_SIUL
674  vuint32_t PARTNUM2:8; /* MCU Part Number */
675 #else
676  vuint32_t PARTNUM:8; /* deprecated name - please avoid */
677 #endif
678  vuint32_t TBD:1; /* Optional Bit */
679  vuint32_t:2;
680  vuint32_t EE:1; /* Data Flash Present */
681  vuint32_t:3;
682  vuint32_t FR:1; /* Flexray Present */
683  } B;
684  } SIUL_MIDR2_32B_tag;
685 
686  typedef union { /* ISR - Interrupt Status Flag Register */
687  vuint32_t R;
688  struct {
689  vuint32_t EIF31:1; /* External Interrupt Status Flag */
690  vuint32_t EIF30:1; /* External Interrupt Status Flag */
691  vuint32_t EIF29:1; /* External Interrupt Status Flag */
692  vuint32_t EIF28:1; /* External Interrupt Status Flag */
693  vuint32_t EIF27:1; /* External Interrupt Status Flag */
694  vuint32_t EIF26:1; /* External Interrupt Status Flag */
695  vuint32_t EIF25:1; /* External Interrupt Status Flag */
696  vuint32_t EIF24:1; /* External Interrupt Status Flag */
697  vuint32_t EIF23:1; /* External Interrupt Status Flag */
698  vuint32_t EIF22:1; /* External Interrupt Status Flag */
699  vuint32_t EIF21:1; /* External Interrupt Status Flag */
700  vuint32_t EIF20:1; /* External Interrupt Status Flag */
701  vuint32_t EIF19:1; /* External Interrupt Status Flag */
702  vuint32_t EIF18:1; /* External Interrupt Status Flag */
703  vuint32_t EIF17:1; /* External Interrupt Status Flag */
704  vuint32_t EIF16:1; /* External Interrupt Status Flag */
705  vuint32_t EIF15:1; /* External Interrupt Status Flag */
706  vuint32_t EIF14:1; /* External Interrupt Status Flag */
707  vuint32_t EIF13:1; /* External Interrupt Status Flag */
708  vuint32_t EIF12:1; /* External Interrupt Status Flag */
709  vuint32_t EIF11:1; /* External Interrupt Status Flag */
710  vuint32_t EIF10:1; /* External Interrupt Status Flag */
711  vuint32_t EIF9:1; /* External Interrupt Status Flag */
712  vuint32_t EIF8:1; /* External Interrupt Status Flag */
713  vuint32_t EIF7:1; /* External Interrupt Status Flag */
714  vuint32_t EIF6:1; /* External Interrupt Status Flag */
715  vuint32_t EIF5:1; /* External Interrupt Status Flag */
716  vuint32_t EIF4:1; /* External Interrupt Status Flag */
717  vuint32_t EIF3:1; /* External Interrupt Status Flag */
718  vuint32_t EIF2:1; /* External Interrupt Status Flag */
719  vuint32_t EIF1:1; /* External Interrupt Status Flag */
720  vuint32_t EIF0:1; /* External Interrupt Status Flag */
721  } B;
722  } SIUL_ISR_32B_tag;
723 
724  typedef union { /* IRER - Interrupt Request Enable Register */
725  vuint32_t R;
726  struct {
727  vuint32_t EIRE31:1; /* Enable External Interrupt Requests */
728  vuint32_t EIRE30:1; /* Enable External Interrupt Requests */
729  vuint32_t EIRE29:1; /* Enable External Interrupt Requests */
730  vuint32_t EIRE28:1; /* Enable External Interrupt Requests */
731  vuint32_t EIRE27:1; /* Enable External Interrupt Requests */
732  vuint32_t EIRE26:1; /* Enable External Interrupt Requests */
733  vuint32_t EIRE25:1; /* Enable External Interrupt Requests */
734  vuint32_t EIRE24:1; /* Enable External Interrupt Requests */
735  vuint32_t EIRE23:1; /* Enable External Interrupt Requests */
736  vuint32_t EIRE22:1; /* Enable External Interrupt Requests */
737  vuint32_t EIRE21:1; /* Enable External Interrupt Requests */
738  vuint32_t EIRE20:1; /* Enable External Interrupt Requests */
739  vuint32_t EIRE19:1; /* Enable External Interrupt Requests */
740  vuint32_t EIRE18:1; /* Enable External Interrupt Requests */
741  vuint32_t EIRE17:1; /* Enable External Interrupt Requests */
742  vuint32_t EIRE16:1; /* Enable External Interrupt Requests */
743  vuint32_t EIRE15:1; /* Enable External Interrupt Requests */
744  vuint32_t EIRE14:1; /* Enable External Interrupt Requests */
745  vuint32_t EIRE13:1; /* Enable External Interrupt Requests */
746  vuint32_t EIRE12:1; /* Enable External Interrupt Requests */
747  vuint32_t EIRE11:1; /* Enable External Interrupt Requests */
748  vuint32_t EIRE10:1; /* Enable External Interrupt Requests */
749  vuint32_t EIRE9:1; /* Enable External Interrupt Requests */
750  vuint32_t EIRE8:1; /* Enable External Interrupt Requests */
751  vuint32_t EIRE7:1; /* Enable External Interrupt Requests */
752  vuint32_t EIRE6:1; /* Enable External Interrupt Requests */
753  vuint32_t EIRE5:1; /* Enable External Interrupt Requests */
754  vuint32_t EIRE4:1; /* Enable External Interrupt Requests */
755  vuint32_t EIRE3:1; /* Enable External Interrupt Requests */
756  vuint32_t EIRE2:1; /* Enable External Interrupt Requests */
757  vuint32_t EIRE1:1; /* Enable External Interrupt Requests */
758  vuint32_t EIRE0:1; /* Enable External Interrupt Requests */
759  } B;
760  } SIUL_IRER_32B_tag;
761 
762  typedef union { /* IREER - Interrupt Rising Edge Event Enable */
763  vuint32_t R;
764  struct {
765  vuint32_t IREE31:1; /* Enable rising-edge events */
766  vuint32_t IREE30:1; /* Enable rising-edge events */
767  vuint32_t IREE29:1; /* Enable rising-edge events */
768  vuint32_t IREE28:1; /* Enable rising-edge events */
769  vuint32_t IREE27:1; /* Enable rising-edge events */
770  vuint32_t IREE26:1; /* Enable rising-edge events */
771  vuint32_t IREE25:1; /* Enable rising-edge events */
772  vuint32_t IREE24:1; /* Enable rising-edge events */
773  vuint32_t IREE23:1; /* Enable rising-edge events */
774  vuint32_t IREE22:1; /* Enable rising-edge events */
775  vuint32_t IREE21:1; /* Enable rising-edge events */
776  vuint32_t IREE20:1; /* Enable rising-edge events */
777  vuint32_t IREE19:1; /* Enable rising-edge events */
778  vuint32_t IREE18:1; /* Enable rising-edge events */
779  vuint32_t IREE17:1; /* Enable rising-edge events */
780  vuint32_t IREE16:1; /* Enable rising-edge events */
781  vuint32_t IREE15:1; /* Enable rising-edge events */
782  vuint32_t IREE14:1; /* Enable rising-edge events */
783  vuint32_t IREE13:1; /* Enable rising-edge events */
784  vuint32_t IREE12:1; /* Enable rising-edge events */
785  vuint32_t IREE11:1; /* Enable rising-edge events */
786  vuint32_t IREE10:1; /* Enable rising-edge events */
787  vuint32_t IREE9:1; /* Enable rising-edge events */
788  vuint32_t IREE8:1; /* Enable rising-edge events */
789  vuint32_t IREE7:1; /* Enable rising-edge events */
790  vuint32_t IREE6:1; /* Enable rising-edge events */
791  vuint32_t IREE5:1; /* Enable rising-edge events */
792  vuint32_t IREE4:1; /* Enable rising-edge events */
793  vuint32_t IREE3:1; /* Enable rising-edge events */
794  vuint32_t IREE2:1; /* Enable rising-edge events */
795  vuint32_t IREE1:1; /* Enable rising-edge events */
796  vuint32_t IREE0:1; /* Enable rising-edge events */
797  } B;
798  } SIUL_IREER_32B_tag;
799 
800  typedef union { /* IFEER - Interrupt Falling-Edge Event Enable */
801  vuint32_t R;
802  struct {
803  vuint32_t IFEE31:1; /* Enable Falling Edge Events */
804  vuint32_t IFEE30:1; /* Enable Falling Edge Events */
805  vuint32_t IFEE29:1; /* Enable Falling Edge Events */
806  vuint32_t IFEE28:1; /* Enable Falling Edge Events */
807  vuint32_t IFEE27:1; /* Enable Falling Edge Events */
808  vuint32_t IFEE26:1; /* Enable Falling Edge Events */
809  vuint32_t IFEE25:1; /* Enable Falling Edge Events */
810  vuint32_t IFEE24:1; /* Enable Falling Edge Events */
811  vuint32_t IFEE23:1; /* Enable Falling Edge Events */
812  vuint32_t IFEE22:1; /* Enable Falling Edge Events */
813  vuint32_t IFEE21:1; /* Enable Falling Edge Events */
814  vuint32_t IFEE20:1; /* Enable Falling Edge Events */
815  vuint32_t IFEE19:1; /* Enable Falling Edge Events */
816  vuint32_t IFEE18:1; /* Enable Falling Edge Events */
817  vuint32_t IFEE17:1; /* Enable Falling Edge Events */
818  vuint32_t IFEE16:1; /* Enable Falling Edge Events */
819  vuint32_t IFEE15:1; /* Enable Falling Edge Events */
820  vuint32_t IFEE14:1; /* Enable Falling Edge Events */
821  vuint32_t IFEE13:1; /* Enable Falling Edge Events */
822  vuint32_t IFEE12:1; /* Enable Falling Edge Events */
823  vuint32_t IFEE11:1; /* Enable Falling Edge Events */
824  vuint32_t IFEE10:1; /* Enable Falling Edge Events */
825  vuint32_t IFEE9:1; /* Enable Falling Edge Events */
826  vuint32_t IFEE8:1; /* Enable Falling Edge Events */
827  vuint32_t IFEE7:1; /* Enable Falling Edge Events */
828  vuint32_t IFEE6:1; /* Enable Falling Edge Events */
829  vuint32_t IFEE5:1; /* Enable Falling Edge Events */
830  vuint32_t IFEE4:1; /* Enable Falling Edge Events */
831  vuint32_t IFEE3:1; /* Enable Falling Edge Events */
832  vuint32_t IFEE2:1; /* Enable Falling Edge Events */
833  vuint32_t IFEE1:1; /* Enable Falling Edge Events */
834  vuint32_t IFEE0:1; /* Enable Falling Edge Events */
835  } B;
836  } SIUL_IFEER_32B_tag;
837 
838  typedef union { /* IFER Interrupt Filter Enable Register */
839  vuint32_t R;
840  struct {
841  vuint32_t IFE31:1; /* Enable Digital Glitch Filter */
842  vuint32_t IFE30:1; /* Enable Digital Glitch Filter */
843  vuint32_t IFE29:1; /* Enable Digital Glitch Filter */
844  vuint32_t IFE28:1; /* Enable Digital Glitch Filter */
845  vuint32_t IFE27:1; /* Enable Digital Glitch Filter */
846  vuint32_t IFE26:1; /* Enable Digital Glitch Filter */
847  vuint32_t IFE25:1; /* Enable Digital Glitch Filter */
848  vuint32_t IFE24:1; /* Enable Digital Glitch Filter */
849  vuint32_t IFE23:1; /* Enable Digital Glitch Filter */
850  vuint32_t IFE22:1; /* Enable Digital Glitch Filter */
851  vuint32_t IFE21:1; /* Enable Digital Glitch Filter */
852  vuint32_t IFE20:1; /* Enable Digital Glitch Filter */
853  vuint32_t IFE19:1; /* Enable Digital Glitch Filter */
854  vuint32_t IFE18:1; /* Enable Digital Glitch Filter */
855  vuint32_t IFE17:1; /* Enable Digital Glitch Filter */
856  vuint32_t IFE16:1; /* Enable Digital Glitch Filter */
857  vuint32_t IFE15:1; /* Enable Digital Glitch Filter */
858  vuint32_t IFE14:1; /* Enable Digital Glitch Filter */
859  vuint32_t IFE13:1; /* Enable Digital Glitch Filter */
860  vuint32_t IFE12:1; /* Enable Digital Glitch Filter */
861  vuint32_t IFE11:1; /* Enable Digital Glitch Filter */
862  vuint32_t IFE10:1; /* Enable Digital Glitch Filter */
863  vuint32_t IFE9:1; /* Enable Digital Glitch Filter */
864  vuint32_t IFE8:1; /* Enable Digital Glitch Filter */
865  vuint32_t IFE7:1; /* Enable Digital Glitch Filter */
866  vuint32_t IFE6:1; /* Enable Digital Glitch Filter */
867  vuint32_t IFE5:1; /* Enable Digital Glitch Filter */
868  vuint32_t IFE4:1; /* Enable Digital Glitch Filter */
869  vuint32_t IFE3:1; /* Enable Digital Glitch Filter */
870  vuint32_t IFE2:1; /* Enable Digital Glitch Filter */
871  vuint32_t IFE1:1; /* Enable Digital Glitch Filter */
872  vuint32_t IFE0:1; /* Enable Digital Glitch Filter */
873  } B;
874  } SIUL_IFER_32B_tag;
875 
876 
877  /* Register layout for all registers PCR... */
878 
879  typedef union { /* PCR - Pad Configuration Register */
880  vuint16_t R;
881  struct {
882  vuint16_t:1;
883 #ifndef USE_FIELD_ALIASES_SIUL
884  vuint16_t SMC:1; /* Safe Mode Control */
885 #else
886  vuint16_t SME:1; /* deprecated name - please avoid */
887 #endif
888  vuint16_t APC:1; /* Analog Pad Control */
889  vuint16_t:1;
890  vuint16_t PA:2; /* Pad Output Assignment */
891  vuint16_t OBE:1; /* Output Buffer Enable */
892  vuint16_t IBE:1; /* Input Buffer Enable */
893 #ifndef USE_FIELD_ALIASES_SIUL
894  vuint16_t DSC:2; /* Drive Strength Control */
895 #else
896  vuint16_t DCS:2; /* deprecated name - please avoid */
897 #endif
898  vuint16_t ODE:1; /* Open Drain Output Enable */
899  vuint16_t HYS:1; /* Input Hysteresis */
900  vuint16_t SRC:2; /* Slew Rate Control */
901  vuint16_t WPE:1; /* Weak Pull Up/Down Enable */
902  vuint16_t WPS:1; /* Weak Pull Up/Down Select */
903  } B;
904  } SIUL_PCR_16B_tag;
905 
906 
907  /* Register layout for all registers PSMI... */
908 
909  typedef union { /* PSMI - Pad Selection for Multiplexed Inputs */
910  vuint8_t R;
911  struct {
912  vuint8_t:4;
913  vuint8_t PADSEL:4; /* Pad selection for pin */
914  } B;
915  } SIUL_PSMI_8B_tag;
916 
917 
918  /* Register layout for all registers PSMI... */
919 
920  typedef union { /* PSMI - Pad Selection for Multiplexed Inputs */
921  vuint32_t R;
922  struct {
923  vuint32_t:4;
924  vuint32_t PADSEL0:4; /* Pad selection for pin */
925  vuint32_t:4;
926  vuint32_t PADSEL1:4; /* Pad selection for pin */
927  vuint32_t:4;
928  vuint32_t PADSEL2:4; /* Pad selection for pin */
929  vuint32_t:4;
930  vuint32_t PADSEL3:4; /* Pad selection for pin */
931  } B;
932  } SIUL_PSMI_32B_tag;
933 
934 
935  /* Register layout for all registers GPDO... */
936 
937  typedef union { /* GPDO - GPIO Pad Data Output Register */
938  vuint8_t R;
939  struct {
940  vuint8_t:7;
941  vuint8_t PDO:1; /* Pad Data Out */
942  } B;
943  } SIUL_GPDO_8B_tag;
944 
945 
946  /* Register layout for all registers GPDO... */
947 
948  typedef union { /* GPDO - GPIO Pad Data Output Register */
949  vuint32_t R;
950  struct {
951  vuint32_t:7;
952  vuint32_t PDO0:1; /* Pad Data Out */
953  vuint32_t:7;
954  vuint32_t PDO1:1; /* Pad Data Out */
955  vuint32_t:7;
956  vuint32_t PDO2:1; /* Pad Data Out */
957  vuint32_t:7;
958  vuint32_t PDO3:1; /* Pad Data Out */
959  } B;
960  } SIUL_GPDO_32B_tag;
961 
962 
963  /* Register layout for all registers GPDI... */
964 
965  typedef union { /* GPDI - GPIO Pad Data Input Register */
966  vuint8_t R;
967  struct {
968  vuint8_t:7;
969  vuint8_t PDI:1; /* Pad Data In */
970  } B;
971  } SIUL_GPDI_8B_tag;
972 
973 
974  /* Register layout for all registers GPDI... */
975 
976  typedef union { /* GPDI - GPIO Pad Data Input Register */
977  vuint32_t R;
978  struct {
979  vuint32_t:7;
980  vuint32_t PDI0:1; /* Pad Data In */
981  vuint32_t:7;
982  vuint32_t PDI1:1; /* Pad Data In */
983  vuint32_t:7;
984  vuint32_t PDI2:1; /* Pad Data In */
985  vuint32_t:7;
986  vuint32_t PDI3:1; /* Pad Data In */
987  } B;
988  } SIUL_GPDI_32B_tag;
989 
990 
991  /* Register layout for all registers PGPDO... */
992 
993  typedef union { /* PGPDO - Parallel GPIO Pad Data Out Register */
994  vuint16_t R;
995  } SIUL_PGPDO_16B_tag;
996 
997 
998  /* Register layout for all registers PGPDI... */
999 
1000  typedef union { /* PGPDI - Parallel GPIO Pad Data In Register */
1001  vuint16_t R;
1002  } SIUL_PGPDI_16B_tag;
1003 
1004 
1005  /* Register layout for all registers MPGPDO... */
1006 
1007  typedef union { /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */
1008  vuint32_t R;
1009  struct {
1010  vuint32_t MASK:16; /* Mask Field */
1011  vuint32_t MPPDO:16; /* Masked Parallel Pad Data Out */
1012  } B;
1013  } SIUL_MPGPDO_32B_tag;
1014 
1015 
1016  /* Register layout for all registers IFMC... */
1017 
1018  typedef union { /* IFMC - Interrupt Filter Maximum Counter Register */
1019  vuint32_t R;
1020  struct {
1021  vuint32_t:28;
1022  vuint32_t MAXCNT:4; /* Maximum Interrupt Filter Counter Setting */
1023  } B;
1024  } SIUL_IFMC_32B_tag;
1025 
1026  typedef union { /* IFCPR - Inerrupt Filter Clock Prescaler Register */
1027  vuint32_t R;
1028  struct {
1029  vuint32_t:28;
1030  vuint32_t IFCP:4; /* Interrupt Filter Clock Prescaler Setting */
1031  } B;
1032  } SIUL_IFCPR_32B_tag;
1033 
1034 
1035 
1036  typedef struct SIUL_struct_tag { /* start of SIUL_tag */
1037  int8_t SIUL_reserved_0000_C[4];
1038  union {
1039  SIUL_MIDR1_32B_tag MIDR; /* deprecated - please avoid */
1040 
1041  /* MIDR1 - MCU ID Register #1 */
1042  SIUL_MIDR1_32B_tag MIDR1; /* offset: 0x0004 size: 32 bit */
1043 
1044  };
1045  /* MIDR2 - MCU ID Register #2 */
1046  SIUL_MIDR2_32B_tag MIDR2; /* offset: 0x0008 size: 32 bit */
1047  int8_t SIUL_reserved_000C[8];
1048  /* ISR - Interrupt Status Flag Register */
1049  SIUL_ISR_32B_tag ISR; /* offset: 0x0014 size: 32 bit */
1050  /* IRER - Interrupt Request Enable Register */
1051  SIUL_IRER_32B_tag IRER; /* offset: 0x0018 size: 32 bit */
1052  int8_t SIUL_reserved_001C[12];
1053  /* IREER - Interrupt Rising Edge Event Enable */
1054  SIUL_IREER_32B_tag IREER; /* offset: 0x0028 size: 32 bit */
1055  /* IFEER - Interrupt Falling-Edge Event Enable */
1056  SIUL_IFEER_32B_tag IFEER; /* offset: 0x002C size: 32 bit */
1057  /* IFER Interrupt Filter Enable Register */
1058  SIUL_IFER_32B_tag IFER; /* offset: 0x0030 size: 32 bit */
1059  int8_t SIUL_reserved_0034_C[12];
1060  union {
1061  /* PCR - Pad Configuration Register */
1062  SIUL_PCR_16B_tag PCR[512]; /* offset: 0x0040 (0x0002 x 512) */
1063 
1064  struct {
1065  /* PCR - Pad Configuration Register */
1066  SIUL_PCR_16B_tag PCR0; /* offset: 0x0040 size: 16 bit */
1067  SIUL_PCR_16B_tag PCR1; /* offset: 0x0042 size: 16 bit */
1068  SIUL_PCR_16B_tag PCR2; /* offset: 0x0044 size: 16 bit */
1069  SIUL_PCR_16B_tag PCR3; /* offset: 0x0046 size: 16 bit */
1070  SIUL_PCR_16B_tag PCR4; /* offset: 0x0048 size: 16 bit */
1071  SIUL_PCR_16B_tag PCR5; /* offset: 0x004A size: 16 bit */
1072  SIUL_PCR_16B_tag PCR6; /* offset: 0x004C size: 16 bit */
1073  SIUL_PCR_16B_tag PCR7; /* offset: 0x004E size: 16 bit */
1074  SIUL_PCR_16B_tag PCR8; /* offset: 0x0050 size: 16 bit */
1075  SIUL_PCR_16B_tag PCR9; /* offset: 0x0052 size: 16 bit */
1076  SIUL_PCR_16B_tag PCR10; /* offset: 0x0054 size: 16 bit */
1077  SIUL_PCR_16B_tag PCR11; /* offset: 0x0056 size: 16 bit */
1078  SIUL_PCR_16B_tag PCR12; /* offset: 0x0058 size: 16 bit */
1079  SIUL_PCR_16B_tag PCR13; /* offset: 0x005A size: 16 bit */
1080  SIUL_PCR_16B_tag PCR14; /* offset: 0x005C size: 16 bit */
1081  SIUL_PCR_16B_tag PCR15; /* offset: 0x005E size: 16 bit */
1082  SIUL_PCR_16B_tag PCR16; /* offset: 0x0060 size: 16 bit */
1083  SIUL_PCR_16B_tag PCR17; /* offset: 0x0062 size: 16 bit */
1084  SIUL_PCR_16B_tag PCR18; /* offset: 0x0064 size: 16 bit */
1085  SIUL_PCR_16B_tag PCR19; /* offset: 0x0066 size: 16 bit */
1086  SIUL_PCR_16B_tag PCR20; /* offset: 0x0068 size: 16 bit */
1087  SIUL_PCR_16B_tag PCR21; /* offset: 0x006A size: 16 bit */
1088  SIUL_PCR_16B_tag PCR22; /* offset: 0x006C size: 16 bit */
1089  SIUL_PCR_16B_tag PCR23; /* offset: 0x006E size: 16 bit */
1090  SIUL_PCR_16B_tag PCR24; /* offset: 0x0070 size: 16 bit */
1091  SIUL_PCR_16B_tag PCR25; /* offset: 0x0072 size: 16 bit */
1092  SIUL_PCR_16B_tag PCR26; /* offset: 0x0074 size: 16 bit */
1093  SIUL_PCR_16B_tag PCR27; /* offset: 0x0076 size: 16 bit */
1094  SIUL_PCR_16B_tag PCR28; /* offset: 0x0078 size: 16 bit */
1095  SIUL_PCR_16B_tag PCR29; /* offset: 0x007A size: 16 bit */
1096  SIUL_PCR_16B_tag PCR30; /* offset: 0x007C size: 16 bit */
1097  SIUL_PCR_16B_tag PCR31; /* offset: 0x007E size: 16 bit */
1098  SIUL_PCR_16B_tag PCR32; /* offset: 0x0080 size: 16 bit */
1099  SIUL_PCR_16B_tag PCR33; /* offset: 0x0082 size: 16 bit */
1100  SIUL_PCR_16B_tag PCR34; /* offset: 0x0084 size: 16 bit */
1101  SIUL_PCR_16B_tag PCR35; /* offset: 0x0086 size: 16 bit */
1102  SIUL_PCR_16B_tag PCR36; /* offset: 0x0088 size: 16 bit */
1103  SIUL_PCR_16B_tag PCR37; /* offset: 0x008A size: 16 bit */
1104  SIUL_PCR_16B_tag PCR38; /* offset: 0x008C size: 16 bit */
1105  SIUL_PCR_16B_tag PCR39; /* offset: 0x008E size: 16 bit */
1106  SIUL_PCR_16B_tag PCR40; /* offset: 0x0090 size: 16 bit */
1107  SIUL_PCR_16B_tag PCR41; /* offset: 0x0092 size: 16 bit */
1108  SIUL_PCR_16B_tag PCR42; /* offset: 0x0094 size: 16 bit */
1109  SIUL_PCR_16B_tag PCR43; /* offset: 0x0096 size: 16 bit */
1110  SIUL_PCR_16B_tag PCR44; /* offset: 0x0098 size: 16 bit */
1111  SIUL_PCR_16B_tag PCR45; /* offset: 0x009A size: 16 bit */
1112  SIUL_PCR_16B_tag PCR46; /* offset: 0x009C size: 16 bit */
1113  SIUL_PCR_16B_tag PCR47; /* offset: 0x009E size: 16 bit */
1114  SIUL_PCR_16B_tag PCR48; /* offset: 0x00A0 size: 16 bit */
1115  SIUL_PCR_16B_tag PCR49; /* offset: 0x00A2 size: 16 bit */
1116  SIUL_PCR_16B_tag PCR50; /* offset: 0x00A4 size: 16 bit */
1117  SIUL_PCR_16B_tag PCR51; /* offset: 0x00A6 size: 16 bit */
1118  SIUL_PCR_16B_tag PCR52; /* offset: 0x00A8 size: 16 bit */
1119  SIUL_PCR_16B_tag PCR53; /* offset: 0x00AA size: 16 bit */
1120  SIUL_PCR_16B_tag PCR54; /* offset: 0x00AC size: 16 bit */
1121  SIUL_PCR_16B_tag PCR55; /* offset: 0x00AE size: 16 bit */
1122  SIUL_PCR_16B_tag PCR56; /* offset: 0x00B0 size: 16 bit */
1123  SIUL_PCR_16B_tag PCR57; /* offset: 0x00B2 size: 16 bit */
1124  SIUL_PCR_16B_tag PCR58; /* offset: 0x00B4 size: 16 bit */
1125  SIUL_PCR_16B_tag PCR59; /* offset: 0x00B6 size: 16 bit */
1126  SIUL_PCR_16B_tag PCR60; /* offset: 0x00B8 size: 16 bit */
1127  SIUL_PCR_16B_tag PCR61; /* offset: 0x00BA size: 16 bit */
1128  SIUL_PCR_16B_tag PCR62; /* offset: 0x00BC size: 16 bit */
1129  SIUL_PCR_16B_tag PCR63; /* offset: 0x00BE size: 16 bit */
1130  SIUL_PCR_16B_tag PCR64; /* offset: 0x00C0 size: 16 bit */
1131  SIUL_PCR_16B_tag PCR65; /* offset: 0x00C2 size: 16 bit */
1132  SIUL_PCR_16B_tag PCR66; /* offset: 0x00C4 size: 16 bit */
1133  SIUL_PCR_16B_tag PCR67; /* offset: 0x00C6 size: 16 bit */
1134  SIUL_PCR_16B_tag PCR68; /* offset: 0x00C8 size: 16 bit */
1135  SIUL_PCR_16B_tag PCR69; /* offset: 0x00CA size: 16 bit */
1136  SIUL_PCR_16B_tag PCR70; /* offset: 0x00CC size: 16 bit */
1137  SIUL_PCR_16B_tag PCR71; /* offset: 0x00CE size: 16 bit */
1138  SIUL_PCR_16B_tag PCR72; /* offset: 0x00D0 size: 16 bit */
1139  SIUL_PCR_16B_tag PCR73; /* offset: 0x00D2 size: 16 bit */
1140  SIUL_PCR_16B_tag PCR74; /* offset: 0x00D4 size: 16 bit */
1141  SIUL_PCR_16B_tag PCR75; /* offset: 0x00D6 size: 16 bit */
1142  SIUL_PCR_16B_tag PCR76; /* offset: 0x00D8 size: 16 bit */
1143  SIUL_PCR_16B_tag PCR77; /* offset: 0x00DA size: 16 bit */
1144  SIUL_PCR_16B_tag PCR78; /* offset: 0x00DC size: 16 bit */
1145  SIUL_PCR_16B_tag PCR79; /* offset: 0x00DE size: 16 bit */
1146  SIUL_PCR_16B_tag PCR80; /* offset: 0x00E0 size: 16 bit */
1147  SIUL_PCR_16B_tag PCR81; /* offset: 0x00E2 size: 16 bit */
1148  SIUL_PCR_16B_tag PCR82; /* offset: 0x00E4 size: 16 bit */
1149  SIUL_PCR_16B_tag PCR83; /* offset: 0x00E6 size: 16 bit */
1150  SIUL_PCR_16B_tag PCR84; /* offset: 0x00E8 size: 16 bit */
1151  SIUL_PCR_16B_tag PCR85; /* offset: 0x00EA size: 16 bit */
1152  SIUL_PCR_16B_tag PCR86; /* offset: 0x00EC size: 16 bit */
1153  SIUL_PCR_16B_tag PCR87; /* offset: 0x00EE size: 16 bit */
1154  SIUL_PCR_16B_tag PCR88; /* offset: 0x00F0 size: 16 bit */
1155  SIUL_PCR_16B_tag PCR89; /* offset: 0x00F2 size: 16 bit */
1156  SIUL_PCR_16B_tag PCR90; /* offset: 0x00F4 size: 16 bit */
1157  SIUL_PCR_16B_tag PCR91; /* offset: 0x00F6 size: 16 bit */
1158  SIUL_PCR_16B_tag PCR92; /* offset: 0x00F8 size: 16 bit */
1159  SIUL_PCR_16B_tag PCR93; /* offset: 0x00FA size: 16 bit */
1160  SIUL_PCR_16B_tag PCR94; /* offset: 0x00FC size: 16 bit */
1161  SIUL_PCR_16B_tag PCR95; /* offset: 0x00FE size: 16 bit */
1162  SIUL_PCR_16B_tag PCR96; /* offset: 0x0100 size: 16 bit */
1163  SIUL_PCR_16B_tag PCR97; /* offset: 0x0102 size: 16 bit */
1164  SIUL_PCR_16B_tag PCR98; /* offset: 0x0104 size: 16 bit */
1165  SIUL_PCR_16B_tag PCR99; /* offset: 0x0106 size: 16 bit */
1166  SIUL_PCR_16B_tag PCR100; /* offset: 0x0108 size: 16 bit */
1167  SIUL_PCR_16B_tag PCR101; /* offset: 0x010A size: 16 bit */
1168  SIUL_PCR_16B_tag PCR102; /* offset: 0x010C size: 16 bit */
1169  SIUL_PCR_16B_tag PCR103; /* offset: 0x010E size: 16 bit */
1170  SIUL_PCR_16B_tag PCR104; /* offset: 0x0110 size: 16 bit */
1171  SIUL_PCR_16B_tag PCR105; /* offset: 0x0112 size: 16 bit */
1172  SIUL_PCR_16B_tag PCR106; /* offset: 0x0114 size: 16 bit */
1173  SIUL_PCR_16B_tag PCR107; /* offset: 0x0116 size: 16 bit */
1174  SIUL_PCR_16B_tag PCR108; /* offset: 0x0118 size: 16 bit */
1175  SIUL_PCR_16B_tag PCR109; /* offset: 0x011A size: 16 bit */
1176  SIUL_PCR_16B_tag PCR110; /* offset: 0x011C size: 16 bit */
1177  SIUL_PCR_16B_tag PCR111; /* offset: 0x011E size: 16 bit */
1178  SIUL_PCR_16B_tag PCR112; /* offset: 0x0120 size: 16 bit */
1179  SIUL_PCR_16B_tag PCR113; /* offset: 0x0122 size: 16 bit */
1180  SIUL_PCR_16B_tag PCR114; /* offset: 0x0124 size: 16 bit */
1181  SIUL_PCR_16B_tag PCR115; /* offset: 0x0126 size: 16 bit */
1182  SIUL_PCR_16B_tag PCR116; /* offset: 0x0128 size: 16 bit */
1183  SIUL_PCR_16B_tag PCR117; /* offset: 0x012A size: 16 bit */
1184  SIUL_PCR_16B_tag PCR118; /* offset: 0x012C size: 16 bit */
1185  SIUL_PCR_16B_tag PCR119; /* offset: 0x012E size: 16 bit */
1186  SIUL_PCR_16B_tag PCR120; /* offset: 0x0130 size: 16 bit */
1187  SIUL_PCR_16B_tag PCR121; /* offset: 0x0132 size: 16 bit */
1188  SIUL_PCR_16B_tag PCR122; /* offset: 0x0134 size: 16 bit */
1189  SIUL_PCR_16B_tag PCR123; /* offset: 0x0136 size: 16 bit */
1190  SIUL_PCR_16B_tag PCR124; /* offset: 0x0138 size: 16 bit */
1191  SIUL_PCR_16B_tag PCR125; /* offset: 0x013A size: 16 bit */
1192  SIUL_PCR_16B_tag PCR126; /* offset: 0x013C size: 16 bit */
1193  SIUL_PCR_16B_tag PCR127; /* offset: 0x013E size: 16 bit */
1194  SIUL_PCR_16B_tag PCR128; /* offset: 0x0140 size: 16 bit */
1195  SIUL_PCR_16B_tag PCR129; /* offset: 0x0142 size: 16 bit */
1196  SIUL_PCR_16B_tag PCR130; /* offset: 0x0144 size: 16 bit */
1197  SIUL_PCR_16B_tag PCR131; /* offset: 0x0146 size: 16 bit */
1198  SIUL_PCR_16B_tag PCR132; /* offset: 0x0148 size: 16 bit */
1199  SIUL_PCR_16B_tag PCR133; /* offset: 0x014A size: 16 bit */
1200  SIUL_PCR_16B_tag PCR134; /* offset: 0x014C size: 16 bit */
1201  SIUL_PCR_16B_tag PCR135; /* offset: 0x014E size: 16 bit */
1202  SIUL_PCR_16B_tag PCR136; /* offset: 0x0150 size: 16 bit */
1203  SIUL_PCR_16B_tag PCR137; /* offset: 0x0152 size: 16 bit */
1204  SIUL_PCR_16B_tag PCR138; /* offset: 0x0154 size: 16 bit */
1205  SIUL_PCR_16B_tag PCR139; /* offset: 0x0156 size: 16 bit */
1206  SIUL_PCR_16B_tag PCR140; /* offset: 0x0158 size: 16 bit */
1207  SIUL_PCR_16B_tag PCR141; /* offset: 0x015A size: 16 bit */
1208  SIUL_PCR_16B_tag PCR142; /* offset: 0x015C size: 16 bit */
1209  SIUL_PCR_16B_tag PCR143; /* offset: 0x015E size: 16 bit */
1210  SIUL_PCR_16B_tag PCR144; /* offset: 0x0160 size: 16 bit */
1211  SIUL_PCR_16B_tag PCR145; /* offset: 0x0162 size: 16 bit */
1212  SIUL_PCR_16B_tag PCR146; /* offset: 0x0164 size: 16 bit */
1213  SIUL_PCR_16B_tag PCR147; /* offset: 0x0166 size: 16 bit */
1214  SIUL_PCR_16B_tag PCR148; /* offset: 0x0168 size: 16 bit */
1215  SIUL_PCR_16B_tag PCR149; /* offset: 0x016A size: 16 bit */
1216  SIUL_PCR_16B_tag PCR150; /* offset: 0x016C size: 16 bit */
1217  SIUL_PCR_16B_tag PCR151; /* offset: 0x016E size: 16 bit */
1218  SIUL_PCR_16B_tag PCR152; /* offset: 0x0170 size: 16 bit */
1219  SIUL_PCR_16B_tag PCR153; /* offset: 0x0172 size: 16 bit */
1220  SIUL_PCR_16B_tag PCR154; /* offset: 0x0174 size: 16 bit */
1221  SIUL_PCR_16B_tag PCR155; /* offset: 0x0176 size: 16 bit */
1222  SIUL_PCR_16B_tag PCR156; /* offset: 0x0178 size: 16 bit */
1223  SIUL_PCR_16B_tag PCR157; /* offset: 0x017A size: 16 bit */
1224  SIUL_PCR_16B_tag PCR158; /* offset: 0x017C size: 16 bit */
1225  SIUL_PCR_16B_tag PCR159; /* offset: 0x017E size: 16 bit */
1226  SIUL_PCR_16B_tag PCR160; /* offset: 0x0180 size: 16 bit */
1227  SIUL_PCR_16B_tag PCR161; /* offset: 0x0182 size: 16 bit */
1228  SIUL_PCR_16B_tag PCR162; /* offset: 0x0184 size: 16 bit */
1229  SIUL_PCR_16B_tag PCR163; /* offset: 0x0186 size: 16 bit */
1230  SIUL_PCR_16B_tag PCR164; /* offset: 0x0188 size: 16 bit */
1231  SIUL_PCR_16B_tag PCR165; /* offset: 0x018A size: 16 bit */
1232  SIUL_PCR_16B_tag PCR166; /* offset: 0x018C size: 16 bit */
1233  SIUL_PCR_16B_tag PCR167; /* offset: 0x018E size: 16 bit */
1234  SIUL_PCR_16B_tag PCR168; /* offset: 0x0190 size: 16 bit */
1235  SIUL_PCR_16B_tag PCR169; /* offset: 0x0192 size: 16 bit */
1236  SIUL_PCR_16B_tag PCR170; /* offset: 0x0194 size: 16 bit */
1237  SIUL_PCR_16B_tag PCR171; /* offset: 0x0196 size: 16 bit */
1238  SIUL_PCR_16B_tag PCR172; /* offset: 0x0198 size: 16 bit */
1239  SIUL_PCR_16B_tag PCR173; /* offset: 0x019A size: 16 bit */
1240  SIUL_PCR_16B_tag PCR174; /* offset: 0x019C size: 16 bit */
1241  SIUL_PCR_16B_tag PCR175; /* offset: 0x019E size: 16 bit */
1242  SIUL_PCR_16B_tag PCR176; /* offset: 0x01A0 size: 16 bit */
1243  SIUL_PCR_16B_tag PCR177; /* offset: 0x01A2 size: 16 bit */
1244  SIUL_PCR_16B_tag PCR178; /* offset: 0x01A4 size: 16 bit */
1245  SIUL_PCR_16B_tag PCR179; /* offset: 0x01A6 size: 16 bit */
1246  SIUL_PCR_16B_tag PCR180; /* offset: 0x01A8 size: 16 bit */
1247  SIUL_PCR_16B_tag PCR181; /* offset: 0x01AA size: 16 bit */
1248  SIUL_PCR_16B_tag PCR182; /* offset: 0x01AC size: 16 bit */
1249  SIUL_PCR_16B_tag PCR183; /* offset: 0x01AE size: 16 bit */
1250  SIUL_PCR_16B_tag PCR184; /* offset: 0x01B0 size: 16 bit */
1251  SIUL_PCR_16B_tag PCR185; /* offset: 0x01B2 size: 16 bit */
1252  SIUL_PCR_16B_tag PCR186; /* offset: 0x01B4 size: 16 bit */
1253  SIUL_PCR_16B_tag PCR187; /* offset: 0x01B6 size: 16 bit */
1254  SIUL_PCR_16B_tag PCR188; /* offset: 0x01B8 size: 16 bit */
1255  SIUL_PCR_16B_tag PCR189; /* offset: 0x01BA size: 16 bit */
1256  SIUL_PCR_16B_tag PCR190; /* offset: 0x01BC size: 16 bit */
1257  SIUL_PCR_16B_tag PCR191; /* offset: 0x01BE size: 16 bit */
1258  SIUL_PCR_16B_tag PCR192; /* offset: 0x01C0 size: 16 bit */
1259  SIUL_PCR_16B_tag PCR193; /* offset: 0x01C2 size: 16 bit */
1260  SIUL_PCR_16B_tag PCR194; /* offset: 0x01C4 size: 16 bit */
1261  SIUL_PCR_16B_tag PCR195; /* offset: 0x01C6 size: 16 bit */
1262  SIUL_PCR_16B_tag PCR196; /* offset: 0x01C8 size: 16 bit */
1263  SIUL_PCR_16B_tag PCR197; /* offset: 0x01CA size: 16 bit */
1264  SIUL_PCR_16B_tag PCR198; /* offset: 0x01CC size: 16 bit */
1265  SIUL_PCR_16B_tag PCR199; /* offset: 0x01CE size: 16 bit */
1266  SIUL_PCR_16B_tag PCR200; /* offset: 0x01D0 size: 16 bit */
1267  SIUL_PCR_16B_tag PCR201; /* offset: 0x01D2 size: 16 bit */
1268  SIUL_PCR_16B_tag PCR202; /* offset: 0x01D4 size: 16 bit */
1269  SIUL_PCR_16B_tag PCR203; /* offset: 0x01D6 size: 16 bit */
1270  SIUL_PCR_16B_tag PCR204; /* offset: 0x01D8 size: 16 bit */
1271  SIUL_PCR_16B_tag PCR205; /* offset: 0x01DA size: 16 bit */
1272  SIUL_PCR_16B_tag PCR206; /* offset: 0x01DC size: 16 bit */
1273  SIUL_PCR_16B_tag PCR207; /* offset: 0x01DE size: 16 bit */
1274  SIUL_PCR_16B_tag PCR208; /* offset: 0x01E0 size: 16 bit */
1275  SIUL_PCR_16B_tag PCR209; /* offset: 0x01E2 size: 16 bit */
1276  SIUL_PCR_16B_tag PCR210; /* offset: 0x01E4 size: 16 bit */
1277  SIUL_PCR_16B_tag PCR211; /* offset: 0x01E6 size: 16 bit */
1278  SIUL_PCR_16B_tag PCR212; /* offset: 0x01E8 size: 16 bit */
1279  SIUL_PCR_16B_tag PCR213; /* offset: 0x01EA size: 16 bit */
1280  SIUL_PCR_16B_tag PCR214; /* offset: 0x01EC size: 16 bit */
1281  SIUL_PCR_16B_tag PCR215; /* offset: 0x01EE size: 16 bit */
1282  SIUL_PCR_16B_tag PCR216; /* offset: 0x01F0 size: 16 bit */
1283  SIUL_PCR_16B_tag PCR217; /* offset: 0x01F2 size: 16 bit */
1284  SIUL_PCR_16B_tag PCR218; /* offset: 0x01F4 size: 16 bit */
1285  SIUL_PCR_16B_tag PCR219; /* offset: 0x01F6 size: 16 bit */
1286  SIUL_PCR_16B_tag PCR220; /* offset: 0x01F8 size: 16 bit */
1287  SIUL_PCR_16B_tag PCR221; /* offset: 0x01FA size: 16 bit */
1288  SIUL_PCR_16B_tag PCR222; /* offset: 0x01FC size: 16 bit */
1289  SIUL_PCR_16B_tag PCR223; /* offset: 0x01FE size: 16 bit */
1290  SIUL_PCR_16B_tag PCR224; /* offset: 0x0200 size: 16 bit */
1291  SIUL_PCR_16B_tag PCR225; /* offset: 0x0202 size: 16 bit */
1292  SIUL_PCR_16B_tag PCR226; /* offset: 0x0204 size: 16 bit */
1293  SIUL_PCR_16B_tag PCR227; /* offset: 0x0206 size: 16 bit */
1294  SIUL_PCR_16B_tag PCR228; /* offset: 0x0208 size: 16 bit */
1295  SIUL_PCR_16B_tag PCR229; /* offset: 0x020A size: 16 bit */
1296  SIUL_PCR_16B_tag PCR230; /* offset: 0x020C size: 16 bit */
1297  SIUL_PCR_16B_tag PCR231; /* offset: 0x020E size: 16 bit */
1298  SIUL_PCR_16B_tag PCR232; /* offset: 0x0210 size: 16 bit */
1299  SIUL_PCR_16B_tag PCR233; /* offset: 0x0212 size: 16 bit */
1300  SIUL_PCR_16B_tag PCR234; /* offset: 0x0214 size: 16 bit */
1301  SIUL_PCR_16B_tag PCR235; /* offset: 0x0216 size: 16 bit */
1302  SIUL_PCR_16B_tag PCR236; /* offset: 0x0218 size: 16 bit */
1303  SIUL_PCR_16B_tag PCR237; /* offset: 0x021A size: 16 bit */
1304  SIUL_PCR_16B_tag PCR238; /* offset: 0x021C size: 16 bit */
1305  SIUL_PCR_16B_tag PCR239; /* offset: 0x021E size: 16 bit */
1306  SIUL_PCR_16B_tag PCR240; /* offset: 0x0220 size: 16 bit */
1307  SIUL_PCR_16B_tag PCR241; /* offset: 0x0222 size: 16 bit */
1308  SIUL_PCR_16B_tag PCR242; /* offset: 0x0224 size: 16 bit */
1309  SIUL_PCR_16B_tag PCR243; /* offset: 0x0226 size: 16 bit */
1310  SIUL_PCR_16B_tag PCR244; /* offset: 0x0228 size: 16 bit */
1311  SIUL_PCR_16B_tag PCR245; /* offset: 0x022A size: 16 bit */
1312  SIUL_PCR_16B_tag PCR246; /* offset: 0x022C size: 16 bit */
1313  SIUL_PCR_16B_tag PCR247; /* offset: 0x022E size: 16 bit */
1314  SIUL_PCR_16B_tag PCR248; /* offset: 0x0230 size: 16 bit */
1315  SIUL_PCR_16B_tag PCR249; /* offset: 0x0232 size: 16 bit */
1316  SIUL_PCR_16B_tag PCR250; /* offset: 0x0234 size: 16 bit */
1317  SIUL_PCR_16B_tag PCR251; /* offset: 0x0236 size: 16 bit */
1318  SIUL_PCR_16B_tag PCR252; /* offset: 0x0238 size: 16 bit */
1319  SIUL_PCR_16B_tag PCR253; /* offset: 0x023A size: 16 bit */
1320  SIUL_PCR_16B_tag PCR254; /* offset: 0x023C size: 16 bit */
1321  SIUL_PCR_16B_tag PCR255; /* offset: 0x023E size: 16 bit */
1322  SIUL_PCR_16B_tag PCR256; /* offset: 0x0240 size: 16 bit */
1323  SIUL_PCR_16B_tag PCR257; /* offset: 0x0242 size: 16 bit */
1324  SIUL_PCR_16B_tag PCR258; /* offset: 0x0244 size: 16 bit */
1325  SIUL_PCR_16B_tag PCR259; /* offset: 0x0246 size: 16 bit */
1326  SIUL_PCR_16B_tag PCR260; /* offset: 0x0248 size: 16 bit */
1327  SIUL_PCR_16B_tag PCR261; /* offset: 0x024A size: 16 bit */
1328  SIUL_PCR_16B_tag PCR262; /* offset: 0x024C size: 16 bit */
1329  SIUL_PCR_16B_tag PCR263; /* offset: 0x024E size: 16 bit */
1330  SIUL_PCR_16B_tag PCR264; /* offset: 0x0250 size: 16 bit */
1331  SIUL_PCR_16B_tag PCR265; /* offset: 0x0252 size: 16 bit */
1332  SIUL_PCR_16B_tag PCR266; /* offset: 0x0254 size: 16 bit */
1333  SIUL_PCR_16B_tag PCR267; /* offset: 0x0256 size: 16 bit */
1334  SIUL_PCR_16B_tag PCR268; /* offset: 0x0258 size: 16 bit */
1335  SIUL_PCR_16B_tag PCR269; /* offset: 0x025A size: 16 bit */
1336  SIUL_PCR_16B_tag PCR270; /* offset: 0x025C size: 16 bit */
1337  SIUL_PCR_16B_tag PCR271; /* offset: 0x025E size: 16 bit */
1338  SIUL_PCR_16B_tag PCR272; /* offset: 0x0260 size: 16 bit */
1339  SIUL_PCR_16B_tag PCR273; /* offset: 0x0262 size: 16 bit */
1340  SIUL_PCR_16B_tag PCR274; /* offset: 0x0264 size: 16 bit */
1341  SIUL_PCR_16B_tag PCR275; /* offset: 0x0266 size: 16 bit */
1342  SIUL_PCR_16B_tag PCR276; /* offset: 0x0268 size: 16 bit */
1343  SIUL_PCR_16B_tag PCR277; /* offset: 0x026A size: 16 bit */
1344  SIUL_PCR_16B_tag PCR278; /* offset: 0x026C size: 16 bit */
1345  SIUL_PCR_16B_tag PCR279; /* offset: 0x026E size: 16 bit */
1346  SIUL_PCR_16B_tag PCR280; /* offset: 0x0270 size: 16 bit */
1347  SIUL_PCR_16B_tag PCR281; /* offset: 0x0272 size: 16 bit */
1348  SIUL_PCR_16B_tag PCR282; /* offset: 0x0274 size: 16 bit */
1349  SIUL_PCR_16B_tag PCR283; /* offset: 0x0276 size: 16 bit */
1350  SIUL_PCR_16B_tag PCR284; /* offset: 0x0278 size: 16 bit */
1351  SIUL_PCR_16B_tag PCR285; /* offset: 0x027A size: 16 bit */
1352  SIUL_PCR_16B_tag PCR286; /* offset: 0x027C size: 16 bit */
1353  SIUL_PCR_16B_tag PCR287; /* offset: 0x027E size: 16 bit */
1354  SIUL_PCR_16B_tag PCR288; /* offset: 0x0280 size: 16 bit */
1355  SIUL_PCR_16B_tag PCR289; /* offset: 0x0282 size: 16 bit */
1356  SIUL_PCR_16B_tag PCR290; /* offset: 0x0284 size: 16 bit */
1357  SIUL_PCR_16B_tag PCR291; /* offset: 0x0286 size: 16 bit */
1358  SIUL_PCR_16B_tag PCR292; /* offset: 0x0288 size: 16 bit */
1359  SIUL_PCR_16B_tag PCR293; /* offset: 0x028A size: 16 bit */
1360  SIUL_PCR_16B_tag PCR294; /* offset: 0x028C size: 16 bit */
1361  SIUL_PCR_16B_tag PCR295; /* offset: 0x028E size: 16 bit */
1362  SIUL_PCR_16B_tag PCR296; /* offset: 0x0290 size: 16 bit */
1363  SIUL_PCR_16B_tag PCR297; /* offset: 0x0292 size: 16 bit */
1364  SIUL_PCR_16B_tag PCR298; /* offset: 0x0294 size: 16 bit */
1365  SIUL_PCR_16B_tag PCR299; /* offset: 0x0296 size: 16 bit */
1366  SIUL_PCR_16B_tag PCR300; /* offset: 0x0298 size: 16 bit */
1367  SIUL_PCR_16B_tag PCR301; /* offset: 0x029A size: 16 bit */
1368  SIUL_PCR_16B_tag PCR302; /* offset: 0x029C size: 16 bit */
1369  SIUL_PCR_16B_tag PCR303; /* offset: 0x029E size: 16 bit */
1370  SIUL_PCR_16B_tag PCR304; /* offset: 0x02A0 size: 16 bit */
1371  SIUL_PCR_16B_tag PCR305; /* offset: 0x02A2 size: 16 bit */
1372  SIUL_PCR_16B_tag PCR306; /* offset: 0x02A4 size: 16 bit */
1373  SIUL_PCR_16B_tag PCR307; /* offset: 0x02A6 size: 16 bit */
1374  SIUL_PCR_16B_tag PCR308; /* offset: 0x02A8 size: 16 bit */
1375  SIUL_PCR_16B_tag PCR309; /* offset: 0x02AA size: 16 bit */
1376  SIUL_PCR_16B_tag PCR310; /* offset: 0x02AC size: 16 bit */
1377  SIUL_PCR_16B_tag PCR311; /* offset: 0x02AE size: 16 bit */
1378  SIUL_PCR_16B_tag PCR312; /* offset: 0x02B0 size: 16 bit */
1379  SIUL_PCR_16B_tag PCR313; /* offset: 0x02B2 size: 16 bit */
1380  SIUL_PCR_16B_tag PCR314; /* offset: 0x02B4 size: 16 bit */
1381  SIUL_PCR_16B_tag PCR315; /* offset: 0x02B6 size: 16 bit */
1382  SIUL_PCR_16B_tag PCR316; /* offset: 0x02B8 size: 16 bit */
1383  SIUL_PCR_16B_tag PCR317; /* offset: 0x02BA size: 16 bit */
1384  SIUL_PCR_16B_tag PCR318; /* offset: 0x02BC size: 16 bit */
1385  SIUL_PCR_16B_tag PCR319; /* offset: 0x02BE size: 16 bit */
1386  SIUL_PCR_16B_tag PCR320; /* offset: 0x02C0 size: 16 bit */
1387  SIUL_PCR_16B_tag PCR321; /* offset: 0x02C2 size: 16 bit */
1388  SIUL_PCR_16B_tag PCR322; /* offset: 0x02C4 size: 16 bit */
1389  SIUL_PCR_16B_tag PCR323; /* offset: 0x02C6 size: 16 bit */
1390  SIUL_PCR_16B_tag PCR324; /* offset: 0x02C8 size: 16 bit */
1391  SIUL_PCR_16B_tag PCR325; /* offset: 0x02CA size: 16 bit */
1392  SIUL_PCR_16B_tag PCR326; /* offset: 0x02CC size: 16 bit */
1393  SIUL_PCR_16B_tag PCR327; /* offset: 0x02CE size: 16 bit */
1394  SIUL_PCR_16B_tag PCR328; /* offset: 0x02D0 size: 16 bit */
1395  SIUL_PCR_16B_tag PCR329; /* offset: 0x02D2 size: 16 bit */
1396  SIUL_PCR_16B_tag PCR330; /* offset: 0x02D4 size: 16 bit */
1397  SIUL_PCR_16B_tag PCR331; /* offset: 0x02D6 size: 16 bit */
1398  SIUL_PCR_16B_tag PCR332; /* offset: 0x02D8 size: 16 bit */
1399  SIUL_PCR_16B_tag PCR333; /* offset: 0x02DA size: 16 bit */
1400  SIUL_PCR_16B_tag PCR334; /* offset: 0x02DC size: 16 bit */
1401  SIUL_PCR_16B_tag PCR335; /* offset: 0x02DE size: 16 bit */
1402  SIUL_PCR_16B_tag PCR336; /* offset: 0x02E0 size: 16 bit */
1403  SIUL_PCR_16B_tag PCR337; /* offset: 0x02E2 size: 16 bit */
1404  SIUL_PCR_16B_tag PCR338; /* offset: 0x02E4 size: 16 bit */
1405  SIUL_PCR_16B_tag PCR339; /* offset: 0x02E6 size: 16 bit */
1406  SIUL_PCR_16B_tag PCR340; /* offset: 0x02E8 size: 16 bit */
1407  SIUL_PCR_16B_tag PCR341; /* offset: 0x02EA size: 16 bit */
1408  SIUL_PCR_16B_tag PCR342; /* offset: 0x02EC size: 16 bit */
1409  SIUL_PCR_16B_tag PCR343; /* offset: 0x02EE size: 16 bit */
1410  SIUL_PCR_16B_tag PCR344; /* offset: 0x02F0 size: 16 bit */
1411  SIUL_PCR_16B_tag PCR345; /* offset: 0x02F2 size: 16 bit */
1412  SIUL_PCR_16B_tag PCR346; /* offset: 0x02F4 size: 16 bit */
1413  SIUL_PCR_16B_tag PCR347; /* offset: 0x02F6 size: 16 bit */
1414  SIUL_PCR_16B_tag PCR348; /* offset: 0x02F8 size: 16 bit */
1415  SIUL_PCR_16B_tag PCR349; /* offset: 0x02FA size: 16 bit */
1416  SIUL_PCR_16B_tag PCR350; /* offset: 0x02FC size: 16 bit */
1417  SIUL_PCR_16B_tag PCR351; /* offset: 0x02FE size: 16 bit */
1418  SIUL_PCR_16B_tag PCR352; /* offset: 0x0300 size: 16 bit */
1419  SIUL_PCR_16B_tag PCR353; /* offset: 0x0302 size: 16 bit */
1420  SIUL_PCR_16B_tag PCR354; /* offset: 0x0304 size: 16 bit */
1421  SIUL_PCR_16B_tag PCR355; /* offset: 0x0306 size: 16 bit */
1422  SIUL_PCR_16B_tag PCR356; /* offset: 0x0308 size: 16 bit */
1423  SIUL_PCR_16B_tag PCR357; /* offset: 0x030A size: 16 bit */
1424  SIUL_PCR_16B_tag PCR358; /* offset: 0x030C size: 16 bit */
1425  SIUL_PCR_16B_tag PCR359; /* offset: 0x030E size: 16 bit */
1426  SIUL_PCR_16B_tag PCR360; /* offset: 0x0310 size: 16 bit */
1427  SIUL_PCR_16B_tag PCR361; /* offset: 0x0312 size: 16 bit */
1428  SIUL_PCR_16B_tag PCR362; /* offset: 0x0314 size: 16 bit */
1429  SIUL_PCR_16B_tag PCR363; /* offset: 0x0316 size: 16 bit */
1430  SIUL_PCR_16B_tag PCR364; /* offset: 0x0318 size: 16 bit */
1431  SIUL_PCR_16B_tag PCR365; /* offset: 0x031A size: 16 bit */
1432  SIUL_PCR_16B_tag PCR366; /* offset: 0x031C size: 16 bit */
1433  SIUL_PCR_16B_tag PCR367; /* offset: 0x031E size: 16 bit */
1434  SIUL_PCR_16B_tag PCR368; /* offset: 0x0320 size: 16 bit */
1435  SIUL_PCR_16B_tag PCR369; /* offset: 0x0322 size: 16 bit */
1436  SIUL_PCR_16B_tag PCR370; /* offset: 0x0324 size: 16 bit */
1437  SIUL_PCR_16B_tag PCR371; /* offset: 0x0326 size: 16 bit */
1438  SIUL_PCR_16B_tag PCR372; /* offset: 0x0328 size: 16 bit */
1439  SIUL_PCR_16B_tag PCR373; /* offset: 0x032A size: 16 bit */
1440  SIUL_PCR_16B_tag PCR374; /* offset: 0x032C size: 16 bit */
1441  SIUL_PCR_16B_tag PCR375; /* offset: 0x032E size: 16 bit */
1442  SIUL_PCR_16B_tag PCR376; /* offset: 0x0330 size: 16 bit */
1443  SIUL_PCR_16B_tag PCR377; /* offset: 0x0332 size: 16 bit */
1444  SIUL_PCR_16B_tag PCR378; /* offset: 0x0334 size: 16 bit */
1445  SIUL_PCR_16B_tag PCR379; /* offset: 0x0336 size: 16 bit */
1446  SIUL_PCR_16B_tag PCR380; /* offset: 0x0338 size: 16 bit */
1447  SIUL_PCR_16B_tag PCR381; /* offset: 0x033A size: 16 bit */
1448  SIUL_PCR_16B_tag PCR382; /* offset: 0x033C size: 16 bit */
1449  SIUL_PCR_16B_tag PCR383; /* offset: 0x033E size: 16 bit */
1450  SIUL_PCR_16B_tag PCR384; /* offset: 0x0340 size: 16 bit */
1451  SIUL_PCR_16B_tag PCR385; /* offset: 0x0342 size: 16 bit */
1452  SIUL_PCR_16B_tag PCR386; /* offset: 0x0344 size: 16 bit */
1453  SIUL_PCR_16B_tag PCR387; /* offset: 0x0346 size: 16 bit */
1454  SIUL_PCR_16B_tag PCR388; /* offset: 0x0348 size: 16 bit */
1455  SIUL_PCR_16B_tag PCR389; /* offset: 0x034A size: 16 bit */
1456  SIUL_PCR_16B_tag PCR390; /* offset: 0x034C size: 16 bit */
1457  SIUL_PCR_16B_tag PCR391; /* offset: 0x034E size: 16 bit */
1458  SIUL_PCR_16B_tag PCR392; /* offset: 0x0350 size: 16 bit */
1459  SIUL_PCR_16B_tag PCR393; /* offset: 0x0352 size: 16 bit */
1460  SIUL_PCR_16B_tag PCR394; /* offset: 0x0354 size: 16 bit */
1461  SIUL_PCR_16B_tag PCR395; /* offset: 0x0356 size: 16 bit */
1462  SIUL_PCR_16B_tag PCR396; /* offset: 0x0358 size: 16 bit */
1463  SIUL_PCR_16B_tag PCR397; /* offset: 0x035A size: 16 bit */
1464  SIUL_PCR_16B_tag PCR398; /* offset: 0x035C size: 16 bit */
1465  SIUL_PCR_16B_tag PCR399; /* offset: 0x035E size: 16 bit */
1466  SIUL_PCR_16B_tag PCR400; /* offset: 0x0360 size: 16 bit */
1467  SIUL_PCR_16B_tag PCR401; /* offset: 0x0362 size: 16 bit */
1468  SIUL_PCR_16B_tag PCR402; /* offset: 0x0364 size: 16 bit */
1469  SIUL_PCR_16B_tag PCR403; /* offset: 0x0366 size: 16 bit */
1470  SIUL_PCR_16B_tag PCR404; /* offset: 0x0368 size: 16 bit */
1471  SIUL_PCR_16B_tag PCR405; /* offset: 0x036A size: 16 bit */
1472  SIUL_PCR_16B_tag PCR406; /* offset: 0x036C size: 16 bit */
1473  SIUL_PCR_16B_tag PCR407; /* offset: 0x036E size: 16 bit */
1474  SIUL_PCR_16B_tag PCR408; /* offset: 0x0370 size: 16 bit */
1475  SIUL_PCR_16B_tag PCR409; /* offset: 0x0372 size: 16 bit */
1476  SIUL_PCR_16B_tag PCR410; /* offset: 0x0374 size: 16 bit */
1477  SIUL_PCR_16B_tag PCR411; /* offset: 0x0376 size: 16 bit */
1478  SIUL_PCR_16B_tag PCR412; /* offset: 0x0378 size: 16 bit */
1479  SIUL_PCR_16B_tag PCR413; /* offset: 0x037A size: 16 bit */
1480  SIUL_PCR_16B_tag PCR414; /* offset: 0x037C size: 16 bit */
1481  SIUL_PCR_16B_tag PCR415; /* offset: 0x037E size: 16 bit */
1482  SIUL_PCR_16B_tag PCR416; /* offset: 0x0380 size: 16 bit */
1483  SIUL_PCR_16B_tag PCR417; /* offset: 0x0382 size: 16 bit */
1484  SIUL_PCR_16B_tag PCR418; /* offset: 0x0384 size: 16 bit */
1485  SIUL_PCR_16B_tag PCR419; /* offset: 0x0386 size: 16 bit */
1486  SIUL_PCR_16B_tag PCR420; /* offset: 0x0388 size: 16 bit */
1487  SIUL_PCR_16B_tag PCR421; /* offset: 0x038A size: 16 bit */
1488  SIUL_PCR_16B_tag PCR422; /* offset: 0x038C size: 16 bit */
1489  SIUL_PCR_16B_tag PCR423; /* offset: 0x038E size: 16 bit */
1490  SIUL_PCR_16B_tag PCR424; /* offset: 0x0390 size: 16 bit */
1491  SIUL_PCR_16B_tag PCR425; /* offset: 0x0392 size: 16 bit */
1492  SIUL_PCR_16B_tag PCR426; /* offset: 0x0394 size: 16 bit */
1493  SIUL_PCR_16B_tag PCR427; /* offset: 0x0396 size: 16 bit */
1494  SIUL_PCR_16B_tag PCR428; /* offset: 0x0398 size: 16 bit */
1495  SIUL_PCR_16B_tag PCR429; /* offset: 0x039A size: 16 bit */
1496  SIUL_PCR_16B_tag PCR430; /* offset: 0x039C size: 16 bit */
1497  SIUL_PCR_16B_tag PCR431; /* offset: 0x039E size: 16 bit */
1498  SIUL_PCR_16B_tag PCR432; /* offset: 0x03A0 size: 16 bit */
1499  SIUL_PCR_16B_tag PCR433; /* offset: 0x03A2 size: 16 bit */
1500  SIUL_PCR_16B_tag PCR434; /* offset: 0x03A4 size: 16 bit */
1501  SIUL_PCR_16B_tag PCR435; /* offset: 0x03A6 size: 16 bit */
1502  SIUL_PCR_16B_tag PCR436; /* offset: 0x03A8 size: 16 bit */
1503  SIUL_PCR_16B_tag PCR437; /* offset: 0x03AA size: 16 bit */
1504  SIUL_PCR_16B_tag PCR438; /* offset: 0x03AC size: 16 bit */
1505  SIUL_PCR_16B_tag PCR439; /* offset: 0x03AE size: 16 bit */
1506  SIUL_PCR_16B_tag PCR440; /* offset: 0x03B0 size: 16 bit */
1507  SIUL_PCR_16B_tag PCR441; /* offset: 0x03B2 size: 16 bit */
1508  SIUL_PCR_16B_tag PCR442; /* offset: 0x03B4 size: 16 bit */
1509  SIUL_PCR_16B_tag PCR443; /* offset: 0x03B6 size: 16 bit */
1510  SIUL_PCR_16B_tag PCR444; /* offset: 0x03B8 size: 16 bit */
1511  SIUL_PCR_16B_tag PCR445; /* offset: 0x03BA size: 16 bit */
1512  SIUL_PCR_16B_tag PCR446; /* offset: 0x03BC size: 16 bit */
1513  SIUL_PCR_16B_tag PCR447; /* offset: 0x03BE size: 16 bit */
1514  SIUL_PCR_16B_tag PCR448; /* offset: 0x03C0 size: 16 bit */
1515  SIUL_PCR_16B_tag PCR449; /* offset: 0x03C2 size: 16 bit */
1516  SIUL_PCR_16B_tag PCR450; /* offset: 0x03C4 size: 16 bit */
1517  SIUL_PCR_16B_tag PCR451; /* offset: 0x03C6 size: 16 bit */
1518  SIUL_PCR_16B_tag PCR452; /* offset: 0x03C8 size: 16 bit */
1519  SIUL_PCR_16B_tag PCR453; /* offset: 0x03CA size: 16 bit */
1520  SIUL_PCR_16B_tag PCR454; /* offset: 0x03CC size: 16 bit */
1521  SIUL_PCR_16B_tag PCR455; /* offset: 0x03CE size: 16 bit */
1522  SIUL_PCR_16B_tag PCR456; /* offset: 0x03D0 size: 16 bit */
1523  SIUL_PCR_16B_tag PCR457; /* offset: 0x03D2 size: 16 bit */
1524  SIUL_PCR_16B_tag PCR458; /* offset: 0x03D4 size: 16 bit */
1525  SIUL_PCR_16B_tag PCR459; /* offset: 0x03D6 size: 16 bit */
1526  SIUL_PCR_16B_tag PCR460; /* offset: 0x03D8 size: 16 bit */
1527  SIUL_PCR_16B_tag PCR461; /* offset: 0x03DA size: 16 bit */
1528  SIUL_PCR_16B_tag PCR462; /* offset: 0x03DC size: 16 bit */
1529  SIUL_PCR_16B_tag PCR463; /* offset: 0x03DE size: 16 bit */
1530  SIUL_PCR_16B_tag PCR464; /* offset: 0x03E0 size: 16 bit */
1531  SIUL_PCR_16B_tag PCR465; /* offset: 0x03E2 size: 16 bit */
1532  SIUL_PCR_16B_tag PCR466; /* offset: 0x03E4 size: 16 bit */
1533  SIUL_PCR_16B_tag PCR467; /* offset: 0x03E6 size: 16 bit */
1534  SIUL_PCR_16B_tag PCR468; /* offset: 0x03E8 size: 16 bit */
1535  SIUL_PCR_16B_tag PCR469; /* offset: 0x03EA size: 16 bit */
1536  SIUL_PCR_16B_tag PCR470; /* offset: 0x03EC size: 16 bit */
1537  SIUL_PCR_16B_tag PCR471; /* offset: 0x03EE size: 16 bit */
1538  SIUL_PCR_16B_tag PCR472; /* offset: 0x03F0 size: 16 bit */
1539  SIUL_PCR_16B_tag PCR473; /* offset: 0x03F2 size: 16 bit */
1540  SIUL_PCR_16B_tag PCR474; /* offset: 0x03F4 size: 16 bit */
1541  SIUL_PCR_16B_tag PCR475; /* offset: 0x03F6 size: 16 bit */
1542  SIUL_PCR_16B_tag PCR476; /* offset: 0x03F8 size: 16 bit */
1543  SIUL_PCR_16B_tag PCR477; /* offset: 0x03FA size: 16 bit */
1544  SIUL_PCR_16B_tag PCR478; /* offset: 0x03FC size: 16 bit */
1545  SIUL_PCR_16B_tag PCR479; /* offset: 0x03FE size: 16 bit */
1546  SIUL_PCR_16B_tag PCR480; /* offset: 0x0400 size: 16 bit */
1547  SIUL_PCR_16B_tag PCR481; /* offset: 0x0402 size: 16 bit */
1548  SIUL_PCR_16B_tag PCR482; /* offset: 0x0404 size: 16 bit */
1549  SIUL_PCR_16B_tag PCR483; /* offset: 0x0406 size: 16 bit */
1550  SIUL_PCR_16B_tag PCR484; /* offset: 0x0408 size: 16 bit */
1551  SIUL_PCR_16B_tag PCR485; /* offset: 0x040A size: 16 bit */
1552  SIUL_PCR_16B_tag PCR486; /* offset: 0x040C size: 16 bit */
1553  SIUL_PCR_16B_tag PCR487; /* offset: 0x040E size: 16 bit */
1554  SIUL_PCR_16B_tag PCR488; /* offset: 0x0410 size: 16 bit */
1555  SIUL_PCR_16B_tag PCR489; /* offset: 0x0412 size: 16 bit */
1556  SIUL_PCR_16B_tag PCR490; /* offset: 0x0414 size: 16 bit */
1557  SIUL_PCR_16B_tag PCR491; /* offset: 0x0416 size: 16 bit */
1558  SIUL_PCR_16B_tag PCR492; /* offset: 0x0418 size: 16 bit */
1559  SIUL_PCR_16B_tag PCR493; /* offset: 0x041A size: 16 bit */
1560  SIUL_PCR_16B_tag PCR494; /* offset: 0x041C size: 16 bit */
1561  SIUL_PCR_16B_tag PCR495; /* offset: 0x041E size: 16 bit */
1562  SIUL_PCR_16B_tag PCR496; /* offset: 0x0420 size: 16 bit */
1563  SIUL_PCR_16B_tag PCR497; /* offset: 0x0422 size: 16 bit */
1564  SIUL_PCR_16B_tag PCR498; /* offset: 0x0424 size: 16 bit */
1565  SIUL_PCR_16B_tag PCR499; /* offset: 0x0426 size: 16 bit */
1566  SIUL_PCR_16B_tag PCR500; /* offset: 0x0428 size: 16 bit */
1567  SIUL_PCR_16B_tag PCR501; /* offset: 0x042A size: 16 bit */
1568  SIUL_PCR_16B_tag PCR502; /* offset: 0x042C size: 16 bit */
1569  SIUL_PCR_16B_tag PCR503; /* offset: 0x042E size: 16 bit */
1570  SIUL_PCR_16B_tag PCR504; /* offset: 0x0430 size: 16 bit */
1571  SIUL_PCR_16B_tag PCR505; /* offset: 0x0432 size: 16 bit */
1572  SIUL_PCR_16B_tag PCR506; /* offset: 0x0434 size: 16 bit */
1573  SIUL_PCR_16B_tag PCR507; /* offset: 0x0436 size: 16 bit */
1574  SIUL_PCR_16B_tag PCR508; /* offset: 0x0438 size: 16 bit */
1575  SIUL_PCR_16B_tag PCR509; /* offset: 0x043A size: 16 bit */
1576  SIUL_PCR_16B_tag PCR510; /* offset: 0x043C size: 16 bit */
1577  SIUL_PCR_16B_tag PCR511; /* offset: 0x043E size: 16 bit */
1578  };
1579 
1580  };
1581  int8_t SIUL_reserved_0440_C[192];
1582  union {
1583  /* PSMI - Pad Selection for Multiplexed Inputs */
1584  SIUL_PSMI_32B_tag PSMI_32B[64]; /* offset: 0x0500 (0x0004 x 64) */
1585 
1586  /* PSMI - Pad Selection for Multiplexed Inputs */
1587  SIUL_PSMI_8B_tag PSMI[256]; /* offset: 0x0500 (0x0001 x 256) */
1588 
1589  struct {
1590  /* PSMI - Pad Selection for Multiplexed Inputs */
1591  SIUL_PSMI_32B_tag PSMI0_3; /* offset: 0x0500 size: 32 bit */
1592  SIUL_PSMI_32B_tag PSMI4_7; /* offset: 0x0504 size: 32 bit */
1593  SIUL_PSMI_32B_tag PSMI8_11; /* offset: 0x0508 size: 32 bit */
1594  SIUL_PSMI_32B_tag PSMI12_15; /* offset: 0x050C size: 32 bit */
1595  SIUL_PSMI_32B_tag PSMI16_19; /* offset: 0x0510 size: 32 bit */
1596  SIUL_PSMI_32B_tag PSMI20_23; /* offset: 0x0514 size: 32 bit */
1597  SIUL_PSMI_32B_tag PSMI24_27; /* offset: 0x0518 size: 32 bit */
1598  SIUL_PSMI_32B_tag PSMI28_31; /* offset: 0x051C size: 32 bit */
1599  SIUL_PSMI_32B_tag PSMI32_35; /* offset: 0x0520 size: 32 bit */
1600  SIUL_PSMI_32B_tag PSMI36_39; /* offset: 0x0524 size: 32 bit */
1601  SIUL_PSMI_32B_tag PSMI40_43; /* offset: 0x0528 size: 32 bit */
1602  SIUL_PSMI_32B_tag PSMI44_47; /* offset: 0x052C size: 32 bit */
1603  SIUL_PSMI_32B_tag PSMI48_51; /* offset: 0x0530 size: 32 bit */
1604  SIUL_PSMI_32B_tag PSMI52_55; /* offset: 0x0534 size: 32 bit */
1605  SIUL_PSMI_32B_tag PSMI56_59; /* offset: 0x0538 size: 32 bit */
1606  SIUL_PSMI_32B_tag PSMI60_63; /* offset: 0x053C size: 32 bit */
1607  SIUL_PSMI_32B_tag PSMI64_67; /* offset: 0x0540 size: 32 bit */
1608  SIUL_PSMI_32B_tag PSMI68_71; /* offset: 0x0544 size: 32 bit */
1609  SIUL_PSMI_32B_tag PSMI72_75; /* offset: 0x0548 size: 32 bit */
1610  SIUL_PSMI_32B_tag PSMI76_79; /* offset: 0x054C size: 32 bit */
1611  SIUL_PSMI_32B_tag PSMI80_83; /* offset: 0x0550 size: 32 bit */
1612  SIUL_PSMI_32B_tag PSMI84_87; /* offset: 0x0554 size: 32 bit */
1613  SIUL_PSMI_32B_tag PSMI88_91; /* offset: 0x0558 size: 32 bit */
1614  SIUL_PSMI_32B_tag PSMI92_95; /* offset: 0x055C size: 32 bit */
1615  SIUL_PSMI_32B_tag PSMI96_99; /* offset: 0x0560 size: 32 bit */
1616  SIUL_PSMI_32B_tag PSMI100_103; /* offset: 0x0564 size: 32 bit */
1617  SIUL_PSMI_32B_tag PSMI104_107; /* offset: 0x0568 size: 32 bit */
1618  SIUL_PSMI_32B_tag PSMI108_111; /* offset: 0x056C size: 32 bit */
1619  SIUL_PSMI_32B_tag PSMI112_115; /* offset: 0x0570 size: 32 bit */
1620  SIUL_PSMI_32B_tag PSMI116_119; /* offset: 0x0574 size: 32 bit */
1621  SIUL_PSMI_32B_tag PSMI120_123; /* offset: 0x0578 size: 32 bit */
1622  SIUL_PSMI_32B_tag PSMI124_127; /* offset: 0x057C size: 32 bit */
1623  SIUL_PSMI_32B_tag PSMI128_131; /* offset: 0x0580 size: 32 bit */
1624  SIUL_PSMI_32B_tag PSMI132_135; /* offset: 0x0584 size: 32 bit */
1625  SIUL_PSMI_32B_tag PSMI136_139; /* offset: 0x0588 size: 32 bit */
1626  SIUL_PSMI_32B_tag PSMI140_143; /* offset: 0x058C size: 32 bit */
1627  SIUL_PSMI_32B_tag PSMI144_147; /* offset: 0x0590 size: 32 bit */
1628  SIUL_PSMI_32B_tag PSMI148_151; /* offset: 0x0594 size: 32 bit */
1629  SIUL_PSMI_32B_tag PSMI152_155; /* offset: 0x0598 size: 32 bit */
1630  SIUL_PSMI_32B_tag PSMI156_159; /* offset: 0x059C size: 32 bit */
1631  SIUL_PSMI_32B_tag PSMI160_163; /* offset: 0x05A0 size: 32 bit */
1632  SIUL_PSMI_32B_tag PSMI164_167; /* offset: 0x05A4 size: 32 bit */
1633  SIUL_PSMI_32B_tag PSMI168_171; /* offset: 0x05A8 size: 32 bit */
1634  SIUL_PSMI_32B_tag PSMI172_175; /* offset: 0x05AC size: 32 bit */
1635  SIUL_PSMI_32B_tag PSMI176_179; /* offset: 0x05B0 size: 32 bit */
1636  SIUL_PSMI_32B_tag PSMI180_183; /* offset: 0x05B4 size: 32 bit */
1637  SIUL_PSMI_32B_tag PSMI184_187; /* offset: 0x05B8 size: 32 bit */
1638  SIUL_PSMI_32B_tag PSMI188_191; /* offset: 0x05BC size: 32 bit */
1639  SIUL_PSMI_32B_tag PSMI192_195; /* offset: 0x05C0 size: 32 bit */
1640  SIUL_PSMI_32B_tag PSMI196_199; /* offset: 0x05C4 size: 32 bit */
1641  SIUL_PSMI_32B_tag PSMI200_203; /* offset: 0x05C8 size: 32 bit */
1642  SIUL_PSMI_32B_tag PSMI204_207; /* offset: 0x05CC size: 32 bit */
1643  SIUL_PSMI_32B_tag PSMI208_211; /* offset: 0x05D0 size: 32 bit */
1644  SIUL_PSMI_32B_tag PSMI212_215; /* offset: 0x05D4 size: 32 bit */
1645  SIUL_PSMI_32B_tag PSMI216_219; /* offset: 0x05D8 size: 32 bit */
1646  SIUL_PSMI_32B_tag PSMI220_223; /* offset: 0x05DC size: 32 bit */
1647  SIUL_PSMI_32B_tag PSMI224_227; /* offset: 0x05E0 size: 32 bit */
1648  SIUL_PSMI_32B_tag PSMI228_231; /* offset: 0x05E4 size: 32 bit */
1649  SIUL_PSMI_32B_tag PSMI232_235; /* offset: 0x05E8 size: 32 bit */
1650  SIUL_PSMI_32B_tag PSMI236_239; /* offset: 0x05EC size: 32 bit */
1651  SIUL_PSMI_32B_tag PSMI240_243; /* offset: 0x05F0 size: 32 bit */
1652  SIUL_PSMI_32B_tag PSMI244_247; /* offset: 0x05F4 size: 32 bit */
1653  SIUL_PSMI_32B_tag PSMI248_251; /* offset: 0x05F8 size: 32 bit */
1654  SIUL_PSMI_32B_tag PSMI252_255; /* offset: 0x05FC size: 32 bit */
1655  };
1656 
1657  struct {
1658  /* PSMI - Pad Selection for Multiplexed Inputs */
1659  SIUL_PSMI_8B_tag PSMI0; /* offset: 0x0500 size: 8 bit */
1660  SIUL_PSMI_8B_tag PSMI1; /* offset: 0x0501 size: 8 bit */
1661  SIUL_PSMI_8B_tag PSMI2; /* offset: 0x0502 size: 8 bit */
1662  SIUL_PSMI_8B_tag PSMI3; /* offset: 0x0503 size: 8 bit */
1663  SIUL_PSMI_8B_tag PSMI4; /* offset: 0x0504 size: 8 bit */
1664  SIUL_PSMI_8B_tag PSMI5; /* offset: 0x0505 size: 8 bit */
1665  SIUL_PSMI_8B_tag PSMI6; /* offset: 0x0506 size: 8 bit */
1666  SIUL_PSMI_8B_tag PSMI7; /* offset: 0x0507 size: 8 bit */
1667  SIUL_PSMI_8B_tag PSMI8; /* offset: 0x0508 size: 8 bit */
1668  SIUL_PSMI_8B_tag PSMI9; /* offset: 0x0509 size: 8 bit */
1669  SIUL_PSMI_8B_tag PSMI10; /* offset: 0x050A size: 8 bit */
1670  SIUL_PSMI_8B_tag PSMI11; /* offset: 0x050B size: 8 bit */
1671  SIUL_PSMI_8B_tag PSMI12; /* offset: 0x050C size: 8 bit */
1672  SIUL_PSMI_8B_tag PSMI13; /* offset: 0x050D size: 8 bit */
1673  SIUL_PSMI_8B_tag PSMI14; /* offset: 0x050E size: 8 bit */
1674  SIUL_PSMI_8B_tag PSMI15; /* offset: 0x050F size: 8 bit */
1675  SIUL_PSMI_8B_tag PSMI16; /* offset: 0x0510 size: 8 bit */
1676  SIUL_PSMI_8B_tag PSMI17; /* offset: 0x0511 size: 8 bit */
1677  SIUL_PSMI_8B_tag PSMI18; /* offset: 0x0512 size: 8 bit */
1678  SIUL_PSMI_8B_tag PSMI19; /* offset: 0x0513 size: 8 bit */
1679  SIUL_PSMI_8B_tag PSMI20; /* offset: 0x0514 size: 8 bit */
1680  SIUL_PSMI_8B_tag PSMI21; /* offset: 0x0515 size: 8 bit */
1681  SIUL_PSMI_8B_tag PSMI22; /* offset: 0x0516 size: 8 bit */
1682  SIUL_PSMI_8B_tag PSMI23; /* offset: 0x0517 size: 8 bit */
1683  SIUL_PSMI_8B_tag PSMI24; /* offset: 0x0518 size: 8 bit */
1684  SIUL_PSMI_8B_tag PSMI25; /* offset: 0x0519 size: 8 bit */
1685  SIUL_PSMI_8B_tag PSMI26; /* offset: 0x051A size: 8 bit */
1686  SIUL_PSMI_8B_tag PSMI27; /* offset: 0x051B size: 8 bit */
1687  SIUL_PSMI_8B_tag PSMI28; /* offset: 0x051C size: 8 bit */
1688  SIUL_PSMI_8B_tag PSMI29; /* offset: 0x051D size: 8 bit */
1689  SIUL_PSMI_8B_tag PSMI30; /* offset: 0x051E size: 8 bit */
1690  SIUL_PSMI_8B_tag PSMI31; /* offset: 0x051F size: 8 bit */
1691  SIUL_PSMI_8B_tag PSMI32; /* offset: 0x0520 size: 8 bit */
1692  SIUL_PSMI_8B_tag PSMI33; /* offset: 0x0521 size: 8 bit */
1693  SIUL_PSMI_8B_tag PSMI34; /* offset: 0x0522 size: 8 bit */
1694  SIUL_PSMI_8B_tag PSMI35; /* offset: 0x0523 size: 8 bit */
1695  SIUL_PSMI_8B_tag PSMI36; /* offset: 0x0524 size: 8 bit */
1696  SIUL_PSMI_8B_tag PSMI37; /* offset: 0x0525 size: 8 bit */
1697  SIUL_PSMI_8B_tag PSMI38; /* offset: 0x0526 size: 8 bit */
1698  SIUL_PSMI_8B_tag PSMI39; /* offset: 0x0527 size: 8 bit */
1699  SIUL_PSMI_8B_tag PSMI40; /* offset: 0x0528 size: 8 bit */
1700  SIUL_PSMI_8B_tag PSMI41; /* offset: 0x0529 size: 8 bit */
1701  SIUL_PSMI_8B_tag PSMI42; /* offset: 0x052A size: 8 bit */
1702  SIUL_PSMI_8B_tag PSMI43; /* offset: 0x052B size: 8 bit */
1703  SIUL_PSMI_8B_tag PSMI44; /* offset: 0x052C size: 8 bit */
1704  SIUL_PSMI_8B_tag PSMI45; /* offset: 0x052D size: 8 bit */
1705  SIUL_PSMI_8B_tag PSMI46; /* offset: 0x052E size: 8 bit */
1706  SIUL_PSMI_8B_tag PSMI47; /* offset: 0x052F size: 8 bit */
1707  SIUL_PSMI_8B_tag PSMI48; /* offset: 0x0530 size: 8 bit */
1708  SIUL_PSMI_8B_tag PSMI49; /* offset: 0x0531 size: 8 bit */
1709  SIUL_PSMI_8B_tag PSMI50; /* offset: 0x0532 size: 8 bit */
1710  SIUL_PSMI_8B_tag PSMI51; /* offset: 0x0533 size: 8 bit */
1711  SIUL_PSMI_8B_tag PSMI52; /* offset: 0x0534 size: 8 bit */
1712  SIUL_PSMI_8B_tag PSMI53; /* offset: 0x0535 size: 8 bit */
1713  SIUL_PSMI_8B_tag PSMI54; /* offset: 0x0536 size: 8 bit */
1714  SIUL_PSMI_8B_tag PSMI55; /* offset: 0x0537 size: 8 bit */
1715  SIUL_PSMI_8B_tag PSMI56; /* offset: 0x0538 size: 8 bit */
1716  SIUL_PSMI_8B_tag PSMI57; /* offset: 0x0539 size: 8 bit */
1717  SIUL_PSMI_8B_tag PSMI58; /* offset: 0x053A size: 8 bit */
1718  SIUL_PSMI_8B_tag PSMI59; /* offset: 0x053B size: 8 bit */
1719  SIUL_PSMI_8B_tag PSMI60; /* offset: 0x053C size: 8 bit */
1720  SIUL_PSMI_8B_tag PSMI61; /* offset: 0x053D size: 8 bit */
1721  SIUL_PSMI_8B_tag PSMI62; /* offset: 0x053E size: 8 bit */
1722  SIUL_PSMI_8B_tag PSMI63; /* offset: 0x053F size: 8 bit */
1723  SIUL_PSMI_8B_tag PSMI64; /* offset: 0x0540 size: 8 bit */
1724  SIUL_PSMI_8B_tag PSMI65; /* offset: 0x0541 size: 8 bit */
1725  SIUL_PSMI_8B_tag PSMI66; /* offset: 0x0542 size: 8 bit */
1726  SIUL_PSMI_8B_tag PSMI67; /* offset: 0x0543 size: 8 bit */
1727  SIUL_PSMI_8B_tag PSMI68; /* offset: 0x0544 size: 8 bit */
1728  SIUL_PSMI_8B_tag PSMI69; /* offset: 0x0545 size: 8 bit */
1729  SIUL_PSMI_8B_tag PSMI70; /* offset: 0x0546 size: 8 bit */
1730  SIUL_PSMI_8B_tag PSMI71; /* offset: 0x0547 size: 8 bit */
1731  SIUL_PSMI_8B_tag PSMI72; /* offset: 0x0548 size: 8 bit */
1732  SIUL_PSMI_8B_tag PSMI73; /* offset: 0x0549 size: 8 bit */
1733  SIUL_PSMI_8B_tag PSMI74; /* offset: 0x054A size: 8 bit */
1734  SIUL_PSMI_8B_tag PSMI75; /* offset: 0x054B size: 8 bit */
1735  SIUL_PSMI_8B_tag PSMI76; /* offset: 0x054C size: 8 bit */
1736  SIUL_PSMI_8B_tag PSMI77; /* offset: 0x054D size: 8 bit */
1737  SIUL_PSMI_8B_tag PSMI78; /* offset: 0x054E size: 8 bit */
1738  SIUL_PSMI_8B_tag PSMI79; /* offset: 0x054F size: 8 bit */
1739  SIUL_PSMI_8B_tag PSMI80; /* offset: 0x0550 size: 8 bit */
1740  SIUL_PSMI_8B_tag PSMI81; /* offset: 0x0551 size: 8 bit */
1741  SIUL_PSMI_8B_tag PSMI82; /* offset: 0x0552 size: 8 bit */
1742  SIUL_PSMI_8B_tag PSMI83; /* offset: 0x0553 size: 8 bit */
1743  SIUL_PSMI_8B_tag PSMI84; /* offset: 0x0554 size: 8 bit */
1744  SIUL_PSMI_8B_tag PSMI85; /* offset: 0x0555 size: 8 bit */
1745  SIUL_PSMI_8B_tag PSMI86; /* offset: 0x0556 size: 8 bit */
1746  SIUL_PSMI_8B_tag PSMI87; /* offset: 0x0557 size: 8 bit */
1747  SIUL_PSMI_8B_tag PSMI88; /* offset: 0x0558 size: 8 bit */
1748  SIUL_PSMI_8B_tag PSMI89; /* offset: 0x0559 size: 8 bit */
1749  SIUL_PSMI_8B_tag PSMI90; /* offset: 0x055A size: 8 bit */
1750  SIUL_PSMI_8B_tag PSMI91; /* offset: 0x055B size: 8 bit */
1751  SIUL_PSMI_8B_tag PSMI92; /* offset: 0x055C size: 8 bit */
1752  SIUL_PSMI_8B_tag PSMI93; /* offset: 0x055D size: 8 bit */
1753  SIUL_PSMI_8B_tag PSMI94; /* offset: 0x055E size: 8 bit */
1754  SIUL_PSMI_8B_tag PSMI95; /* offset: 0x055F size: 8 bit */
1755  SIUL_PSMI_8B_tag PSMI96; /* offset: 0x0560 size: 8 bit */
1756  SIUL_PSMI_8B_tag PSMI97; /* offset: 0x0561 size: 8 bit */
1757  SIUL_PSMI_8B_tag PSMI98; /* offset: 0x0562 size: 8 bit */
1758  SIUL_PSMI_8B_tag PSMI99; /* offset: 0x0563 size: 8 bit */
1759  SIUL_PSMI_8B_tag PSMI100; /* offset: 0x0564 size: 8 bit */
1760  SIUL_PSMI_8B_tag PSMI101; /* offset: 0x0565 size: 8 bit */
1761  SIUL_PSMI_8B_tag PSMI102; /* offset: 0x0566 size: 8 bit */
1762  SIUL_PSMI_8B_tag PSMI103; /* offset: 0x0567 size: 8 bit */
1763  SIUL_PSMI_8B_tag PSMI104; /* offset: 0x0568 size: 8 bit */
1764  SIUL_PSMI_8B_tag PSMI105; /* offset: 0x0569 size: 8 bit */
1765  SIUL_PSMI_8B_tag PSMI106; /* offset: 0x056A size: 8 bit */
1766  SIUL_PSMI_8B_tag PSMI107; /* offset: 0x056B size: 8 bit */
1767  SIUL_PSMI_8B_tag PSMI108; /* offset: 0x056C size: 8 bit */
1768  SIUL_PSMI_8B_tag PSMI109; /* offset: 0x056D size: 8 bit */
1769  SIUL_PSMI_8B_tag PSMI110; /* offset: 0x056E size: 8 bit */
1770  SIUL_PSMI_8B_tag PSMI111; /* offset: 0x056F size: 8 bit */
1771  SIUL_PSMI_8B_tag PSMI112; /* offset: 0x0570 size: 8 bit */
1772  SIUL_PSMI_8B_tag PSMI113; /* offset: 0x0571 size: 8 bit */
1773  SIUL_PSMI_8B_tag PSMI114; /* offset: 0x0572 size: 8 bit */
1774  SIUL_PSMI_8B_tag PSMI115; /* offset: 0x0573 size: 8 bit */
1775  SIUL_PSMI_8B_tag PSMI116; /* offset: 0x0574 size: 8 bit */
1776  SIUL_PSMI_8B_tag PSMI117; /* offset: 0x0575 size: 8 bit */
1777  SIUL_PSMI_8B_tag PSMI118; /* offset: 0x0576 size: 8 bit */
1778  SIUL_PSMI_8B_tag PSMI119; /* offset: 0x0577 size: 8 bit */
1779  SIUL_PSMI_8B_tag PSMI120; /* offset: 0x0578 size: 8 bit */
1780  SIUL_PSMI_8B_tag PSMI121; /* offset: 0x0579 size: 8 bit */
1781  SIUL_PSMI_8B_tag PSMI122; /* offset: 0x057A size: 8 bit */
1782  SIUL_PSMI_8B_tag PSMI123; /* offset: 0x057B size: 8 bit */
1783  SIUL_PSMI_8B_tag PSMI124; /* offset: 0x057C size: 8 bit */
1784  SIUL_PSMI_8B_tag PSMI125; /* offset: 0x057D size: 8 bit */
1785  SIUL_PSMI_8B_tag PSMI126; /* offset: 0x057E size: 8 bit */
1786  SIUL_PSMI_8B_tag PSMI127; /* offset: 0x057F size: 8 bit */
1787  SIUL_PSMI_8B_tag PSMI128; /* offset: 0x0580 size: 8 bit */
1788  SIUL_PSMI_8B_tag PSMI129; /* offset: 0x0581 size: 8 bit */
1789  SIUL_PSMI_8B_tag PSMI130; /* offset: 0x0582 size: 8 bit */
1790  SIUL_PSMI_8B_tag PSMI131; /* offset: 0x0583 size: 8 bit */
1791  SIUL_PSMI_8B_tag PSMI132; /* offset: 0x0584 size: 8 bit */
1792  SIUL_PSMI_8B_tag PSMI133; /* offset: 0x0585 size: 8 bit */
1793  SIUL_PSMI_8B_tag PSMI134; /* offset: 0x0586 size: 8 bit */
1794  SIUL_PSMI_8B_tag PSMI135; /* offset: 0x0587 size: 8 bit */
1795  SIUL_PSMI_8B_tag PSMI136; /* offset: 0x0588 size: 8 bit */
1796  SIUL_PSMI_8B_tag PSMI137; /* offset: 0x0589 size: 8 bit */
1797  SIUL_PSMI_8B_tag PSMI138; /* offset: 0x058A size: 8 bit */
1798  SIUL_PSMI_8B_tag PSMI139; /* offset: 0x058B size: 8 bit */
1799  SIUL_PSMI_8B_tag PSMI140; /* offset: 0x058C size: 8 bit */
1800  SIUL_PSMI_8B_tag PSMI141; /* offset: 0x058D size: 8 bit */
1801  SIUL_PSMI_8B_tag PSMI142; /* offset: 0x058E size: 8 bit */
1802  SIUL_PSMI_8B_tag PSMI143; /* offset: 0x058F size: 8 bit */
1803  SIUL_PSMI_8B_tag PSMI144; /* offset: 0x0590 size: 8 bit */
1804  SIUL_PSMI_8B_tag PSMI145; /* offset: 0x0591 size: 8 bit */
1805  SIUL_PSMI_8B_tag PSMI146; /* offset: 0x0592 size: 8 bit */
1806  SIUL_PSMI_8B_tag PSMI147; /* offset: 0x0593 size: 8 bit */
1807  SIUL_PSMI_8B_tag PSMI148; /* offset: 0x0594 size: 8 bit */
1808  SIUL_PSMI_8B_tag PSMI149; /* offset: 0x0595 size: 8 bit */
1809  SIUL_PSMI_8B_tag PSMI150; /* offset: 0x0596 size: 8 bit */
1810  SIUL_PSMI_8B_tag PSMI151; /* offset: 0x0597 size: 8 bit */
1811  SIUL_PSMI_8B_tag PSMI152; /* offset: 0x0598 size: 8 bit */
1812  SIUL_PSMI_8B_tag PSMI153; /* offset: 0x0599 size: 8 bit */
1813  SIUL_PSMI_8B_tag PSMI154; /* offset: 0x059A size: 8 bit */
1814  SIUL_PSMI_8B_tag PSMI155; /* offset: 0x059B size: 8 bit */
1815  SIUL_PSMI_8B_tag PSMI156; /* offset: 0x059C size: 8 bit */
1816  SIUL_PSMI_8B_tag PSMI157; /* offset: 0x059D size: 8 bit */
1817  SIUL_PSMI_8B_tag PSMI158; /* offset: 0x059E size: 8 bit */
1818  SIUL_PSMI_8B_tag PSMI159; /* offset: 0x059F size: 8 bit */
1819  SIUL_PSMI_8B_tag PSMI160; /* offset: 0x05A0 size: 8 bit */
1820  SIUL_PSMI_8B_tag PSMI161; /* offset: 0x05A1 size: 8 bit */
1821  SIUL_PSMI_8B_tag PSMI162; /* offset: 0x05A2 size: 8 bit */
1822  SIUL_PSMI_8B_tag PSMI163; /* offset: 0x05A3 size: 8 bit */
1823  SIUL_PSMI_8B_tag PSMI164; /* offset: 0x05A4 size: 8 bit */
1824  SIUL_PSMI_8B_tag PSMI165; /* offset: 0x05A5 size: 8 bit */
1825  SIUL_PSMI_8B_tag PSMI166; /* offset: 0x05A6 size: 8 bit */
1826  SIUL_PSMI_8B_tag PSMI167; /* offset: 0x05A7 size: 8 bit */
1827  SIUL_PSMI_8B_tag PSMI168; /* offset: 0x05A8 size: 8 bit */
1828  SIUL_PSMI_8B_tag PSMI169; /* offset: 0x05A9 size: 8 bit */
1829  SIUL_PSMI_8B_tag PSMI170; /* offset: 0x05AA size: 8 bit */
1830  SIUL_PSMI_8B_tag PSMI171; /* offset: 0x05AB size: 8 bit */
1831  SIUL_PSMI_8B_tag PSMI172; /* offset: 0x05AC size: 8 bit */
1832  SIUL_PSMI_8B_tag PSMI173; /* offset: 0x05AD size: 8 bit */
1833  SIUL_PSMI_8B_tag PSMI174; /* offset: 0x05AE size: 8 bit */
1834  SIUL_PSMI_8B_tag PSMI175; /* offset: 0x05AF size: 8 bit */
1835  SIUL_PSMI_8B_tag PSMI176; /* offset: 0x05B0 size: 8 bit */
1836  SIUL_PSMI_8B_tag PSMI177; /* offset: 0x05B1 size: 8 bit */
1837  SIUL_PSMI_8B_tag PSMI178; /* offset: 0x05B2 size: 8 bit */
1838  SIUL_PSMI_8B_tag PSMI179; /* offset: 0x05B3 size: 8 bit */
1839  SIUL_PSMI_8B_tag PSMI180; /* offset: 0x05B4 size: 8 bit */
1840  SIUL_PSMI_8B_tag PSMI181; /* offset: 0x05B5 size: 8 bit */
1841  SIUL_PSMI_8B_tag PSMI182; /* offset: 0x05B6 size: 8 bit */
1842  SIUL_PSMI_8B_tag PSMI183; /* offset: 0x05B7 size: 8 bit */
1843  SIUL_PSMI_8B_tag PSMI184; /* offset: 0x05B8 size: 8 bit */
1844  SIUL_PSMI_8B_tag PSMI185; /* offset: 0x05B9 size: 8 bit */
1845  SIUL_PSMI_8B_tag PSMI186; /* offset: 0x05BA size: 8 bit */
1846  SIUL_PSMI_8B_tag PSMI187; /* offset: 0x05BB size: 8 bit */
1847  SIUL_PSMI_8B_tag PSMI188; /* offset: 0x05BC size: 8 bit */
1848  SIUL_PSMI_8B_tag PSMI189; /* offset: 0x05BD size: 8 bit */
1849  SIUL_PSMI_8B_tag PSMI190; /* offset: 0x05BE size: 8 bit */
1850  SIUL_PSMI_8B_tag PSMI191; /* offset: 0x05BF size: 8 bit */
1851  SIUL_PSMI_8B_tag PSMI192; /* offset: 0x05C0 size: 8 bit */
1852  SIUL_PSMI_8B_tag PSMI193; /* offset: 0x05C1 size: 8 bit */
1853  SIUL_PSMI_8B_tag PSMI194; /* offset: 0x05C2 size: 8 bit */
1854  SIUL_PSMI_8B_tag PSMI195; /* offset: 0x05C3 size: 8 bit */
1855  SIUL_PSMI_8B_tag PSMI196; /* offset: 0x05C4 size: 8 bit */
1856  SIUL_PSMI_8B_tag PSMI197; /* offset: 0x05C5 size: 8 bit */
1857  SIUL_PSMI_8B_tag PSMI198; /* offset: 0x05C6 size: 8 bit */
1858  SIUL_PSMI_8B_tag PSMI199; /* offset: 0x05C7 size: 8 bit */
1859  SIUL_PSMI_8B_tag PSMI200; /* offset: 0x05C8 size: 8 bit */
1860  SIUL_PSMI_8B_tag PSMI201; /* offset: 0x05C9 size: 8 bit */
1861  SIUL_PSMI_8B_tag PSMI202; /* offset: 0x05CA size: 8 bit */
1862  SIUL_PSMI_8B_tag PSMI203; /* offset: 0x05CB size: 8 bit */
1863  SIUL_PSMI_8B_tag PSMI204; /* offset: 0x05CC size: 8 bit */
1864  SIUL_PSMI_8B_tag PSMI205; /* offset: 0x05CD size: 8 bit */
1865  SIUL_PSMI_8B_tag PSMI206; /* offset: 0x05CE size: 8 bit */
1866  SIUL_PSMI_8B_tag PSMI207; /* offset: 0x05CF size: 8 bit */
1867  SIUL_PSMI_8B_tag PSMI208; /* offset: 0x05D0 size: 8 bit */
1868  SIUL_PSMI_8B_tag PSMI209; /* offset: 0x05D1 size: 8 bit */
1869  SIUL_PSMI_8B_tag PSMI210; /* offset: 0x05D2 size: 8 bit */
1870  SIUL_PSMI_8B_tag PSMI211; /* offset: 0x05D3 size: 8 bit */
1871  SIUL_PSMI_8B_tag PSMI212; /* offset: 0x05D4 size: 8 bit */
1872  SIUL_PSMI_8B_tag PSMI213; /* offset: 0x05D5 size: 8 bit */
1873  SIUL_PSMI_8B_tag PSMI214; /* offset: 0x05D6 size: 8 bit */
1874  SIUL_PSMI_8B_tag PSMI215; /* offset: 0x05D7 size: 8 bit */
1875  SIUL_PSMI_8B_tag PSMI216; /* offset: 0x05D8 size: 8 bit */
1876  SIUL_PSMI_8B_tag PSMI217; /* offset: 0x05D9 size: 8 bit */
1877  SIUL_PSMI_8B_tag PSMI218; /* offset: 0x05DA size: 8 bit */
1878  SIUL_PSMI_8B_tag PSMI219; /* offset: 0x05DB size: 8 bit */
1879  SIUL_PSMI_8B_tag PSMI220; /* offset: 0x05DC size: 8 bit */
1880  SIUL_PSMI_8B_tag PSMI221; /* offset: 0x05DD size: 8 bit */
1881  SIUL_PSMI_8B_tag PSMI222; /* offset: 0x05DE size: 8 bit */
1882  SIUL_PSMI_8B_tag PSMI223; /* offset: 0x05DF size: 8 bit */
1883  SIUL_PSMI_8B_tag PSMI224; /* offset: 0x05E0 size: 8 bit */
1884  SIUL_PSMI_8B_tag PSMI225; /* offset: 0x05E1 size: 8 bit */
1885  SIUL_PSMI_8B_tag PSMI226; /* offset: 0x05E2 size: 8 bit */
1886  SIUL_PSMI_8B_tag PSMI227; /* offset: 0x05E3 size: 8 bit */
1887  SIUL_PSMI_8B_tag PSMI228; /* offset: 0x05E4 size: 8 bit */
1888  SIUL_PSMI_8B_tag PSMI229; /* offset: 0x05E5 size: 8 bit */
1889  SIUL_PSMI_8B_tag PSMI230; /* offset: 0x05E6 size: 8 bit */
1890  SIUL_PSMI_8B_tag PSMI231; /* offset: 0x05E7 size: 8 bit */
1891  SIUL_PSMI_8B_tag PSMI232; /* offset: 0x05E8 size: 8 bit */
1892  SIUL_PSMI_8B_tag PSMI233; /* offset: 0x05E9 size: 8 bit */
1893  SIUL_PSMI_8B_tag PSMI234; /* offset: 0x05EA size: 8 bit */
1894  SIUL_PSMI_8B_tag PSMI235; /* offset: 0x05EB size: 8 bit */
1895  SIUL_PSMI_8B_tag PSMI236; /* offset: 0x05EC size: 8 bit */
1896  SIUL_PSMI_8B_tag PSMI237; /* offset: 0x05ED size: 8 bit */
1897  SIUL_PSMI_8B_tag PSMI238; /* offset: 0x05EE size: 8 bit */
1898  SIUL_PSMI_8B_tag PSMI239; /* offset: 0x05EF size: 8 bit */
1899  SIUL_PSMI_8B_tag PSMI240; /* offset: 0x05F0 size: 8 bit */
1900  SIUL_PSMI_8B_tag PSMI241; /* offset: 0x05F1 size: 8 bit */
1901  SIUL_PSMI_8B_tag PSMI242; /* offset: 0x05F2 size: 8 bit */
1902  SIUL_PSMI_8B_tag PSMI243; /* offset: 0x05F3 size: 8 bit */
1903  SIUL_PSMI_8B_tag PSMI244; /* offset: 0x05F4 size: 8 bit */
1904  SIUL_PSMI_8B_tag PSMI245; /* offset: 0x05F5 size: 8 bit */
1905  SIUL_PSMI_8B_tag PSMI246; /* offset: 0x05F6 size: 8 bit */
1906  SIUL_PSMI_8B_tag PSMI247; /* offset: 0x05F7 size: 8 bit */
1907  SIUL_PSMI_8B_tag PSMI248; /* offset: 0x05F8 size: 8 bit */
1908  SIUL_PSMI_8B_tag PSMI249; /* offset: 0x05F9 size: 8 bit */
1909  SIUL_PSMI_8B_tag PSMI250; /* offset: 0x05FA size: 8 bit */
1910  SIUL_PSMI_8B_tag PSMI251; /* offset: 0x05FB size: 8 bit */
1911  SIUL_PSMI_8B_tag PSMI252; /* offset: 0x05FC size: 8 bit */
1912  SIUL_PSMI_8B_tag PSMI253; /* offset: 0x05FD size: 8 bit */
1913  SIUL_PSMI_8B_tag PSMI254; /* offset: 0x05FE size: 8 bit */
1914  SIUL_PSMI_8B_tag PSMI255; /* offset: 0x05FF size: 8 bit */
1915  };
1916 
1917  };
1918  union {
1919  /* GPDO - GPIO Pad Data Output Register */
1920  SIUL_GPDO_32B_tag GPDO_32B[128]; /* offset: 0x0600 (0x0004 x 128) */
1921 
1922  /* GPDO - GPIO Pad Data Output Register */
1923  SIUL_GPDO_8B_tag GPDO[512]; /* offset: 0x0600 (0x0001 x 512) */
1924 
1925  struct {
1926  /* GPDO - GPIO Pad Data Output Register */
1927  SIUL_GPDO_32B_tag GPDO0_3; /* offset: 0x0600 size: 32 bit */
1928  SIUL_GPDO_32B_tag GPDO4_7; /* offset: 0x0604 size: 32 bit */
1929  SIUL_GPDO_32B_tag GPDO8_11; /* offset: 0x0608 size: 32 bit */
1930  SIUL_GPDO_32B_tag GPDO12_15; /* offset: 0x060C size: 32 bit */
1931  SIUL_GPDO_32B_tag GPDO16_19; /* offset: 0x0610 size: 32 bit */
1932  SIUL_GPDO_32B_tag GPDO20_23; /* offset: 0x0614 size: 32 bit */
1933  SIUL_GPDO_32B_tag GPDO24_27; /* offset: 0x0618 size: 32 bit */
1934  SIUL_GPDO_32B_tag GPDO28_31; /* offset: 0x061C size: 32 bit */
1935  SIUL_GPDO_32B_tag GPDO32_35; /* offset: 0x0620 size: 32 bit */
1936  SIUL_GPDO_32B_tag GPDO36_39; /* offset: 0x0624 size: 32 bit */
1937  SIUL_GPDO_32B_tag GPDO40_43; /* offset: 0x0628 size: 32 bit */
1938  SIUL_GPDO_32B_tag GPDO44_47; /* offset: 0x062C size: 32 bit */
1939  SIUL_GPDO_32B_tag GPDO48_51; /* offset: 0x0630 size: 32 bit */
1940  SIUL_GPDO_32B_tag GPDO52_55; /* offset: 0x0634 size: 32 bit */
1941  SIUL_GPDO_32B_tag GPDO56_59; /* offset: 0x0638 size: 32 bit */
1942  SIUL_GPDO_32B_tag GPDO60_63; /* offset: 0x063C size: 32 bit */
1943  SIUL_GPDO_32B_tag GPDO64_67; /* offset: 0x0640 size: 32 bit */
1944  SIUL_GPDO_32B_tag GPDO68_71; /* offset: 0x0644 size: 32 bit */
1945  SIUL_GPDO_32B_tag GPDO72_75; /* offset: 0x0648 size: 32 bit */
1946  SIUL_GPDO_32B_tag GPDO76_79; /* offset: 0x064C size: 32 bit */
1947  SIUL_GPDO_32B_tag GPDO80_83; /* offset: 0x0650 size: 32 bit */
1948  SIUL_GPDO_32B_tag GPDO84_87; /* offset: 0x0654 size: 32 bit */
1949  SIUL_GPDO_32B_tag GPDO88_91; /* offset: 0x0658 size: 32 bit */
1950  SIUL_GPDO_32B_tag GPDO92_95; /* offset: 0x065C size: 32 bit */
1951  SIUL_GPDO_32B_tag GPDO96_99; /* offset: 0x0660 size: 32 bit */
1952  SIUL_GPDO_32B_tag GPDO100_103; /* offset: 0x0664 size: 32 bit */
1953  SIUL_GPDO_32B_tag GPDO104_107; /* offset: 0x0668 size: 32 bit */
1954  SIUL_GPDO_32B_tag GPDO108_111; /* offset: 0x066C size: 32 bit */
1955  SIUL_GPDO_32B_tag GPDO112_115; /* offset: 0x0670 size: 32 bit */
1956  SIUL_GPDO_32B_tag GPDO116_119; /* offset: 0x0674 size: 32 bit */
1957  SIUL_GPDO_32B_tag GPDO120_123; /* offset: 0x0678 size: 32 bit */
1958  SIUL_GPDO_32B_tag GPDO124_127; /* offset: 0x067C size: 32 bit */
1959  SIUL_GPDO_32B_tag GPDO128_131; /* offset: 0x0680 size: 32 bit */
1960  SIUL_GPDO_32B_tag GPDO132_135; /* offset: 0x0684 size: 32 bit */
1961  SIUL_GPDO_32B_tag GPDO136_139; /* offset: 0x0688 size: 32 bit */
1962  SIUL_GPDO_32B_tag GPDO140_143; /* offset: 0x068C size: 32 bit */
1963  SIUL_GPDO_32B_tag GPDO144_147; /* offset: 0x0690 size: 32 bit */
1964  SIUL_GPDO_32B_tag GPDO148_151; /* offset: 0x0694 size: 32 bit */
1965  SIUL_GPDO_32B_tag GPDO152_155; /* offset: 0x0698 size: 32 bit */
1966  SIUL_GPDO_32B_tag GPDO156_159; /* offset: 0x069C size: 32 bit */
1967  SIUL_GPDO_32B_tag GPDO160_163; /* offset: 0x06A0 size: 32 bit */
1968  SIUL_GPDO_32B_tag GPDO164_167; /* offset: 0x06A4 size: 32 bit */
1969  SIUL_GPDO_32B_tag GPDO168_171; /* offset: 0x06A8 size: 32 bit */
1970  SIUL_GPDO_32B_tag GPDO172_175; /* offset: 0x06AC size: 32 bit */
1971  SIUL_GPDO_32B_tag GPDO176_179; /* offset: 0x06B0 size: 32 bit */
1972  SIUL_GPDO_32B_tag GPDO180_183; /* offset: 0x06B4 size: 32 bit */
1973  SIUL_GPDO_32B_tag GPDO184_187; /* offset: 0x06B8 size: 32 bit */
1974  SIUL_GPDO_32B_tag GPDO188_191; /* offset: 0x06BC size: 32 bit */
1975  SIUL_GPDO_32B_tag GPDO192_195; /* offset: 0x06C0 size: 32 bit */
1976  SIUL_GPDO_32B_tag GPDO196_199; /* offset: 0x06C4 size: 32 bit */
1977  SIUL_GPDO_32B_tag GPDO200_203; /* offset: 0x06C8 size: 32 bit */
1978  SIUL_GPDO_32B_tag GPDO204_207; /* offset: 0x06CC size: 32 bit */
1979  SIUL_GPDO_32B_tag GPDO208_211; /* offset: 0x06D0 size: 32 bit */
1980  SIUL_GPDO_32B_tag GPDO212_215; /* offset: 0x06D4 size: 32 bit */
1981  SIUL_GPDO_32B_tag GPDO216_219; /* offset: 0x06D8 size: 32 bit */
1982  SIUL_GPDO_32B_tag GPDO220_223; /* offset: 0x06DC size: 32 bit */
1983  SIUL_GPDO_32B_tag GPDO224_227; /* offset: 0x06E0 size: 32 bit */
1984  SIUL_GPDO_32B_tag GPDO228_231; /* offset: 0x06E4 size: 32 bit */
1985  SIUL_GPDO_32B_tag GPDO232_235; /* offset: 0x06E8 size: 32 bit */
1986  SIUL_GPDO_32B_tag GPDO236_239; /* offset: 0x06EC size: 32 bit */
1987  SIUL_GPDO_32B_tag GPDO240_243; /* offset: 0x06F0 size: 32 bit */
1988  SIUL_GPDO_32B_tag GPDO244_247; /* offset: 0x06F4 size: 32 bit */
1989  SIUL_GPDO_32B_tag GPDO248_251; /* offset: 0x06F8 size: 32 bit */
1990  SIUL_GPDO_32B_tag GPDO252_255; /* offset: 0x06FC size: 32 bit */
1991  SIUL_GPDO_32B_tag GPDO256_259; /* offset: 0x0700 size: 32 bit */
1992  SIUL_GPDO_32B_tag GPDO260_263; /* offset: 0x0704 size: 32 bit */
1993  SIUL_GPDO_32B_tag GPDO264_267; /* offset: 0x0708 size: 32 bit */
1994  SIUL_GPDO_32B_tag GPDO268_271; /* offset: 0x070C size: 32 bit */
1995  SIUL_GPDO_32B_tag GPDO272_275; /* offset: 0x0710 size: 32 bit */
1996  SIUL_GPDO_32B_tag GPDO276_279; /* offset: 0x0714 size: 32 bit */
1997  SIUL_GPDO_32B_tag GPDO280_283; /* offset: 0x0718 size: 32 bit */
1998  SIUL_GPDO_32B_tag GPDO284_287; /* offset: 0x071C size: 32 bit */
1999  SIUL_GPDO_32B_tag GPDO288_291; /* offset: 0x0720 size: 32 bit */
2000  SIUL_GPDO_32B_tag GPDO292_295; /* offset: 0x0724 size: 32 bit */
2001  SIUL_GPDO_32B_tag GPDO296_299; /* offset: 0x0728 size: 32 bit */
2002  SIUL_GPDO_32B_tag GPDO300_303; /* offset: 0x072C size: 32 bit */
2003  SIUL_GPDO_32B_tag GPDO304_307; /* offset: 0x0730 size: 32 bit */
2004  SIUL_GPDO_32B_tag GPDO308_311; /* offset: 0x0734 size: 32 bit */
2005  SIUL_GPDO_32B_tag GPDO312_315; /* offset: 0x0738 size: 32 bit */
2006  SIUL_GPDO_32B_tag GPDO316_319; /* offset: 0x073C size: 32 bit */
2007  SIUL_GPDO_32B_tag GPDO320_323; /* offset: 0x0740 size: 32 bit */
2008  SIUL_GPDO_32B_tag GPDO324_327; /* offset: 0x0744 size: 32 bit */
2009  SIUL_GPDO_32B_tag GPDO328_331; /* offset: 0x0748 size: 32 bit */
2010  SIUL_GPDO_32B_tag GPDO332_335; /* offset: 0x074C size: 32 bit */
2011  SIUL_GPDO_32B_tag GPDO336_339; /* offset: 0x0750 size: 32 bit */
2012  SIUL_GPDO_32B_tag GPDO340_343; /* offset: 0x0754 size: 32 bit */
2013  SIUL_GPDO_32B_tag GPDO344_347; /* offset: 0x0758 size: 32 bit */
2014  SIUL_GPDO_32B_tag GPDO348_351; /* offset: 0x075C size: 32 bit */
2015  SIUL_GPDO_32B_tag GPDO352_355; /* offset: 0x0760 size: 32 bit */
2016  SIUL_GPDO_32B_tag GPDO356_359; /* offset: 0x0764 size: 32 bit */
2017  SIUL_GPDO_32B_tag GPDO360_363; /* offset: 0x0768 size: 32 bit */
2018  SIUL_GPDO_32B_tag GPDO364_367; /* offset: 0x076C size: 32 bit */
2019  SIUL_GPDO_32B_tag GPDO368_371; /* offset: 0x0770 size: 32 bit */
2020  SIUL_GPDO_32B_tag GPDO372_375; /* offset: 0x0774 size: 32 bit */
2021  SIUL_GPDO_32B_tag GPDO376_379; /* offset: 0x0778 size: 32 bit */
2022  SIUL_GPDO_32B_tag GPDO380_383; /* offset: 0x077C size: 32 bit */
2023  SIUL_GPDO_32B_tag GPDO384_387; /* offset: 0x0780 size: 32 bit */
2024  SIUL_GPDO_32B_tag GPDO388_391; /* offset: 0x0784 size: 32 bit */
2025  SIUL_GPDO_32B_tag GPDO392_395; /* offset: 0x0788 size: 32 bit */
2026  SIUL_GPDO_32B_tag GPDO396_399; /* offset: 0x078C size: 32 bit */
2027  SIUL_GPDO_32B_tag GPDO400_403; /* offset: 0x0790 size: 32 bit */
2028  SIUL_GPDO_32B_tag GPDO404_407; /* offset: 0x0794 size: 32 bit */
2029  SIUL_GPDO_32B_tag GPDO408_411; /* offset: 0x0798 size: 32 bit */
2030  SIUL_GPDO_32B_tag GPDO412_415; /* offset: 0x079C size: 32 bit */
2031  SIUL_GPDO_32B_tag GPDO416_419; /* offset: 0x07A0 size: 32 bit */
2032  SIUL_GPDO_32B_tag GPDO420_423; /* offset: 0x07A4 size: 32 bit */
2033  SIUL_GPDO_32B_tag GPDO424_427; /* offset: 0x07A8 size: 32 bit */
2034  SIUL_GPDO_32B_tag GPDO428_431; /* offset: 0x07AC size: 32 bit */
2035  SIUL_GPDO_32B_tag GPDO432_435; /* offset: 0x07B0 size: 32 bit */
2036  SIUL_GPDO_32B_tag GPDO436_439; /* offset: 0x07B4 size: 32 bit */
2037  SIUL_GPDO_32B_tag GPDO440_443; /* offset: 0x07B8 size: 32 bit */
2038  SIUL_GPDO_32B_tag GPDO444_447; /* offset: 0x07BC size: 32 bit */
2039  SIUL_GPDO_32B_tag GPDO448_451; /* offset: 0x07C0 size: 32 bit */
2040  SIUL_GPDO_32B_tag GPDO452_455; /* offset: 0x07C4 size: 32 bit */
2041  SIUL_GPDO_32B_tag GPDO456_459; /* offset: 0x07C8 size: 32 bit */
2042  SIUL_GPDO_32B_tag GPDO460_463; /* offset: 0x07CC size: 32 bit */
2043  SIUL_GPDO_32B_tag GPDO464_467; /* offset: 0x07D0 size: 32 bit */
2044  SIUL_GPDO_32B_tag GPDO468_471; /* offset: 0x07D4 size: 32 bit */
2045  SIUL_GPDO_32B_tag GPDO472_475; /* offset: 0x07D8 size: 32 bit */
2046  SIUL_GPDO_32B_tag GPDO476_479; /* offset: 0x07DC size: 32 bit */
2047  SIUL_GPDO_32B_tag GPDO480_483; /* offset: 0x07E0 size: 32 bit */
2048  SIUL_GPDO_32B_tag GPDO484_487; /* offset: 0x07E4 size: 32 bit */
2049  SIUL_GPDO_32B_tag GPDO488_491; /* offset: 0x07E8 size: 32 bit */
2050  SIUL_GPDO_32B_tag GPDO492_495; /* offset: 0x07EC size: 32 bit */
2051  SIUL_GPDO_32B_tag GPDO496_499; /* offset: 0x07F0 size: 32 bit */
2052  SIUL_GPDO_32B_tag GPDO500_503; /* offset: 0x07F4 size: 32 bit */
2053  SIUL_GPDO_32B_tag GPDO504_507; /* offset: 0x07F8 size: 32 bit */
2054  SIUL_GPDO_32B_tag GPDO508_511; /* offset: 0x07FC size: 32 bit */
2055  };
2056 
2057  struct {
2058  /* GPDO - GPIO Pad Data Output Register */
2059  SIUL_GPDO_8B_tag GPDO0; /* offset: 0x0600 size: 8 bit */
2060  SIUL_GPDO_8B_tag GPDO1; /* offset: 0x0601 size: 8 bit */
2061  SIUL_GPDO_8B_tag GPDO2; /* offset: 0x0602 size: 8 bit */
2062  SIUL_GPDO_8B_tag GPDO3; /* offset: 0x0603 size: 8 bit */
2063  SIUL_GPDO_8B_tag GPDO4; /* offset: 0x0604 size: 8 bit */
2064  SIUL_GPDO_8B_tag GPDO5; /* offset: 0x0605 size: 8 bit */
2065  SIUL_GPDO_8B_tag GPDO6; /* offset: 0x0606 size: 8 bit */
2066  SIUL_GPDO_8B_tag GPDO7; /* offset: 0x0607 size: 8 bit */
2067  SIUL_GPDO_8B_tag GPDO8; /* offset: 0x0608 size: 8 bit */
2068  SIUL_GPDO_8B_tag GPDO9; /* offset: 0x0609 size: 8 bit */
2069  SIUL_GPDO_8B_tag GPDO10; /* offset: 0x060A size: 8 bit */
2070  SIUL_GPDO_8B_tag GPDO11; /* offset: 0x060B size: 8 bit */
2071  SIUL_GPDO_8B_tag GPDO12; /* offset: 0x060C size: 8 bit */
2072  SIUL_GPDO_8B_tag GPDO13; /* offset: 0x060D size: 8 bit */
2073  SIUL_GPDO_8B_tag GPDO14; /* offset: 0x060E size: 8 bit */
2074  SIUL_GPDO_8B_tag GPDO15; /* offset: 0x060F size: 8 bit */
2075  SIUL_GPDO_8B_tag GPDO16; /* offset: 0x0610 size: 8 bit */
2076  SIUL_GPDO_8B_tag GPDO17; /* offset: 0x0611 size: 8 bit */
2077  SIUL_GPDO_8B_tag GPDO18; /* offset: 0x0612 size: 8 bit */
2078  SIUL_GPDO_8B_tag GPDO19; /* offset: 0x0613 size: 8 bit */
2079  SIUL_GPDO_8B_tag GPDO20; /* offset: 0x0614 size: 8 bit */
2080  SIUL_GPDO_8B_tag GPDO21; /* offset: 0x0615 size: 8 bit */
2081  SIUL_GPDO_8B_tag GPDO22; /* offset: 0x0616 size: 8 bit */
2082  SIUL_GPDO_8B_tag GPDO23; /* offset: 0x0617 size: 8 bit */
2083  SIUL_GPDO_8B_tag GPDO24; /* offset: 0x0618 size: 8 bit */
2084  SIUL_GPDO_8B_tag GPDO25; /* offset: 0x0619 size: 8 bit */
2085  SIUL_GPDO_8B_tag GPDO26; /* offset: 0x061A size: 8 bit */
2086  SIUL_GPDO_8B_tag GPDO27; /* offset: 0x061B size: 8 bit */
2087  SIUL_GPDO_8B_tag GPDO28; /* offset: 0x061C size: 8 bit */
2088  SIUL_GPDO_8B_tag GPDO29; /* offset: 0x061D size: 8 bit */
2089  SIUL_GPDO_8B_tag GPDO30; /* offset: 0x061E size: 8 bit */
2090  SIUL_GPDO_8B_tag GPDO31; /* offset: 0x061F size: 8 bit */
2091  SIUL_GPDO_8B_tag GPDO32; /* offset: 0x0620 size: 8 bit */
2092  SIUL_GPDO_8B_tag GPDO33; /* offset: 0x0621 size: 8 bit */
2093  SIUL_GPDO_8B_tag GPDO34; /* offset: 0x0622 size: 8 bit */
2094  SIUL_GPDO_8B_tag GPDO35; /* offset: 0x0623 size: 8 bit */
2095  SIUL_GPDO_8B_tag GPDO36; /* offset: 0x0624 size: 8 bit */
2096  SIUL_GPDO_8B_tag GPDO37; /* offset: 0x0625 size: 8 bit */
2097  SIUL_GPDO_8B_tag GPDO38; /* offset: 0x0626 size: 8 bit */
2098  SIUL_GPDO_8B_tag GPDO39; /* offset: 0x0627 size: 8 bit */
2099  SIUL_GPDO_8B_tag GPDO40; /* offset: 0x0628 size: 8 bit */
2100  SIUL_GPDO_8B_tag GPDO41; /* offset: 0x0629 size: 8 bit */
2101  SIUL_GPDO_8B_tag GPDO42; /* offset: 0x062A size: 8 bit */
2102  SIUL_GPDO_8B_tag GPDO43; /* offset: 0x062B size: 8 bit */
2103  SIUL_GPDO_8B_tag GPDO44; /* offset: 0x062C size: 8 bit */
2104  SIUL_GPDO_8B_tag GPDO45; /* offset: 0x062D size: 8 bit */
2105  SIUL_GPDO_8B_tag GPDO46; /* offset: 0x062E size: 8 bit */
2106  SIUL_GPDO_8B_tag GPDO47; /* offset: 0x062F size: 8 bit */
2107  SIUL_GPDO_8B_tag GPDO48; /* offset: 0x0630 size: 8 bit */
2108  SIUL_GPDO_8B_tag GPDO49; /* offset: 0x0631 size: 8 bit */
2109  SIUL_GPDO_8B_tag GPDO50; /* offset: 0x0632 size: 8 bit */
2110  SIUL_GPDO_8B_tag GPDO51; /* offset: 0x0633 size: 8 bit */
2111  SIUL_GPDO_8B_tag GPDO52; /* offset: 0x0634 size: 8 bit */
2112  SIUL_GPDO_8B_tag GPDO53; /* offset: 0x0635 size: 8 bit */
2113  SIUL_GPDO_8B_tag GPDO54; /* offset: 0x0636 size: 8 bit */
2114  SIUL_GPDO_8B_tag GPDO55; /* offset: 0x0637 size: 8 bit */
2115  SIUL_GPDO_8B_tag GPDO56; /* offset: 0x0638 size: 8 bit */
2116  SIUL_GPDO_8B_tag GPDO57; /* offset: 0x0639 size: 8 bit */
2117  SIUL_GPDO_8B_tag GPDO58; /* offset: 0x063A size: 8 bit */
2118  SIUL_GPDO_8B_tag GPDO59; /* offset: 0x063B size: 8 bit */
2119  SIUL_GPDO_8B_tag GPDO60; /* offset: 0x063C size: 8 bit */
2120  SIUL_GPDO_8B_tag GPDO61; /* offset: 0x063D size: 8 bit */
2121  SIUL_GPDO_8B_tag GPDO62; /* offset: 0x063E size: 8 bit */
2122  SIUL_GPDO_8B_tag GPDO63; /* offset: 0x063F size: 8 bit */
2123  SIUL_GPDO_8B_tag GPDO64; /* offset: 0x0640 size: 8 bit */
2124  SIUL_GPDO_8B_tag GPDO65; /* offset: 0x0641 size: 8 bit */
2125  SIUL_GPDO_8B_tag GPDO66; /* offset: 0x0642 size: 8 bit */
2126  SIUL_GPDO_8B_tag GPDO67; /* offset: 0x0643 size: 8 bit */
2127  SIUL_GPDO_8B_tag GPDO68; /* offset: 0x0644 size: 8 bit */
2128  SIUL_GPDO_8B_tag GPDO69; /* offset: 0x0645 size: 8 bit */
2129  SIUL_GPDO_8B_tag GPDO70; /* offset: 0x0646 size: 8 bit */
2130  SIUL_GPDO_8B_tag GPDO71; /* offset: 0x0647 size: 8 bit */
2131  SIUL_GPDO_8B_tag GPDO72; /* offset: 0x0648 size: 8 bit */
2132  SIUL_GPDO_8B_tag GPDO73; /* offset: 0x0649 size: 8 bit */
2133  SIUL_GPDO_8B_tag GPDO74; /* offset: 0x064A size: 8 bit */
2134  SIUL_GPDO_8B_tag GPDO75; /* offset: 0x064B size: 8 bit */
2135  SIUL_GPDO_8B_tag GPDO76; /* offset: 0x064C size: 8 bit */
2136  SIUL_GPDO_8B_tag GPDO77; /* offset: 0x064D size: 8 bit */
2137  SIUL_GPDO_8B_tag GPDO78; /* offset: 0x064E size: 8 bit */
2138  SIUL_GPDO_8B_tag GPDO79; /* offset: 0x064F size: 8 bit */
2139  SIUL_GPDO_8B_tag GPDO80; /* offset: 0x0650 size: 8 bit */
2140  SIUL_GPDO_8B_tag GPDO81; /* offset: 0x0651 size: 8 bit */
2141  SIUL_GPDO_8B_tag GPDO82; /* offset: 0x0652 size: 8 bit */
2142  SIUL_GPDO_8B_tag GPDO83; /* offset: 0x0653 size: 8 bit */
2143  SIUL_GPDO_8B_tag GPDO84; /* offset: 0x0654 size: 8 bit */
2144  SIUL_GPDO_8B_tag GPDO85; /* offset: 0x0655 size: 8 bit */
2145  SIUL_GPDO_8B_tag GPDO86; /* offset: 0x0656 size: 8 bit */
2146  SIUL_GPDO_8B_tag GPDO87; /* offset: 0x0657 size: 8 bit */
2147  SIUL_GPDO_8B_tag GPDO88; /* offset: 0x0658 size: 8 bit */
2148  SIUL_GPDO_8B_tag GPDO89; /* offset: 0x0659 size: 8 bit */
2149  SIUL_GPDO_8B_tag GPDO90; /* offset: 0x065A size: 8 bit */
2150  SIUL_GPDO_8B_tag GPDO91; /* offset: 0x065B size: 8 bit */
2151  SIUL_GPDO_8B_tag GPDO92; /* offset: 0x065C size: 8 bit */
2152  SIUL_GPDO_8B_tag GPDO93; /* offset: 0x065D size: 8 bit */
2153  SIUL_GPDO_8B_tag GPDO94; /* offset: 0x065E size: 8 bit */
2154  SIUL_GPDO_8B_tag GPDO95; /* offset: 0x065F size: 8 bit */
2155  SIUL_GPDO_8B_tag GPDO96; /* offset: 0x0660 size: 8 bit */
2156  SIUL_GPDO_8B_tag GPDO97; /* offset: 0x0661 size: 8 bit */
2157  SIUL_GPDO_8B_tag GPDO98; /* offset: 0x0662 size: 8 bit */
2158  SIUL_GPDO_8B_tag GPDO99; /* offset: 0x0663 size: 8 bit */
2159  SIUL_GPDO_8B_tag GPDO100; /* offset: 0x0664 size: 8 bit */
2160  SIUL_GPDO_8B_tag GPDO101; /* offset: 0x0665 size: 8 bit */
2161  SIUL_GPDO_8B_tag GPDO102; /* offset: 0x0666 size: 8 bit */
2162  SIUL_GPDO_8B_tag GPDO103; /* offset: 0x0667 size: 8 bit */
2163  SIUL_GPDO_8B_tag GPDO104; /* offset: 0x0668 size: 8 bit */
2164  SIUL_GPDO_8B_tag GPDO105; /* offset: 0x0669 size: 8 bit */
2165  SIUL_GPDO_8B_tag GPDO106; /* offset: 0x066A size: 8 bit */
2166  SIUL_GPDO_8B_tag GPDO107; /* offset: 0x066B size: 8 bit */
2167  SIUL_GPDO_8B_tag GPDO108; /* offset: 0x066C size: 8 bit */
2168  SIUL_GPDO_8B_tag GPDO109; /* offset: 0x066D size: 8 bit */
2169  SIUL_GPDO_8B_tag GPDO110; /* offset: 0x066E size: 8 bit */
2170  SIUL_GPDO_8B_tag GPDO111; /* offset: 0x066F size: 8 bit */
2171  SIUL_GPDO_8B_tag GPDO112; /* offset: 0x0670 size: 8 bit */
2172  SIUL_GPDO_8B_tag GPDO113; /* offset: 0x0671 size: 8 bit */
2173  SIUL_GPDO_8B_tag GPDO114; /* offset: 0x0672 size: 8 bit */
2174  SIUL_GPDO_8B_tag GPDO115; /* offset: 0x0673 size: 8 bit */
2175  SIUL_GPDO_8B_tag GPDO116; /* offset: 0x0674 size: 8 bit */
2176  SIUL_GPDO_8B_tag GPDO117; /* offset: 0x0675 size: 8 bit */
2177  SIUL_GPDO_8B_tag GPDO118; /* offset: 0x0676 size: 8 bit */
2178  SIUL_GPDO_8B_tag GPDO119; /* offset: 0x0677 size: 8 bit */
2179  SIUL_GPDO_8B_tag GPDO120; /* offset: 0x0678 size: 8 bit */
2180  SIUL_GPDO_8B_tag GPDO121; /* offset: 0x0679 size: 8 bit */
2181  SIUL_GPDO_8B_tag GPDO122; /* offset: 0x067A size: 8 bit */
2182  SIUL_GPDO_8B_tag GPDO123; /* offset: 0x067B size: 8 bit */
2183  SIUL_GPDO_8B_tag GPDO124; /* offset: 0x067C size: 8 bit */
2184  SIUL_GPDO_8B_tag GPDO125; /* offset: 0x067D size: 8 bit */
2185  SIUL_GPDO_8B_tag GPDO126; /* offset: 0x067E size: 8 bit */
2186  SIUL_GPDO_8B_tag GPDO127; /* offset: 0x067F size: 8 bit */
2187  SIUL_GPDO_8B_tag GPDO128; /* offset: 0x0680 size: 8 bit */
2188  SIUL_GPDO_8B_tag GPDO129; /* offset: 0x0681 size: 8 bit */
2189  SIUL_GPDO_8B_tag GPDO130; /* offset: 0x0682 size: 8 bit */
2190  SIUL_GPDO_8B_tag GPDO131; /* offset: 0x0683 size: 8 bit */
2191  SIUL_GPDO_8B_tag GPDO132; /* offset: 0x0684 size: 8 bit */
2192  SIUL_GPDO_8B_tag GPDO133; /* offset: 0x0685 size: 8 bit */
2193  SIUL_GPDO_8B_tag GPDO134; /* offset: 0x0686 size: 8 bit */
2194  SIUL_GPDO_8B_tag GPDO135; /* offset: 0x0687 size: 8 bit */
2195  SIUL_GPDO_8B_tag GPDO136; /* offset: 0x0688 size: 8 bit */
2196  SIUL_GPDO_8B_tag GPDO137; /* offset: 0x0689 size: 8 bit */
2197  SIUL_GPDO_8B_tag GPDO138; /* offset: 0x068A size: 8 bit */
2198  SIUL_GPDO_8B_tag GPDO139; /* offset: 0x068B size: 8 bit */
2199  SIUL_GPDO_8B_tag GPDO140; /* offset: 0x068C size: 8 bit */
2200  SIUL_GPDO_8B_tag GPDO141; /* offset: 0x068D size: 8 bit */
2201  SIUL_GPDO_8B_tag GPDO142; /* offset: 0x068E size: 8 bit */
2202  SIUL_GPDO_8B_tag GPDO143; /* offset: 0x068F size: 8 bit */
2203  SIUL_GPDO_8B_tag GPDO144; /* offset: 0x0690 size: 8 bit */
2204  SIUL_GPDO_8B_tag GPDO145; /* offset: 0x0691 size: 8 bit */
2205  SIUL_GPDO_8B_tag GPDO146; /* offset: 0x0692 size: 8 bit */
2206  SIUL_GPDO_8B_tag GPDO147; /* offset: 0x0693 size: 8 bit */
2207  SIUL_GPDO_8B_tag GPDO148; /* offset: 0x0694 size: 8 bit */
2208  SIUL_GPDO_8B_tag GPDO149; /* offset: 0x0695 size: 8 bit */
2209  SIUL_GPDO_8B_tag GPDO150; /* offset: 0x0696 size: 8 bit */
2210  SIUL_GPDO_8B_tag GPDO151; /* offset: 0x0697 size: 8 bit */
2211  SIUL_GPDO_8B_tag GPDO152; /* offset: 0x0698 size: 8 bit */
2212  SIUL_GPDO_8B_tag GPDO153; /* offset: 0x0699 size: 8 bit */
2213  SIUL_GPDO_8B_tag GPDO154; /* offset: 0x069A size: 8 bit */
2214  SIUL_GPDO_8B_tag GPDO155; /* offset: 0x069B size: 8 bit */
2215  SIUL_GPDO_8B_tag GPDO156; /* offset: 0x069C size: 8 bit */
2216  SIUL_GPDO_8B_tag GPDO157; /* offset: 0x069D size: 8 bit */
2217  SIUL_GPDO_8B_tag GPDO158; /* offset: 0x069E size: 8 bit */
2218  SIUL_GPDO_8B_tag GPDO159; /* offset: 0x069F size: 8 bit */
2219  SIUL_GPDO_8B_tag GPDO160; /* offset: 0x06A0 size: 8 bit */
2220  SIUL_GPDO_8B_tag GPDO161; /* offset: 0x06A1 size: 8 bit */
2221  SIUL_GPDO_8B_tag GPDO162; /* offset: 0x06A2 size: 8 bit */
2222  SIUL_GPDO_8B_tag GPDO163; /* offset: 0x06A3 size: 8 bit */
2223  SIUL_GPDO_8B_tag GPDO164; /* offset: 0x06A4 size: 8 bit */
2224  SIUL_GPDO_8B_tag GPDO165; /* offset: 0x06A5 size: 8 bit */
2225  SIUL_GPDO_8B_tag GPDO166; /* offset: 0x06A6 size: 8 bit */
2226  SIUL_GPDO_8B_tag GPDO167; /* offset: 0x06A7 size: 8 bit */
2227  SIUL_GPDO_8B_tag GPDO168; /* offset: 0x06A8 size: 8 bit */
2228  SIUL_GPDO_8B_tag GPDO169; /* offset: 0x06A9 size: 8 bit */
2229  SIUL_GPDO_8B_tag GPDO170; /* offset: 0x06AA size: 8 bit */
2230  SIUL_GPDO_8B_tag GPDO171; /* offset: 0x06AB size: 8 bit */
2231  SIUL_GPDO_8B_tag GPDO172; /* offset: 0x06AC size: 8 bit */
2232  SIUL_GPDO_8B_tag GPDO173; /* offset: 0x06AD size: 8 bit */
2233  SIUL_GPDO_8B_tag GPDO174; /* offset: 0x06AE size: 8 bit */
2234  SIUL_GPDO_8B_tag GPDO175; /* offset: 0x06AF size: 8 bit */
2235  SIUL_GPDO_8B_tag GPDO176; /* offset: 0x06B0 size: 8 bit */
2236  SIUL_GPDO_8B_tag GPDO177; /* offset: 0x06B1 size: 8 bit */
2237  SIUL_GPDO_8B_tag GPDO178; /* offset: 0x06B2 size: 8 bit */
2238  SIUL_GPDO_8B_tag GPDO179; /* offset: 0x06B3 size: 8 bit */
2239  SIUL_GPDO_8B_tag GPDO180; /* offset: 0x06B4 size: 8 bit */
2240  SIUL_GPDO_8B_tag GPDO181; /* offset: 0x06B5 size: 8 bit */
2241  SIUL_GPDO_8B_tag GPDO182; /* offset: 0x06B6 size: 8 bit */
2242  SIUL_GPDO_8B_tag GPDO183; /* offset: 0x06B7 size: 8 bit */
2243  SIUL_GPDO_8B_tag GPDO184; /* offset: 0x06B8 size: 8 bit */
2244  SIUL_GPDO_8B_tag GPDO185; /* offset: 0x06B9 size: 8 bit */
2245  SIUL_GPDO_8B_tag GPDO186; /* offset: 0x06BA size: 8 bit */
2246  SIUL_GPDO_8B_tag GPDO187; /* offset: 0x06BB size: 8 bit */
2247  SIUL_GPDO_8B_tag GPDO188; /* offset: 0x06BC size: 8 bit */
2248  SIUL_GPDO_8B_tag GPDO189; /* offset: 0x06BD size: 8 bit */
2249  SIUL_GPDO_8B_tag GPDO190; /* offset: 0x06BE size: 8 bit */
2250  SIUL_GPDO_8B_tag GPDO191; /* offset: 0x06BF size: 8 bit */
2251  SIUL_GPDO_8B_tag GPDO192; /* offset: 0x06C0 size: 8 bit */
2252  SIUL_GPDO_8B_tag GPDO193; /* offset: 0x06C1 size: 8 bit */
2253  SIUL_GPDO_8B_tag GPDO194; /* offset: 0x06C2 size: 8 bit */
2254  SIUL_GPDO_8B_tag GPDO195; /* offset: 0x06C3 size: 8 bit */
2255  SIUL_GPDO_8B_tag GPDO196; /* offset: 0x06C4 size: 8 bit */
2256  SIUL_GPDO_8B_tag GPDO197; /* offset: 0x06C5 size: 8 bit */
2257  SIUL_GPDO_8B_tag GPDO198; /* offset: 0x06C6 size: 8 bit */
2258  SIUL_GPDO_8B_tag GPDO199; /* offset: 0x06C7 size: 8 bit */
2259  SIUL_GPDO_8B_tag GPDO200; /* offset: 0x06C8 size: 8 bit */
2260  SIUL_GPDO_8B_tag GPDO201; /* offset: 0x06C9 size: 8 bit */
2261  SIUL_GPDO_8B_tag GPDO202; /* offset: 0x06CA size: 8 bit */
2262  SIUL_GPDO_8B_tag GPDO203; /* offset: 0x06CB size: 8 bit */
2263  SIUL_GPDO_8B_tag GPDO204; /* offset: 0x06CC size: 8 bit */
2264  SIUL_GPDO_8B_tag GPDO205; /* offset: 0x06CD size: 8 bit */
2265  SIUL_GPDO_8B_tag GPDO206; /* offset: 0x06CE size: 8 bit */
2266  SIUL_GPDO_8B_tag GPDO207; /* offset: 0x06CF size: 8 bit */
2267  SIUL_GPDO_8B_tag GPDO208; /* offset: 0x06D0 size: 8 bit */
2268  SIUL_GPDO_8B_tag GPDO209; /* offset: 0x06D1 size: 8 bit */
2269  SIUL_GPDO_8B_tag GPDO210; /* offset: 0x06D2 size: 8 bit */
2270  SIUL_GPDO_8B_tag GPDO211; /* offset: 0x06D3 size: 8 bit */
2271  SIUL_GPDO_8B_tag GPDO212; /* offset: 0x06D4 size: 8 bit */
2272  SIUL_GPDO_8B_tag GPDO213; /* offset: 0x06D5 size: 8 bit */
2273  SIUL_GPDO_8B_tag GPDO214; /* offset: 0x06D6 size: 8 bit */
2274  SIUL_GPDO_8B_tag GPDO215; /* offset: 0x06D7 size: 8 bit */
2275  SIUL_GPDO_8B_tag GPDO216; /* offset: 0x06D8 size: 8 bit */
2276  SIUL_GPDO_8B_tag GPDO217; /* offset: 0x06D9 size: 8 bit */
2277  SIUL_GPDO_8B_tag GPDO218; /* offset: 0x06DA size: 8 bit */
2278  SIUL_GPDO_8B_tag GPDO219; /* offset: 0x06DB size: 8 bit */
2279  SIUL_GPDO_8B_tag GPDO220; /* offset: 0x06DC size: 8 bit */
2280  SIUL_GPDO_8B_tag GPDO221; /* offset: 0x06DD size: 8 bit */
2281  SIUL_GPDO_8B_tag GPDO222; /* offset: 0x06DE size: 8 bit */
2282  SIUL_GPDO_8B_tag GPDO223; /* offset: 0x06DF size: 8 bit */
2283  SIUL_GPDO_8B_tag GPDO224; /* offset: 0x06E0 size: 8 bit */
2284  SIUL_GPDO_8B_tag GPDO225; /* offset: 0x06E1 size: 8 bit */
2285  SIUL_GPDO_8B_tag GPDO226; /* offset: 0x06E2 size: 8 bit */
2286  SIUL_GPDO_8B_tag GPDO227; /* offset: 0x06E3 size: 8 bit */
2287  SIUL_GPDO_8B_tag GPDO228; /* offset: 0x06E4 size: 8 bit */
2288  SIUL_GPDO_8B_tag GPDO229; /* offset: 0x06E5 size: 8 bit */
2289  SIUL_GPDO_8B_tag GPDO230; /* offset: 0x06E6 size: 8 bit */
2290  SIUL_GPDO_8B_tag GPDO231; /* offset: 0x06E7 size: 8 bit */
2291  SIUL_GPDO_8B_tag GPDO232; /* offset: 0x06E8 size: 8 bit */
2292  SIUL_GPDO_8B_tag GPDO233; /* offset: 0x06E9 size: 8 bit */
2293  SIUL_GPDO_8B_tag GPDO234; /* offset: 0x06EA size: 8 bit */
2294  SIUL_GPDO_8B_tag GPDO235; /* offset: 0x06EB size: 8 bit */
2295  SIUL_GPDO_8B_tag GPDO236; /* offset: 0x06EC size: 8 bit */
2296  SIUL_GPDO_8B_tag GPDO237; /* offset: 0x06ED size: 8 bit */
2297  SIUL_GPDO_8B_tag GPDO238; /* offset: 0x06EE size: 8 bit */
2298  SIUL_GPDO_8B_tag GPDO239; /* offset: 0x06EF size: 8 bit */
2299  SIUL_GPDO_8B_tag GPDO240; /* offset: 0x06F0 size: 8 bit */
2300  SIUL_GPDO_8B_tag GPDO241; /* offset: 0x06F1 size: 8 bit */
2301  SIUL_GPDO_8B_tag GPDO242; /* offset: 0x06F2 size: 8 bit */
2302  SIUL_GPDO_8B_tag GPDO243; /* offset: 0x06F3 size: 8 bit */
2303  SIUL_GPDO_8B_tag GPDO244; /* offset: 0x06F4 size: 8 bit */
2304  SIUL_GPDO_8B_tag GPDO245; /* offset: 0x06F5 size: 8 bit */
2305  SIUL_GPDO_8B_tag GPDO246; /* offset: 0x06F6 size: 8 bit */
2306  SIUL_GPDO_8B_tag GPDO247; /* offset: 0x06F7 size: 8 bit */
2307  SIUL_GPDO_8B_tag GPDO248; /* offset: 0x06F8 size: 8 bit */
2308  SIUL_GPDO_8B_tag GPDO249; /* offset: 0x06F9 size: 8 bit */
2309  SIUL_GPDO_8B_tag GPDO250; /* offset: 0x06FA size: 8 bit */
2310  SIUL_GPDO_8B_tag GPDO251; /* offset: 0x06FB size: 8 bit */
2311  SIUL_GPDO_8B_tag GPDO252; /* offset: 0x06FC size: 8 bit */
2312  SIUL_GPDO_8B_tag GPDO253; /* offset: 0x06FD size: 8 bit */
2313  SIUL_GPDO_8B_tag GPDO254; /* offset: 0x06FE size: 8 bit */
2314  SIUL_GPDO_8B_tag GPDO255; /* offset: 0x06FF size: 8 bit */
2315  SIUL_GPDO_8B_tag GPDO256; /* offset: 0x0700 size: 8 bit */
2316  SIUL_GPDO_8B_tag GPDO257; /* offset: 0x0701 size: 8 bit */
2317  SIUL_GPDO_8B_tag GPDO258; /* offset: 0x0702 size: 8 bit */
2318  SIUL_GPDO_8B_tag GPDO259; /* offset: 0x0703 size: 8 bit */
2319  SIUL_GPDO_8B_tag GPDO260; /* offset: 0x0704 size: 8 bit */
2320  SIUL_GPDO_8B_tag GPDO261; /* offset: 0x0705 size: 8 bit */
2321  SIUL_GPDO_8B_tag GPDO262; /* offset: 0x0706 size: 8 bit */
2322  SIUL_GPDO_8B_tag GPDO263; /* offset: 0x0707 size: 8 bit */
2323  SIUL_GPDO_8B_tag GPDO264; /* offset: 0x0708 size: 8 bit */
2324  SIUL_GPDO_8B_tag GPDO265; /* offset: 0x0709 size: 8 bit */
2325  SIUL_GPDO_8B_tag GPDO266; /* offset: 0x070A size: 8 bit */
2326  SIUL_GPDO_8B_tag GPDO267; /* offset: 0x070B size: 8 bit */
2327  SIUL_GPDO_8B_tag GPDO268; /* offset: 0x070C size: 8 bit */
2328  SIUL_GPDO_8B_tag GPDO269; /* offset: 0x070D size: 8 bit */
2329  SIUL_GPDO_8B_tag GPDO270; /* offset: 0x070E size: 8 bit */
2330  SIUL_GPDO_8B_tag GPDO271; /* offset: 0x070F size: 8 bit */
2331  SIUL_GPDO_8B_tag GPDO272; /* offset: 0x0710 size: 8 bit */
2332  SIUL_GPDO_8B_tag GPDO273; /* offset: 0x0711 size: 8 bit */
2333  SIUL_GPDO_8B_tag GPDO274; /* offset: 0x0712 size: 8 bit */
2334  SIUL_GPDO_8B_tag GPDO275; /* offset: 0x0713 size: 8 bit */
2335  SIUL_GPDO_8B_tag GPDO276; /* offset: 0x0714 size: 8 bit */
2336  SIUL_GPDO_8B_tag GPDO277; /* offset: 0x0715 size: 8 bit */
2337  SIUL_GPDO_8B_tag GPDO278; /* offset: 0x0716 size: 8 bit */
2338  SIUL_GPDO_8B_tag GPDO279; /* offset: 0x0717 size: 8 bit */
2339  SIUL_GPDO_8B_tag GPDO280; /* offset: 0x0718 size: 8 bit */
2340  SIUL_GPDO_8B_tag GPDO281; /* offset: 0x0719 size: 8 bit */
2341  SIUL_GPDO_8B_tag GPDO282; /* offset: 0x071A size: 8 bit */
2342  SIUL_GPDO_8B_tag GPDO283; /* offset: 0x071B size: 8 bit */
2343  SIUL_GPDO_8B_tag GPDO284; /* offset: 0x071C size: 8 bit */
2344  SIUL_GPDO_8B_tag GPDO285; /* offset: 0x071D size: 8 bit */
2345  SIUL_GPDO_8B_tag GPDO286; /* offset: 0x071E size: 8 bit */
2346  SIUL_GPDO_8B_tag GPDO287; /* offset: 0x071F size: 8 bit */
2347  SIUL_GPDO_8B_tag GPDO288; /* offset: 0x0720 size: 8 bit */
2348  SIUL_GPDO_8B_tag GPDO289; /* offset: 0x0721 size: 8 bit */
2349  SIUL_GPDO_8B_tag GPDO290; /* offset: 0x0722 size: 8 bit */
2350  SIUL_GPDO_8B_tag GPDO291; /* offset: 0x0723 size: 8 bit */
2351  SIUL_GPDO_8B_tag GPDO292; /* offset: 0x0724 size: 8 bit */
2352  SIUL_GPDO_8B_tag GPDO293; /* offset: 0x0725 size: 8 bit */
2353  SIUL_GPDO_8B_tag GPDO294; /* offset: 0x0726 size: 8 bit */
2354  SIUL_GPDO_8B_tag GPDO295; /* offset: 0x0727 size: 8 bit */
2355  SIUL_GPDO_8B_tag GPDO296; /* offset: 0x0728 size: 8 bit */
2356  SIUL_GPDO_8B_tag GPDO297; /* offset: 0x0729 size: 8 bit */
2357  SIUL_GPDO_8B_tag GPDO298; /* offset: 0x072A size: 8 bit */
2358  SIUL_GPDO_8B_tag GPDO299; /* offset: 0x072B size: 8 bit */
2359  SIUL_GPDO_8B_tag GPDO300; /* offset: 0x072C size: 8 bit */
2360  SIUL_GPDO_8B_tag GPDO301; /* offset: 0x072D size: 8 bit */
2361  SIUL_GPDO_8B_tag GPDO302; /* offset: 0x072E size: 8 bit */
2362  SIUL_GPDO_8B_tag GPDO303; /* offset: 0x072F size: 8 bit */
2363  SIUL_GPDO_8B_tag GPDO304; /* offset: 0x0730 size: 8 bit */
2364  SIUL_GPDO_8B_tag GPDO305; /* offset: 0x0731 size: 8 bit */
2365  SIUL_GPDO_8B_tag GPDO306; /* offset: 0x0732 size: 8 bit */
2366  SIUL_GPDO_8B_tag GPDO307; /* offset: 0x0733 size: 8 bit */
2367  SIUL_GPDO_8B_tag GPDO308; /* offset: 0x0734 size: 8 bit */
2368  SIUL_GPDO_8B_tag GPDO309; /* offset: 0x0735 size: 8 bit */
2369  SIUL_GPDO_8B_tag GPDO310; /* offset: 0x0736 size: 8 bit */
2370  SIUL_GPDO_8B_tag GPDO311; /* offset: 0x0737 size: 8 bit */
2371  SIUL_GPDO_8B_tag GPDO312; /* offset: 0x0738 size: 8 bit */
2372  SIUL_GPDO_8B_tag GPDO313; /* offset: 0x0739 size: 8 bit */
2373  SIUL_GPDO_8B_tag GPDO314; /* offset: 0x073A size: 8 bit */
2374  SIUL_GPDO_8B_tag GPDO315; /* offset: 0x073B size: 8 bit */
2375  SIUL_GPDO_8B_tag GPDO316; /* offset: 0x073C size: 8 bit */
2376  SIUL_GPDO_8B_tag GPDO317; /* offset: 0x073D size: 8 bit */
2377  SIUL_GPDO_8B_tag GPDO318; /* offset: 0x073E size: 8 bit */
2378  SIUL_GPDO_8B_tag GPDO319; /* offset: 0x073F size: 8 bit */
2379  SIUL_GPDO_8B_tag GPDO320; /* offset: 0x0740 size: 8 bit */
2380  SIUL_GPDO_8B_tag GPDO321; /* offset: 0x0741 size: 8 bit */
2381  SIUL_GPDO_8B_tag GPDO322; /* offset: 0x0742 size: 8 bit */
2382  SIUL_GPDO_8B_tag GPDO323; /* offset: 0x0743 size: 8 bit */
2383  SIUL_GPDO_8B_tag GPDO324; /* offset: 0x0744 size: 8 bit */
2384  SIUL_GPDO_8B_tag GPDO325; /* offset: 0x0745 size: 8 bit */
2385  SIUL_GPDO_8B_tag GPDO326; /* offset: 0x0746 size: 8 bit */
2386  SIUL_GPDO_8B_tag GPDO327; /* offset: 0x0747 size: 8 bit */
2387  SIUL_GPDO_8B_tag GPDO328; /* offset: 0x0748 size: 8 bit */
2388  SIUL_GPDO_8B_tag GPDO329; /* offset: 0x0749 size: 8 bit */
2389  SIUL_GPDO_8B_tag GPDO330; /* offset: 0x074A size: 8 bit */
2390  SIUL_GPDO_8B_tag GPDO331; /* offset: 0x074B size: 8 bit */
2391  SIUL_GPDO_8B_tag GPDO332; /* offset: 0x074C size: 8 bit */
2392  SIUL_GPDO_8B_tag GPDO333; /* offset: 0x074D size: 8 bit */
2393  SIUL_GPDO_8B_tag GPDO334; /* offset: 0x074E size: 8 bit */
2394  SIUL_GPDO_8B_tag GPDO335; /* offset: 0x074F size: 8 bit */
2395  SIUL_GPDO_8B_tag GPDO336; /* offset: 0x0750 size: 8 bit */
2396  SIUL_GPDO_8B_tag GPDO337; /* offset: 0x0751 size: 8 bit */
2397  SIUL_GPDO_8B_tag GPDO338; /* offset: 0x0752 size: 8 bit */
2398  SIUL_GPDO_8B_tag GPDO339; /* offset: 0x0753 size: 8 bit */
2399  SIUL_GPDO_8B_tag GPDO340; /* offset: 0x0754 size: 8 bit */
2400  SIUL_GPDO_8B_tag GPDO341; /* offset: 0x0755 size: 8 bit */
2401  SIUL_GPDO_8B_tag GPDO342; /* offset: 0x0756 size: 8 bit */
2402  SIUL_GPDO_8B_tag GPDO343; /* offset: 0x0757 size: 8 bit */
2403  SIUL_GPDO_8B_tag GPDO344; /* offset: 0x0758 size: 8 bit */
2404  SIUL_GPDO_8B_tag GPDO345; /* offset: 0x0759 size: 8 bit */
2405  SIUL_GPDO_8B_tag GPDO346; /* offset: 0x075A size: 8 bit */
2406  SIUL_GPDO_8B_tag GPDO347; /* offset: 0x075B size: 8 bit */
2407  SIUL_GPDO_8B_tag GPDO348; /* offset: 0x075C size: 8 bit */
2408  SIUL_GPDO_8B_tag GPDO349; /* offset: 0x075D size: 8 bit */
2409  SIUL_GPDO_8B_tag GPDO350; /* offset: 0x075E size: 8 bit */
2410  SIUL_GPDO_8B_tag GPDO351; /* offset: 0x075F size: 8 bit */
2411  SIUL_GPDO_8B_tag GPDO352; /* offset: 0x0760 size: 8 bit */
2412  SIUL_GPDO_8B_tag GPDO353; /* offset: 0x0761 size: 8 bit */
2413  SIUL_GPDO_8B_tag GPDO354; /* offset: 0x0762 size: 8 bit */
2414  SIUL_GPDO_8B_tag GPDO355; /* offset: 0x0763 size: 8 bit */
2415  SIUL_GPDO_8B_tag GPDO356; /* offset: 0x0764 size: 8 bit */
2416  SIUL_GPDO_8B_tag GPDO357; /* offset: 0x0765 size: 8 bit */
2417  SIUL_GPDO_8B_tag GPDO358; /* offset: 0x0766 size: 8 bit */
2418  SIUL_GPDO_8B_tag GPDO359; /* offset: 0x0767 size: 8 bit */
2419  SIUL_GPDO_8B_tag GPDO360; /* offset: 0x0768 size: 8 bit */
2420  SIUL_GPDO_8B_tag GPDO361; /* offset: 0x0769 size: 8 bit */
2421  SIUL_GPDO_8B_tag GPDO362; /* offset: 0x076A size: 8 bit */
2422  SIUL_GPDO_8B_tag GPDO363; /* offset: 0x076B size: 8 bit */
2423  SIUL_GPDO_8B_tag GPDO364; /* offset: 0x076C size: 8 bit */
2424  SIUL_GPDO_8B_tag GPDO365; /* offset: 0x076D size: 8 bit */
2425  SIUL_GPDO_8B_tag GPDO366; /* offset: 0x076E size: 8 bit */
2426  SIUL_GPDO_8B_tag GPDO367; /* offset: 0x076F size: 8 bit */
2427  SIUL_GPDO_8B_tag GPDO368; /* offset: 0x0770 size: 8 bit */
2428  SIUL_GPDO_8B_tag GPDO369; /* offset: 0x0771 size: 8 bit */
2429  SIUL_GPDO_8B_tag GPDO370; /* offset: 0x0772 size: 8 bit */
2430  SIUL_GPDO_8B_tag GPDO371; /* offset: 0x0773 size: 8 bit */
2431  SIUL_GPDO_8B_tag GPDO372; /* offset: 0x0774 size: 8 bit */
2432  SIUL_GPDO_8B_tag GPDO373; /* offset: 0x0775 size: 8 bit */
2433  SIUL_GPDO_8B_tag GPDO374; /* offset: 0x0776 size: 8 bit */
2434  SIUL_GPDO_8B_tag GPDO375; /* offset: 0x0777 size: 8 bit */
2435  SIUL_GPDO_8B_tag GPDO376; /* offset: 0x0778 size: 8 bit */
2436  SIUL_GPDO_8B_tag GPDO377; /* offset: 0x0779 size: 8 bit */
2437  SIUL_GPDO_8B_tag GPDO378; /* offset: 0x077A size: 8 bit */
2438  SIUL_GPDO_8B_tag GPDO379; /* offset: 0x077B size: 8 bit */
2439  SIUL_GPDO_8B_tag GPDO380; /* offset: 0x077C size: 8 bit */
2440  SIUL_GPDO_8B_tag GPDO381; /* offset: 0x077D size: 8 bit */
2441  SIUL_GPDO_8B_tag GPDO382; /* offset: 0x077E size: 8 bit */
2442  SIUL_GPDO_8B_tag GPDO383; /* offset: 0x077F size: 8 bit */
2443  SIUL_GPDO_8B_tag GPDO384; /* offset: 0x0780 size: 8 bit */
2444  SIUL_GPDO_8B_tag GPDO385; /* offset: 0x0781 size: 8 bit */
2445  SIUL_GPDO_8B_tag GPDO386; /* offset: 0x0782 size: 8 bit */
2446  SIUL_GPDO_8B_tag GPDO387; /* offset: 0x0783 size: 8 bit */
2447  SIUL_GPDO_8B_tag GPDO388; /* offset: 0x0784 size: 8 bit */
2448  SIUL_GPDO_8B_tag GPDO389; /* offset: 0x0785 size: 8 bit */
2449  SIUL_GPDO_8B_tag GPDO390; /* offset: 0x0786 size: 8 bit */
2450  SIUL_GPDO_8B_tag GPDO391; /* offset: 0x0787 size: 8 bit */
2451  SIUL_GPDO_8B_tag GPDO392; /* offset: 0x0788 size: 8 bit */
2452  SIUL_GPDO_8B_tag GPDO393; /* offset: 0x0789 size: 8 bit */
2453  SIUL_GPDO_8B_tag GPDO394; /* offset: 0x078A size: 8 bit */
2454  SIUL_GPDO_8B_tag GPDO395; /* offset: 0x078B size: 8 bit */
2455  SIUL_GPDO_8B_tag GPDO396; /* offset: 0x078C size: 8 bit */
2456  SIUL_GPDO_8B_tag GPDO397; /* offset: 0x078D size: 8 bit */
2457  SIUL_GPDO_8B_tag GPDO398; /* offset: 0x078E size: 8 bit */
2458  SIUL_GPDO_8B_tag GPDO399; /* offset: 0x078F size: 8 bit */
2459  SIUL_GPDO_8B_tag GPDO400; /* offset: 0x0790 size: 8 bit */
2460  SIUL_GPDO_8B_tag GPDO401; /* offset: 0x0791 size: 8 bit */
2461  SIUL_GPDO_8B_tag GPDO402; /* offset: 0x0792 size: 8 bit */
2462  SIUL_GPDO_8B_tag GPDO403; /* offset: 0x0793 size: 8 bit */
2463  SIUL_GPDO_8B_tag GPDO404; /* offset: 0x0794 size: 8 bit */
2464  SIUL_GPDO_8B_tag GPDO405; /* offset: 0x0795 size: 8 bit */
2465  SIUL_GPDO_8B_tag GPDO406; /* offset: 0x0796 size: 8 bit */
2466  SIUL_GPDO_8B_tag GPDO407; /* offset: 0x0797 size: 8 bit */
2467  SIUL_GPDO_8B_tag GPDO408; /* offset: 0x0798 size: 8 bit */
2468  SIUL_GPDO_8B_tag GPDO409; /* offset: 0x0799 size: 8 bit */
2469  SIUL_GPDO_8B_tag GPDO410; /* offset: 0x079A size: 8 bit */
2470  SIUL_GPDO_8B_tag GPDO411; /* offset: 0x079B size: 8 bit */
2471  SIUL_GPDO_8B_tag GPDO412; /* offset: 0x079C size: 8 bit */
2472  SIUL_GPDO_8B_tag GPDO413; /* offset: 0x079D size: 8 bit */
2473  SIUL_GPDO_8B_tag GPDO414; /* offset: 0x079E size: 8 bit */
2474  SIUL_GPDO_8B_tag GPDO415; /* offset: 0x079F size: 8 bit */
2475  SIUL_GPDO_8B_tag GPDO416; /* offset: 0x07A0 size: 8 bit */
2476  SIUL_GPDO_8B_tag GPDO417; /* offset: 0x07A1 size: 8 bit */
2477  SIUL_GPDO_8B_tag GPDO418; /* offset: 0x07A2 size: 8 bit */
2478  SIUL_GPDO_8B_tag GPDO419; /* offset: 0x07A3 size: 8 bit */
2479  SIUL_GPDO_8B_tag GPDO420; /* offset: 0x07A4 size: 8 bit */
2480  SIUL_GPDO_8B_tag GPDO421; /* offset: 0x07A5 size: 8 bit */
2481  SIUL_GPDO_8B_tag GPDO422; /* offset: 0x07A6 size: 8 bit */
2482  SIUL_GPDO_8B_tag GPDO423; /* offset: 0x07A7 size: 8 bit */
2483  SIUL_GPDO_8B_tag GPDO424; /* offset: 0x07A8 size: 8 bit */
2484  SIUL_GPDO_8B_tag GPDO425; /* offset: 0x07A9 size: 8 bit */
2485  SIUL_GPDO_8B_tag GPDO426; /* offset: 0x07AA size: 8 bit */
2486  SIUL_GPDO_8B_tag GPDO427; /* offset: 0x07AB size: 8 bit */
2487  SIUL_GPDO_8B_tag GPDO428; /* offset: 0x07AC size: 8 bit */
2488  SIUL_GPDO_8B_tag GPDO429; /* offset: 0x07AD size: 8 bit */
2489  SIUL_GPDO_8B_tag GPDO430; /* offset: 0x07AE size: 8 bit */
2490  SIUL_GPDO_8B_tag GPDO431; /* offset: 0x07AF size: 8 bit */
2491  SIUL_GPDO_8B_tag GPDO432; /* offset: 0x07B0 size: 8 bit */
2492  SIUL_GPDO_8B_tag GPDO433; /* offset: 0x07B1 size: 8 bit */
2493  SIUL_GPDO_8B_tag GPDO434; /* offset: 0x07B2 size: 8 bit */
2494  SIUL_GPDO_8B_tag GPDO435; /* offset: 0x07B3 size: 8 bit */
2495  SIUL_GPDO_8B_tag GPDO436; /* offset: 0x07B4 size: 8 bit */
2496  SIUL_GPDO_8B_tag GPDO437; /* offset: 0x07B5 size: 8 bit */
2497  SIUL_GPDO_8B_tag GPDO438; /* offset: 0x07B6 size: 8 bit */
2498  SIUL_GPDO_8B_tag GPDO439; /* offset: 0x07B7 size: 8 bit */
2499  SIUL_GPDO_8B_tag GPDO440; /* offset: 0x07B8 size: 8 bit */
2500  SIUL_GPDO_8B_tag GPDO441; /* offset: 0x07B9 size: 8 bit */
2501  SIUL_GPDO_8B_tag GPDO442; /* offset: 0x07BA size: 8 bit */
2502  SIUL_GPDO_8B_tag GPDO443; /* offset: 0x07BB size: 8 bit */
2503  SIUL_GPDO_8B_tag GPDO444; /* offset: 0x07BC size: 8 bit */
2504  SIUL_GPDO_8B_tag GPDO445; /* offset: 0x07BD size: 8 bit */
2505  SIUL_GPDO_8B_tag GPDO446; /* offset: 0x07BE size: 8 bit */
2506  SIUL_GPDO_8B_tag GPDO447; /* offset: 0x07BF size: 8 bit */
2507  SIUL_GPDO_8B_tag GPDO448; /* offset: 0x07C0 size: 8 bit */
2508  SIUL_GPDO_8B_tag GPDO449; /* offset: 0x07C1 size: 8 bit */
2509  SIUL_GPDO_8B_tag GPDO450; /* offset: 0x07C2 size: 8 bit */
2510  SIUL_GPDO_8B_tag GPDO451; /* offset: 0x07C3 size: 8 bit */
2511  SIUL_GPDO_8B_tag GPDO452; /* offset: 0x07C4 size: 8 bit */
2512  SIUL_GPDO_8B_tag GPDO453; /* offset: 0x07C5 size: 8 bit */
2513  SIUL_GPDO_8B_tag GPDO454; /* offset: 0x07C6 size: 8 bit */
2514  SIUL_GPDO_8B_tag GPDO455; /* offset: 0x07C7 size: 8 bit */
2515  SIUL_GPDO_8B_tag GPDO456; /* offset: 0x07C8 size: 8 bit */
2516  SIUL_GPDO_8B_tag GPDO457; /* offset: 0x07C9 size: 8 bit */
2517  SIUL_GPDO_8B_tag GPDO458; /* offset: 0x07CA size: 8 bit */
2518  SIUL_GPDO_8B_tag GPDO459; /* offset: 0x07CB size: 8 bit */
2519  SIUL_GPDO_8B_tag GPDO460; /* offset: 0x07CC size: 8 bit */
2520  SIUL_GPDO_8B_tag GPDO461; /* offset: 0x07CD size: 8 bit */
2521  SIUL_GPDO_8B_tag GPDO462; /* offset: 0x07CE size: 8 bit */
2522  SIUL_GPDO_8B_tag GPDO463; /* offset: 0x07CF size: 8 bit */
2523  SIUL_GPDO_8B_tag GPDO464; /* offset: 0x07D0 size: 8 bit */
2524  SIUL_GPDO_8B_tag GPDO465; /* offset: 0x07D1 size: 8 bit */
2525  SIUL_GPDO_8B_tag GPDO466; /* offset: 0x07D2 size: 8 bit */
2526  SIUL_GPDO_8B_tag GPDO467; /* offset: 0x07D3 size: 8 bit */
2527  SIUL_GPDO_8B_tag GPDO468; /* offset: 0x07D4 size: 8 bit */
2528  SIUL_GPDO_8B_tag GPDO469; /* offset: 0x07D5 size: 8 bit */
2529  SIUL_GPDO_8B_tag GPDO470; /* offset: 0x07D6 size: 8 bit */
2530  SIUL_GPDO_8B_tag GPDO471; /* offset: 0x07D7 size: 8 bit */
2531  SIUL_GPDO_8B_tag GPDO472; /* offset: 0x07D8 size: 8 bit */
2532  SIUL_GPDO_8B_tag GPDO473; /* offset: 0x07D9 size: 8 bit */
2533  SIUL_GPDO_8B_tag GPDO474; /* offset: 0x07DA size: 8 bit */
2534  SIUL_GPDO_8B_tag GPDO475; /* offset: 0x07DB size: 8 bit */
2535  SIUL_GPDO_8B_tag GPDO476; /* offset: 0x07DC size: 8 bit */
2536  SIUL_GPDO_8B_tag GPDO477; /* offset: 0x07DD size: 8 bit */
2537  SIUL_GPDO_8B_tag GPDO478; /* offset: 0x07DE size: 8 bit */
2538  SIUL_GPDO_8B_tag GPDO479; /* offset: 0x07DF size: 8 bit */
2539  SIUL_GPDO_8B_tag GPDO480; /* offset: 0x07E0 size: 8 bit */
2540  SIUL_GPDO_8B_tag GPDO481; /* offset: 0x07E1 size: 8 bit */
2541  SIUL_GPDO_8B_tag GPDO482; /* offset: 0x07E2 size: 8 bit */
2542  SIUL_GPDO_8B_tag GPDO483; /* offset: 0x07E3 size: 8 bit */
2543  SIUL_GPDO_8B_tag GPDO484; /* offset: 0x07E4 size: 8 bit */
2544  SIUL_GPDO_8B_tag GPDO485; /* offset: 0x07E5 size: 8 bit */
2545  SIUL_GPDO_8B_tag GPDO486; /* offset: 0x07E6 size: 8 bit */
2546  SIUL_GPDO_8B_tag GPDO487; /* offset: 0x07E7 size: 8 bit */
2547  SIUL_GPDO_8B_tag GPDO488; /* offset: 0x07E8 size: 8 bit */
2548  SIUL_GPDO_8B_tag GPDO489; /* offset: 0x07E9 size: 8 bit */
2549  SIUL_GPDO_8B_tag GPDO490; /* offset: 0x07EA size: 8 bit */
2550  SIUL_GPDO_8B_tag GPDO491; /* offset: 0x07EB size: 8 bit */
2551  SIUL_GPDO_8B_tag GPDO492; /* offset: 0x07EC size: 8 bit */
2552  SIUL_GPDO_8B_tag GPDO493; /* offset: 0x07ED size: 8 bit */
2553  SIUL_GPDO_8B_tag GPDO494; /* offset: 0x07EE size: 8 bit */
2554  SIUL_GPDO_8B_tag GPDO495; /* offset: 0x07EF size: 8 bit */
2555  SIUL_GPDO_8B_tag GPDO496; /* offset: 0x07F0 size: 8 bit */
2556  SIUL_GPDO_8B_tag GPDO497; /* offset: 0x07F1 size: 8 bit */
2557  SIUL_GPDO_8B_tag GPDO498; /* offset: 0x07F2 size: 8 bit */
2558  SIUL_GPDO_8B_tag GPDO499; /* offset: 0x07F3 size: 8 bit */
2559  SIUL_GPDO_8B_tag GPDO500; /* offset: 0x07F4 size: 8 bit */
2560  SIUL_GPDO_8B_tag GPDO501; /* offset: 0x07F5 size: 8 bit */
2561  SIUL_GPDO_8B_tag GPDO502; /* offset: 0x07F6 size: 8 bit */
2562  SIUL_GPDO_8B_tag GPDO503; /* offset: 0x07F7 size: 8 bit */
2563  SIUL_GPDO_8B_tag GPDO504; /* offset: 0x07F8 size: 8 bit */
2564  SIUL_GPDO_8B_tag GPDO505; /* offset: 0x07F9 size: 8 bit */
2565  SIUL_GPDO_8B_tag GPDO506; /* offset: 0x07FA size: 8 bit */
2566  SIUL_GPDO_8B_tag GPDO507; /* offset: 0x07FB size: 8 bit */
2567  SIUL_GPDO_8B_tag GPDO508; /* offset: 0x07FC size: 8 bit */
2568  SIUL_GPDO_8B_tag GPDO509; /* offset: 0x07FD size: 8 bit */
2569  SIUL_GPDO_8B_tag GPDO510; /* offset: 0x07FE size: 8 bit */
2570  SIUL_GPDO_8B_tag GPDO511; /* offset: 0x07FF size: 8 bit */
2571  };
2572 
2573  };
2574  union {
2575  /* GPDI - GPIO Pad Data Input Register */
2576  SIUL_GPDI_32B_tag GPDI_32B[128]; /* offset: 0x0800 (0x0004 x 128) */
2577 
2578  /* GPDI - GPIO Pad Data Input Register */
2579  SIUL_GPDI_8B_tag GPDI[512]; /* offset: 0x0800 (0x0001 x 512) */
2580 
2581  struct {
2582  /* GPDI - GPIO Pad Data Input Register */
2583  SIUL_GPDI_32B_tag GPDI0_3; /* offset: 0x0800 size: 32 bit */
2584  SIUL_GPDI_32B_tag GPDI4_7; /* offset: 0x0804 size: 32 bit */
2585  SIUL_GPDI_32B_tag GPDI8_11; /* offset: 0x0808 size: 32 bit */
2586  SIUL_GPDI_32B_tag GPDI12_15; /* offset: 0x080C size: 32 bit */
2587  SIUL_GPDI_32B_tag GPDI16_19; /* offset: 0x0810 size: 32 bit */
2588  SIUL_GPDI_32B_tag GPDI20_23; /* offset: 0x0814 size: 32 bit */
2589  SIUL_GPDI_32B_tag GPDI24_27; /* offset: 0x0818 size: 32 bit */
2590  SIUL_GPDI_32B_tag GPDI28_31; /* offset: 0x081C size: 32 bit */
2591  SIUL_GPDI_32B_tag GPDI32_35; /* offset: 0x0820 size: 32 bit */
2592  SIUL_GPDI_32B_tag GPDI36_39; /* offset: 0x0824 size: 32 bit */
2593  SIUL_GPDI_32B_tag GPDI40_43; /* offset: 0x0828 size: 32 bit */
2594  SIUL_GPDI_32B_tag GPDI44_47; /* offset: 0x082C size: 32 bit */
2595  SIUL_GPDI_32B_tag GPDI48_51; /* offset: 0x0830 size: 32 bit */
2596  SIUL_GPDI_32B_tag GPDI52_55; /* offset: 0x0834 size: 32 bit */
2597  SIUL_GPDI_32B_tag GPDI56_59; /* offset: 0x0838 size: 32 bit */
2598  SIUL_GPDI_32B_tag GPDI60_63; /* offset: 0x083C size: 32 bit */
2599  SIUL_GPDI_32B_tag GPDI64_67; /* offset: 0x0840 size: 32 bit */
2600  SIUL_GPDI_32B_tag GPDI68_71; /* offset: 0x0844 size: 32 bit */
2601  SIUL_GPDI_32B_tag GPDI72_75; /* offset: 0x0848 size: 32 bit */
2602  SIUL_GPDI_32B_tag GPDI76_79; /* offset: 0x084C size: 32 bit */
2603  SIUL_GPDI_32B_tag GPDI80_83; /* offset: 0x0850 size: 32 bit */
2604  SIUL_GPDI_32B_tag GPDI84_87; /* offset: 0x0854 size: 32 bit */
2605  SIUL_GPDI_32B_tag GPDI88_91; /* offset: 0x0858 size: 32 bit */
2606  SIUL_GPDI_32B_tag GPDI92_95; /* offset: 0x085C size: 32 bit */
2607  SIUL_GPDI_32B_tag GPDI96_99; /* offset: 0x0860 size: 32 bit */
2608  SIUL_GPDI_32B_tag GPDI100_103; /* offset: 0x0864 size: 32 bit */
2609  SIUL_GPDI_32B_tag GPDI104_107; /* offset: 0x0868 size: 32 bit */
2610  SIUL_GPDI_32B_tag GPDI108_111; /* offset: 0x086C size: 32 bit */
2611  SIUL_GPDI_32B_tag GPDI112_115; /* offset: 0x0870 size: 32 bit */
2612  SIUL_GPDI_32B_tag GPDI116_119; /* offset: 0x0874 size: 32 bit */
2613  SIUL_GPDI_32B_tag GPDI120_123; /* offset: 0x0878 size: 32 bit */
2614  SIUL_GPDI_32B_tag GPDI124_127; /* offset: 0x087C size: 32 bit */
2615  SIUL_GPDI_32B_tag GPDI128_131; /* offset: 0x0880 size: 32 bit */
2616  SIUL_GPDI_32B_tag GPDI132_135; /* offset: 0x0884 size: 32 bit */
2617  SIUL_GPDI_32B_tag GPDI136_139; /* offset: 0x0888 size: 32 bit */
2618  SIUL_GPDI_32B_tag GPDI140_143; /* offset: 0x088C size: 32 bit */
2619  SIUL_GPDI_32B_tag GPDI144_147; /* offset: 0x0890 size: 32 bit */
2620  SIUL_GPDI_32B_tag GPDI148_151; /* offset: 0x0894 size: 32 bit */
2621  SIUL_GPDI_32B_tag GPDI152_155; /* offset: 0x0898 size: 32 bit */
2622  SIUL_GPDI_32B_tag GPDI156_159; /* offset: 0x089C size: 32 bit */
2623  SIUL_GPDI_32B_tag GPDI160_163; /* offset: 0x08A0 size: 32 bit */
2624  SIUL_GPDI_32B_tag GPDI164_167; /* offset: 0x08A4 size: 32 bit */
2625  SIUL_GPDI_32B_tag GPDI168_171; /* offset: 0x08A8 size: 32 bit */
2626  SIUL_GPDI_32B_tag GPDI172_175; /* offset: 0x08AC size: 32 bit */
2627  SIUL_GPDI_32B_tag GPDI176_179; /* offset: 0x08B0 size: 32 bit */
2628  SIUL_GPDI_32B_tag GPDI180_183; /* offset: 0x08B4 size: 32 bit */
2629  SIUL_GPDI_32B_tag GPDI184_187; /* offset: 0x08B8 size: 32 bit */
2630  SIUL_GPDI_32B_tag GPDI188_191; /* offset: 0x08BC size: 32 bit */
2631  SIUL_GPDI_32B_tag GPDI192_195; /* offset: 0x08C0 size: 32 bit */
2632  SIUL_GPDI_32B_tag GPDI196_199; /* offset: 0x08C4 size: 32 bit */
2633  SIUL_GPDI_32B_tag GPDI200_203; /* offset: 0x08C8 size: 32 bit */
2634  SIUL_GPDI_32B_tag GPDI204_207; /* offset: 0x08CC size: 32 bit */
2635  SIUL_GPDI_32B_tag GPDI208_211; /* offset: 0x08D0 size: 32 bit */
2636  SIUL_GPDI_32B_tag GPDI212_215; /* offset: 0x08D4 size: 32 bit */
2637  SIUL_GPDI_32B_tag GPDI216_219; /* offset: 0x08D8 size: 32 bit */
2638  SIUL_GPDI_32B_tag GPDI220_223; /* offset: 0x08DC size: 32 bit */
2639  SIUL_GPDI_32B_tag GPDI224_227; /* offset: 0x08E0 size: 32 bit */
2640  SIUL_GPDI_32B_tag GPDI228_231; /* offset: 0x08E4 size: 32 bit */
2641  SIUL_GPDI_32B_tag GPDI232_235; /* offset: 0x08E8 size: 32 bit */
2642  SIUL_GPDI_32B_tag GPDI236_239; /* offset: 0x08EC size: 32 bit */
2643  SIUL_GPDI_32B_tag GPDI240_243; /* offset: 0x08F0 size: 32 bit */
2644  SIUL_GPDI_32B_tag GPDI244_247; /* offset: 0x08F4 size: 32 bit */
2645  SIUL_GPDI_32B_tag GPDI248_251; /* offset: 0x08F8 size: 32 bit */
2646  SIUL_GPDI_32B_tag GPDI252_255; /* offset: 0x08FC size: 32 bit */
2647  SIUL_GPDI_32B_tag GPDI256_259; /* offset: 0x0900 size: 32 bit */
2648  SIUL_GPDI_32B_tag GPDI260_263; /* offset: 0x0904 size: 32 bit */
2649  SIUL_GPDI_32B_tag GPDI264_267; /* offset: 0x0908 size: 32 bit */
2650  SIUL_GPDI_32B_tag GPDI268_271; /* offset: 0x090C size: 32 bit */
2651  SIUL_GPDI_32B_tag GPDI272_275; /* offset: 0x0910 size: 32 bit */
2652  SIUL_GPDI_32B_tag GPDI276_279; /* offset: 0x0914 size: 32 bit */
2653  SIUL_GPDI_32B_tag GPDI280_283; /* offset: 0x0918 size: 32 bit */
2654  SIUL_GPDI_32B_tag GPDI284_287; /* offset: 0x091C size: 32 bit */
2655  SIUL_GPDI_32B_tag GPDI288_291; /* offset: 0x0920 size: 32 bit */
2656  SIUL_GPDI_32B_tag GPDI292_295; /* offset: 0x0924 size: 32 bit */
2657  SIUL_GPDI_32B_tag GPDI296_299; /* offset: 0x0928 size: 32 bit */
2658  SIUL_GPDI_32B_tag GPDI300_303; /* offset: 0x092C size: 32 bit */
2659  SIUL_GPDI_32B_tag GPDI304_307; /* offset: 0x0930 size: 32 bit */
2660  SIUL_GPDI_32B_tag GPDI308_311; /* offset: 0x0934 size: 32 bit */
2661  SIUL_GPDI_32B_tag GPDI312_315; /* offset: 0x0938 size: 32 bit */
2662  SIUL_GPDI_32B_tag GPDI316_319; /* offset: 0x093C size: 32 bit */
2663  SIUL_GPDI_32B_tag GPDI320_323; /* offset: 0x0940 size: 32 bit */
2664  SIUL_GPDI_32B_tag GPDI324_327; /* offset: 0x0944 size: 32 bit */
2665  SIUL_GPDI_32B_tag GPDI328_331; /* offset: 0x0948 size: 32 bit */
2666  SIUL_GPDI_32B_tag GPDI332_335; /* offset: 0x094C size: 32 bit */
2667  SIUL_GPDI_32B_tag GPDI336_339; /* offset: 0x0950 size: 32 bit */
2668  SIUL_GPDI_32B_tag GPDI340_343; /* offset: 0x0954 size: 32 bit */
2669  SIUL_GPDI_32B_tag GPDI344_347; /* offset: 0x0958 size: 32 bit */
2670  SIUL_GPDI_32B_tag GPDI348_351; /* offset: 0x095C size: 32 bit */
2671  SIUL_GPDI_32B_tag GPDI352_355; /* offset: 0x0960 size: 32 bit */
2672  SIUL_GPDI_32B_tag GPDI356_359; /* offset: 0x0964 size: 32 bit */
2673  SIUL_GPDI_32B_tag GPDI360_363; /* offset: 0x0968 size: 32 bit */
2674  SIUL_GPDI_32B_tag GPDI364_367; /* offset: 0x096C size: 32 bit */
2675  SIUL_GPDI_32B_tag GPDI368_371; /* offset: 0x0970 size: 32 bit */
2676  SIUL_GPDI_32B_tag GPDI372_375; /* offset: 0x0974 size: 32 bit */
2677  SIUL_GPDI_32B_tag GPDI376_379; /* offset: 0x0978 size: 32 bit */
2678  SIUL_GPDI_32B_tag GPDI380_383; /* offset: 0x097C size: 32 bit */
2679  SIUL_GPDI_32B_tag GPDI384_387; /* offset: 0x0980 size: 32 bit */
2680  SIUL_GPDI_32B_tag GPDI388_391; /* offset: 0x0984 size: 32 bit */
2681  SIUL_GPDI_32B_tag GPDI392_395; /* offset: 0x0988 size: 32 bit */
2682  SIUL_GPDI_32B_tag GPDI396_399; /* offset: 0x098C size: 32 bit */
2683  SIUL_GPDI_32B_tag GPDI400_403; /* offset: 0x0990 size: 32 bit */
2684  SIUL_GPDI_32B_tag GPDI404_407; /* offset: 0x0994 size: 32 bit */
2685  SIUL_GPDI_32B_tag GPDI408_411; /* offset: 0x0998 size: 32 bit */
2686  SIUL_GPDI_32B_tag GPDI412_415; /* offset: 0x099C size: 32 bit */
2687  SIUL_GPDI_32B_tag GPDI416_419; /* offset: 0x09A0 size: 32 bit */
2688  SIUL_GPDI_32B_tag GPDI420_423; /* offset: 0x09A4 size: 32 bit */
2689  SIUL_GPDI_32B_tag GPDI424_427; /* offset: 0x09A8 size: 32 bit */
2690  SIUL_GPDI_32B_tag GPDI428_431; /* offset: 0x09AC size: 32 bit */
2691  SIUL_GPDI_32B_tag GPDI432_435; /* offset: 0x09B0 size: 32 bit */
2692  SIUL_GPDI_32B_tag GPDI436_439; /* offset: 0x09B4 size: 32 bit */
2693  SIUL_GPDI_32B_tag GPDI440_443; /* offset: 0x09B8 size: 32 bit */
2694  SIUL_GPDI_32B_tag GPDI444_447; /* offset: 0x09BC size: 32 bit */
2695  SIUL_GPDI_32B_tag GPDI448_451; /* offset: 0x09C0 size: 32 bit */
2696  SIUL_GPDI_32B_tag GPDI452_455; /* offset: 0x09C4 size: 32 bit */
2697  SIUL_GPDI_32B_tag GPDI456_459; /* offset: 0x09C8 size: 32 bit */
2698  SIUL_GPDI_32B_tag GPDI460_463; /* offset: 0x09CC size: 32 bit */
2699  SIUL_GPDI_32B_tag GPDI464_467; /* offset: 0x09D0 size: 32 bit */
2700  SIUL_GPDI_32B_tag GPDI468_471; /* offset: 0x09D4 size: 32 bit */
2701  SIUL_GPDI_32B_tag GPDI472_475; /* offset: 0x09D8 size: 32 bit */
2702  SIUL_GPDI_32B_tag GPDI476_479; /* offset: 0x09DC size: 32 bit */
2703  SIUL_GPDI_32B_tag GPDI480_483; /* offset: 0x09E0 size: 32 bit */
2704  SIUL_GPDI_32B_tag GPDI484_487; /* offset: 0x09E4 size: 32 bit */
2705  SIUL_GPDI_32B_tag GPDI488_491; /* offset: 0x09E8 size: 32 bit */
2706  SIUL_GPDI_32B_tag GPDI492_495; /* offset: 0x09EC size: 32 bit */
2707  SIUL_GPDI_32B_tag GPDI496_499; /* offset: 0x09F0 size: 32 bit */
2708  SIUL_GPDI_32B_tag GPDI500_503; /* offset: 0x09F4 size: 32 bit */
2709  SIUL_GPDI_32B_tag GPDI504_507; /* offset: 0x09F8 size: 32 bit */
2710  SIUL_GPDI_32B_tag GPDI508_511; /* offset: 0x09FC size: 32 bit */
2711  };
2712 
2713  struct {
2714  /* GPDI - GPIO Pad Data Input Register */
2715  SIUL_GPDI_8B_tag GPDI0; /* offset: 0x0800 size: 8 bit */
2716  SIUL_GPDI_8B_tag GPDI1; /* offset: 0x0801 size: 8 bit */
2717  SIUL_GPDI_8B_tag GPDI2; /* offset: 0x0802 size: 8 bit */
2718  SIUL_GPDI_8B_tag GPDI3; /* offset: 0x0803 size: 8 bit */
2719  SIUL_GPDI_8B_tag GPDI4; /* offset: 0x0804 size: 8 bit */
2720  SIUL_GPDI_8B_tag GPDI5; /* offset: 0x0805 size: 8 bit */
2721  SIUL_GPDI_8B_tag GPDI6; /* offset: 0x0806 size: 8 bit */
2722  SIUL_GPDI_8B_tag GPDI7; /* offset: 0x0807 size: 8 bit */
2723  SIUL_GPDI_8B_tag GPDI8; /* offset: 0x0808 size: 8 bit */
2724  SIUL_GPDI_8B_tag GPDI9; /* offset: 0x0809 size: 8 bit */
2725  SIUL_GPDI_8B_tag GPDI10; /* offset: 0x080A size: 8 bit */
2726  SIUL_GPDI_8B_tag GPDI11; /* offset: 0x080B size: 8 bit */
2727  SIUL_GPDI_8B_tag GPDI12; /* offset: 0x080C size: 8 bit */
2728  SIUL_GPDI_8B_tag GPDI13; /* offset: 0x080D size: 8 bit */
2729  SIUL_GPDI_8B_tag GPDI14; /* offset: 0x080E size: 8 bit */
2730  SIUL_GPDI_8B_tag GPDI15; /* offset: 0x080F size: 8 bit */
2731  SIUL_GPDI_8B_tag GPDI16; /* offset: 0x0810 size: 8 bit */
2732  SIUL_GPDI_8B_tag GPDI17; /* offset: 0x0811 size: 8 bit */
2733  SIUL_GPDI_8B_tag GPDI18; /* offset: 0x0812 size: 8 bit */
2734  SIUL_GPDI_8B_tag GPDI19; /* offset: 0x0813 size: 8 bit */
2735  SIUL_GPDI_8B_tag GPDI20; /* offset: 0x0814 size: 8 bit */
2736  SIUL_GPDI_8B_tag GPDI21; /* offset: 0x0815 size: 8 bit */
2737  SIUL_GPDI_8B_tag GPDI22; /* offset: 0x0816 size: 8 bit */
2738  SIUL_GPDI_8B_tag GPDI23; /* offset: 0x0817 size: 8 bit */
2739  SIUL_GPDI_8B_tag GPDI24; /* offset: 0x0818 size: 8 bit */
2740  SIUL_GPDI_8B_tag GPDI25; /* offset: 0x0819 size: 8 bit */
2741  SIUL_GPDI_8B_tag GPDI26; /* offset: 0x081A size: 8 bit */
2742  SIUL_GPDI_8B_tag GPDI27; /* offset: 0x081B size: 8 bit */
2743  SIUL_GPDI_8B_tag GPDI28; /* offset: 0x081C size: 8 bit */
2744  SIUL_GPDI_8B_tag GPDI29; /* offset: 0x081D size: 8 bit */
2745  SIUL_GPDI_8B_tag GPDI30; /* offset: 0x081E size: 8 bit */
2746  SIUL_GPDI_8B_tag GPDI31; /* offset: 0x081F size: 8 bit */
2747  SIUL_GPDI_8B_tag GPDI32; /* offset: 0x0820 size: 8 bit */
2748  SIUL_GPDI_8B_tag GPDI33; /* offset: 0x0821 size: 8 bit */
2749  SIUL_GPDI_8B_tag GPDI34; /* offset: 0x0822 size: 8 bit */
2750  SIUL_GPDI_8B_tag GPDI35; /* offset: 0x0823 size: 8 bit */
2751  SIUL_GPDI_8B_tag GPDI36; /* offset: 0x0824 size: 8 bit */
2752  SIUL_GPDI_8B_tag GPDI37; /* offset: 0x0825 size: 8 bit */
2753  SIUL_GPDI_8B_tag GPDI38; /* offset: 0x0826 size: 8 bit */
2754  SIUL_GPDI_8B_tag GPDI39; /* offset: 0x0827 size: 8 bit */
2755  SIUL_GPDI_8B_tag GPDI40; /* offset: 0x0828 size: 8 bit */
2756  SIUL_GPDI_8B_tag GPDI41; /* offset: 0x0829 size: 8 bit */
2757  SIUL_GPDI_8B_tag GPDI42; /* offset: 0x082A size: 8 bit */
2758  SIUL_GPDI_8B_tag GPDI43; /* offset: 0x082B size: 8 bit */
2759  SIUL_GPDI_8B_tag GPDI44; /* offset: 0x082C size: 8 bit */
2760  SIUL_GPDI_8B_tag GPDI45; /* offset: 0x082D size: 8 bit */
2761  SIUL_GPDI_8B_tag GPDI46; /* offset: 0x082E size: 8 bit */
2762  SIUL_GPDI_8B_tag GPDI47; /* offset: 0x082F size: 8 bit */
2763  SIUL_GPDI_8B_tag GPDI48; /* offset: 0x0830 size: 8 bit */
2764  SIUL_GPDI_8B_tag GPDI49; /* offset: 0x0831 size: 8 bit */
2765  SIUL_GPDI_8B_tag GPDI50; /* offset: 0x0832 size: 8 bit */
2766  SIUL_GPDI_8B_tag GPDI51; /* offset: 0x0833 size: 8 bit */
2767  SIUL_GPDI_8B_tag GPDI52; /* offset: 0x0834 size: 8 bit */
2768  SIUL_GPDI_8B_tag GPDI53; /* offset: 0x0835 size: 8 bit */
2769  SIUL_GPDI_8B_tag GPDI54; /* offset: 0x0836 size: 8 bit */
2770  SIUL_GPDI_8B_tag GPDI55; /* offset: 0x0837 size: 8 bit */
2771  SIUL_GPDI_8B_tag GPDI56; /* offset: 0x0838 size: 8 bit */
2772  SIUL_GPDI_8B_tag GPDI57; /* offset: 0x0839 size: 8 bit */
2773  SIUL_GPDI_8B_tag GPDI58; /* offset: 0x083A size: 8 bit */
2774  SIUL_GPDI_8B_tag GPDI59; /* offset: 0x083B size: 8 bit */
2775  SIUL_GPDI_8B_tag GPDI60; /* offset: 0x083C size: 8 bit */
2776  SIUL_GPDI_8B_tag GPDI61; /* offset: 0x083D size: 8 bit */
2777  SIUL_GPDI_8B_tag GPDI62; /* offset: 0x083E size: 8 bit */
2778  SIUL_GPDI_8B_tag GPDI63; /* offset: 0x083F size: 8 bit */
2779  SIUL_GPDI_8B_tag GPDI64; /* offset: 0x0840 size: 8 bit */
2780  SIUL_GPDI_8B_tag GPDI65; /* offset: 0x0841 size: 8 bit */
2781  SIUL_GPDI_8B_tag GPDI66; /* offset: 0x0842 size: 8 bit */
2782  SIUL_GPDI_8B_tag GPDI67; /* offset: 0x0843 size: 8 bit */
2783  SIUL_GPDI_8B_tag GPDI68; /* offset: 0x0844 size: 8 bit */
2784  SIUL_GPDI_8B_tag GPDI69; /* offset: 0x0845 size: 8 bit */
2785  SIUL_GPDI_8B_tag GPDI70; /* offset: 0x0846 size: 8 bit */
2786  SIUL_GPDI_8B_tag GPDI71; /* offset: 0x0847 size: 8 bit */
2787  SIUL_GPDI_8B_tag GPDI72; /* offset: 0x0848 size: 8 bit */
2788  SIUL_GPDI_8B_tag GPDI73; /* offset: 0x0849 size: 8 bit */
2789  SIUL_GPDI_8B_tag GPDI74; /* offset: 0x084A size: 8 bit */
2790  SIUL_GPDI_8B_tag GPDI75; /* offset: 0x084B size: 8 bit */
2791  SIUL_GPDI_8B_tag GPDI76; /* offset: 0x084C size: 8 bit */
2792  SIUL_GPDI_8B_tag GPDI77; /* offset: 0x084D size: 8 bit */
2793  SIUL_GPDI_8B_tag GPDI78; /* offset: 0x084E size: 8 bit */
2794  SIUL_GPDI_8B_tag GPDI79; /* offset: 0x084F size: 8 bit */
2795  SIUL_GPDI_8B_tag GPDI80; /* offset: 0x0850 size: 8 bit */
2796  SIUL_GPDI_8B_tag GPDI81; /* offset: 0x0851 size: 8 bit */
2797  SIUL_GPDI_8B_tag GPDI82; /* offset: 0x0852 size: 8 bit */
2798  SIUL_GPDI_8B_tag GPDI83; /* offset: 0x0853 size: 8 bit */
2799  SIUL_GPDI_8B_tag GPDI84; /* offset: 0x0854 size: 8 bit */
2800  SIUL_GPDI_8B_tag GPDI85; /* offset: 0x0855 size: 8 bit */
2801  SIUL_GPDI_8B_tag GPDI86; /* offset: 0x0856 size: 8 bit */
2802  SIUL_GPDI_8B_tag GPDI87; /* offset: 0x0857 size: 8 bit */
2803  SIUL_GPDI_8B_tag GPDI88; /* offset: 0x0858 size: 8 bit */
2804  SIUL_GPDI_8B_tag GPDI89; /* offset: 0x0859 size: 8 bit */
2805  SIUL_GPDI_8B_tag GPDI90; /* offset: 0x085A size: 8 bit */
2806  SIUL_GPDI_8B_tag GPDI91; /* offset: 0x085B size: 8 bit */
2807  SIUL_GPDI_8B_tag GPDI92; /* offset: 0x085C size: 8 bit */
2808  SIUL_GPDI_8B_tag GPDI93; /* offset: 0x085D size: 8 bit */
2809  SIUL_GPDI_8B_tag GPDI94; /* offset: 0x085E size: 8 bit */
2810  SIUL_GPDI_8B_tag GPDI95; /* offset: 0x085F size: 8 bit */
2811  SIUL_GPDI_8B_tag GPDI96; /* offset: 0x0860 size: 8 bit */
2812  SIUL_GPDI_8B_tag GPDI97; /* offset: 0x0861 size: 8 bit */
2813  SIUL_GPDI_8B_tag GPDI98; /* offset: 0x0862 size: 8 bit */
2814  SIUL_GPDI_8B_tag GPDI99; /* offset: 0x0863 size: 8 bit */
2815  SIUL_GPDI_8B_tag GPDI100; /* offset: 0x0864 size: 8 bit */
2816  SIUL_GPDI_8B_tag GPDI101; /* offset: 0x0865 size: 8 bit */
2817  SIUL_GPDI_8B_tag GPDI102; /* offset: 0x0866 size: 8 bit */
2818  SIUL_GPDI_8B_tag GPDI103; /* offset: 0x0867 size: 8 bit */
2819  SIUL_GPDI_8B_tag GPDI104; /* offset: 0x0868 size: 8 bit */
2820  SIUL_GPDI_8B_tag GPDI105; /* offset: 0x0869 size: 8 bit */
2821  SIUL_GPDI_8B_tag GPDI106; /* offset: 0x086A size: 8 bit */
2822  SIUL_GPDI_8B_tag GPDI107; /* offset: 0x086B size: 8 bit */
2823  SIUL_GPDI_8B_tag GPDI108; /* offset: 0x086C size: 8 bit */
2824  SIUL_GPDI_8B_tag GPDI109; /* offset: 0x086D size: 8 bit */
2825  SIUL_GPDI_8B_tag GPDI110; /* offset: 0x086E size: 8 bit */
2826  SIUL_GPDI_8B_tag GPDI111; /* offset: 0x086F size: 8 bit */
2827  SIUL_GPDI_8B_tag GPDI112; /* offset: 0x0870 size: 8 bit */
2828  SIUL_GPDI_8B_tag GPDI113; /* offset: 0x0871 size: 8 bit */
2829  SIUL_GPDI_8B_tag GPDI114; /* offset: 0x0872 size: 8 bit */
2830  SIUL_GPDI_8B_tag GPDI115; /* offset: 0x0873 size: 8 bit */
2831  SIUL_GPDI_8B_tag GPDI116; /* offset: 0x0874 size: 8 bit */
2832  SIUL_GPDI_8B_tag GPDI117; /* offset: 0x0875 size: 8 bit */
2833  SIUL_GPDI_8B_tag GPDI118; /* offset: 0x0876 size: 8 bit */
2834  SIUL_GPDI_8B_tag GPDI119; /* offset: 0x0877 size: 8 bit */
2835  SIUL_GPDI_8B_tag GPDI120; /* offset: 0x0878 size: 8 bit */
2836  SIUL_GPDI_8B_tag GPDI121; /* offset: 0x0879 size: 8 bit */
2837  SIUL_GPDI_8B_tag GPDI122; /* offset: 0x087A size: 8 bit */
2838  SIUL_GPDI_8B_tag GPDI123; /* offset: 0x087B size: 8 bit */
2839  SIUL_GPDI_8B_tag GPDI124; /* offset: 0x087C size: 8 bit */
2840  SIUL_GPDI_8B_tag GPDI125; /* offset: 0x087D size: 8 bit */
2841  SIUL_GPDI_8B_tag GPDI126; /* offset: 0x087E size: 8 bit */
2842  SIUL_GPDI_8B_tag GPDI127; /* offset: 0x087F size: 8 bit */
2843  SIUL_GPDI_8B_tag GPDI128; /* offset: 0x0880 size: 8 bit */
2844  SIUL_GPDI_8B_tag GPDI129; /* offset: 0x0881 size: 8 bit */
2845  SIUL_GPDI_8B_tag GPDI130; /* offset: 0x0882 size: 8 bit */
2846  SIUL_GPDI_8B_tag GPDI131; /* offset: 0x0883 size: 8 bit */
2847  SIUL_GPDI_8B_tag GPDI132; /* offset: 0x0884 size: 8 bit */
2848  SIUL_GPDI_8B_tag GPDI133; /* offset: 0x0885 size: 8 bit */
2849  SIUL_GPDI_8B_tag GPDI134; /* offset: 0x0886 size: 8 bit */
2850  SIUL_GPDI_8B_tag GPDI135; /* offset: 0x0887 size: 8 bit */
2851  SIUL_GPDI_8B_tag GPDI136; /* offset: 0x0888 size: 8 bit */
2852  SIUL_GPDI_8B_tag GPDI137; /* offset: 0x0889 size: 8 bit */
2853  SIUL_GPDI_8B_tag GPDI138; /* offset: 0x088A size: 8 bit */
2854  SIUL_GPDI_8B_tag GPDI139; /* offset: 0x088B size: 8 bit */
2855  SIUL_GPDI_8B_tag GPDI140; /* offset: 0x088C size: 8 bit */
2856  SIUL_GPDI_8B_tag GPDI141; /* offset: 0x088D size: 8 bit */
2857  SIUL_GPDI_8B_tag GPDI142; /* offset: 0x088E size: 8 bit */
2858  SIUL_GPDI_8B_tag GPDI143; /* offset: 0x088F size: 8 bit */
2859  SIUL_GPDI_8B_tag GPDI144; /* offset: 0x0890 size: 8 bit */
2860  SIUL_GPDI_8B_tag GPDI145; /* offset: 0x0891 size: 8 bit */
2861  SIUL_GPDI_8B_tag GPDI146; /* offset: 0x0892 size: 8 bit */
2862  SIUL_GPDI_8B_tag GPDI147; /* offset: 0x0893 size: 8 bit */
2863  SIUL_GPDI_8B_tag GPDI148; /* offset: 0x0894 size: 8 bit */
2864  SIUL_GPDI_8B_tag GPDI149; /* offset: 0x0895 size: 8 bit */
2865  SIUL_GPDI_8B_tag GPDI150; /* offset: 0x0896 size: 8 bit */
2866  SIUL_GPDI_8B_tag GPDI151; /* offset: 0x0897 size: 8 bit */
2867  SIUL_GPDI_8B_tag GPDI152; /* offset: 0x0898 size: 8 bit */
2868  SIUL_GPDI_8B_tag GPDI153; /* offset: 0x0899 size: 8 bit */
2869  SIUL_GPDI_8B_tag GPDI154; /* offset: 0x089A size: 8 bit */
2870  SIUL_GPDI_8B_tag GPDI155; /* offset: 0x089B size: 8 bit */
2871  SIUL_GPDI_8B_tag GPDI156; /* offset: 0x089C size: 8 bit */
2872  SIUL_GPDI_8B_tag GPDI157; /* offset: 0x089D size: 8 bit */
2873  SIUL_GPDI_8B_tag GPDI158; /* offset: 0x089E size: 8 bit */
2874  SIUL_GPDI_8B_tag GPDI159; /* offset: 0x089F size: 8 bit */
2875  SIUL_GPDI_8B_tag GPDI160; /* offset: 0x08A0 size: 8 bit */
2876  SIUL_GPDI_8B_tag GPDI161; /* offset: 0x08A1 size: 8 bit */
2877  SIUL_GPDI_8B_tag GPDI162; /* offset: 0x08A2 size: 8 bit */
2878  SIUL_GPDI_8B_tag GPDI163; /* offset: 0x08A3 size: 8 bit */
2879  SIUL_GPDI_8B_tag GPDI164; /* offset: 0x08A4 size: 8 bit */
2880  SIUL_GPDI_8B_tag GPDI165; /* offset: 0x08A5 size: 8 bit */
2881  SIUL_GPDI_8B_tag GPDI166; /* offset: 0x08A6 size: 8 bit */
2882  SIUL_GPDI_8B_tag GPDI167; /* offset: 0x08A7 size: 8 bit */
2883  SIUL_GPDI_8B_tag GPDI168; /* offset: 0x08A8 size: 8 bit */
2884  SIUL_GPDI_8B_tag GPDI169; /* offset: 0x08A9 size: 8 bit */
2885  SIUL_GPDI_8B_tag GPDI170; /* offset: 0x08AA size: 8 bit */
2886  SIUL_GPDI_8B_tag GPDI171; /* offset: 0x08AB size: 8 bit */
2887  SIUL_GPDI_8B_tag GPDI172; /* offset: 0x08AC size: 8 bit */
2888  SIUL_GPDI_8B_tag GPDI173; /* offset: 0x08AD size: 8 bit */
2889  SIUL_GPDI_8B_tag GPDI174; /* offset: 0x08AE size: 8 bit */
2890  SIUL_GPDI_8B_tag GPDI175; /* offset: 0x08AF size: 8 bit */
2891  SIUL_GPDI_8B_tag GPDI176; /* offset: 0x08B0 size: 8 bit */
2892  SIUL_GPDI_8B_tag GPDI177; /* offset: 0x08B1 size: 8 bit */
2893  SIUL_GPDI_8B_tag GPDI178; /* offset: 0x08B2 size: 8 bit */
2894  SIUL_GPDI_8B_tag GPDI179; /* offset: 0x08B3 size: 8 bit */
2895  SIUL_GPDI_8B_tag GPDI180; /* offset: 0x08B4 size: 8 bit */
2896  SIUL_GPDI_8B_tag GPDI181; /* offset: 0x08B5 size: 8 bit */
2897  SIUL_GPDI_8B_tag GPDI182; /* offset: 0x08B6 size: 8 bit */
2898  SIUL_GPDI_8B_tag GPDI183; /* offset: 0x08B7 size: 8 bit */
2899  SIUL_GPDI_8B_tag GPDI184; /* offset: 0x08B8 size: 8 bit */
2900  SIUL_GPDI_8B_tag GPDI185; /* offset: 0x08B9 size: 8 bit */
2901  SIUL_GPDI_8B_tag GPDI186; /* offset: 0x08BA size: 8 bit */
2902  SIUL_GPDI_8B_tag GPDI187; /* offset: 0x08BB size: 8 bit */
2903  SIUL_GPDI_8B_tag GPDI188; /* offset: 0x08BC size: 8 bit */
2904  SIUL_GPDI_8B_tag GPDI189; /* offset: 0x08BD size: 8 bit */
2905  SIUL_GPDI_8B_tag GPDI190; /* offset: 0x08BE size: 8 bit */
2906  SIUL_GPDI_8B_tag GPDI191; /* offset: 0x08BF size: 8 bit */
2907  SIUL_GPDI_8B_tag GPDI192; /* offset: 0x08C0 size: 8 bit */
2908  SIUL_GPDI_8B_tag GPDI193; /* offset: 0x08C1 size: 8 bit */
2909  SIUL_GPDI_8B_tag GPDI194; /* offset: 0x08C2 size: 8 bit */
2910  SIUL_GPDI_8B_tag GPDI195; /* offset: 0x08C3 size: 8 bit */
2911  SIUL_GPDI_8B_tag GPDI196; /* offset: 0x08C4 size: 8 bit */
2912  SIUL_GPDI_8B_tag GPDI197; /* offset: 0x08C5 size: 8 bit */
2913  SIUL_GPDI_8B_tag GPDI198; /* offset: 0x08C6 size: 8 bit */
2914  SIUL_GPDI_8B_tag GPDI199; /* offset: 0x08C7 size: 8 bit */
2915  SIUL_GPDI_8B_tag GPDI200; /* offset: 0x08C8 size: 8 bit */
2916  SIUL_GPDI_8B_tag GPDI201; /* offset: 0x08C9 size: 8 bit */
2917  SIUL_GPDI_8B_tag GPDI202; /* offset: 0x08CA size: 8 bit */
2918  SIUL_GPDI_8B_tag GPDI203; /* offset: 0x08CB size: 8 bit */
2919  SIUL_GPDI_8B_tag GPDI204; /* offset: 0x08CC size: 8 bit */
2920  SIUL_GPDI_8B_tag GPDI205; /* offset: 0x08CD size: 8 bit */
2921  SIUL_GPDI_8B_tag GPDI206; /* offset: 0x08CE size: 8 bit */
2922  SIUL_GPDI_8B_tag GPDI207; /* offset: 0x08CF size: 8 bit */
2923  SIUL_GPDI_8B_tag GPDI208; /* offset: 0x08D0 size: 8 bit */
2924  SIUL_GPDI_8B_tag GPDI209; /* offset: 0x08D1 size: 8 bit */
2925  SIUL_GPDI_8B_tag GPDI210; /* offset: 0x08D2 size: 8 bit */
2926  SIUL_GPDI_8B_tag GPDI211; /* offset: 0x08D3 size: 8 bit */
2927  SIUL_GPDI_8B_tag GPDI212; /* offset: 0x08D4 size: 8 bit */
2928  SIUL_GPDI_8B_tag GPDI213; /* offset: 0x08D5 size: 8 bit */
2929  SIUL_GPDI_8B_tag GPDI214; /* offset: 0x08D6 size: 8 bit */
2930  SIUL_GPDI_8B_tag GPDI215; /* offset: 0x08D7 size: 8 bit */
2931  SIUL_GPDI_8B_tag GPDI216; /* offset: 0x08D8 size: 8 bit */
2932  SIUL_GPDI_8B_tag GPDI217; /* offset: 0x08D9 size: 8 bit */
2933  SIUL_GPDI_8B_tag GPDI218; /* offset: 0x08DA size: 8 bit */
2934  SIUL_GPDI_8B_tag GPDI219; /* offset: 0x08DB size: 8 bit */
2935  SIUL_GPDI_8B_tag GPDI220; /* offset: 0x08DC size: 8 bit */
2936  SIUL_GPDI_8B_tag GPDI221; /* offset: 0x08DD size: 8 bit */
2937  SIUL_GPDI_8B_tag GPDI222; /* offset: 0x08DE size: 8 bit */
2938  SIUL_GPDI_8B_tag GPDI223; /* offset: 0x08DF size: 8 bit */
2939  SIUL_GPDI_8B_tag GPDI224; /* offset: 0x08E0 size: 8 bit */
2940  SIUL_GPDI_8B_tag GPDI225; /* offset: 0x08E1 size: 8 bit */
2941  SIUL_GPDI_8B_tag GPDI226; /* offset: 0x08E2 size: 8 bit */
2942  SIUL_GPDI_8B_tag GPDI227; /* offset: 0x08E3 size: 8 bit */
2943  SIUL_GPDI_8B_tag GPDI228; /* offset: 0x08E4 size: 8 bit */
2944  SIUL_GPDI_8B_tag GPDI229; /* offset: 0x08E5 size: 8 bit */
2945  SIUL_GPDI_8B_tag GPDI230; /* offset: 0x08E6 size: 8 bit */
2946  SIUL_GPDI_8B_tag GPDI231; /* offset: 0x08E7 size: 8 bit */
2947  SIUL_GPDI_8B_tag GPDI232; /* offset: 0x08E8 size: 8 bit */
2948  SIUL_GPDI_8B_tag GPDI233; /* offset: 0x08E9 size: 8 bit */
2949  SIUL_GPDI_8B_tag GPDI234; /* offset: 0x08EA size: 8 bit */
2950  SIUL_GPDI_8B_tag GPDI235; /* offset: 0x08EB size: 8 bit */
2951  SIUL_GPDI_8B_tag GPDI236; /* offset: 0x08EC size: 8 bit */
2952  SIUL_GPDI_8B_tag GPDI237; /* offset: 0x08ED size: 8 bit */
2953  SIUL_GPDI_8B_tag GPDI238; /* offset: 0x08EE size: 8 bit */
2954  SIUL_GPDI_8B_tag GPDI239; /* offset: 0x08EF size: 8 bit */
2955  SIUL_GPDI_8B_tag GPDI240; /* offset: 0x08F0 size: 8 bit */
2956  SIUL_GPDI_8B_tag GPDI241; /* offset: 0x08F1 size: 8 bit */
2957  SIUL_GPDI_8B_tag GPDI242; /* offset: 0x08F2 size: 8 bit */
2958  SIUL_GPDI_8B_tag GPDI243; /* offset: 0x08F3 size: 8 bit */
2959  SIUL_GPDI_8B_tag GPDI244; /* offset: 0x08F4 size: 8 bit */
2960  SIUL_GPDI_8B_tag GPDI245; /* offset: 0x08F5 size: 8 bit */
2961  SIUL_GPDI_8B_tag GPDI246; /* offset: 0x08F6 size: 8 bit */
2962  SIUL_GPDI_8B_tag GPDI247; /* offset: 0x08F7 size: 8 bit */
2963  SIUL_GPDI_8B_tag GPDI248; /* offset: 0x08F8 size: 8 bit */
2964  SIUL_GPDI_8B_tag GPDI249; /* offset: 0x08F9 size: 8 bit */
2965  SIUL_GPDI_8B_tag GPDI250; /* offset: 0x08FA size: 8 bit */
2966  SIUL_GPDI_8B_tag GPDI251; /* offset: 0x08FB size: 8 bit */
2967  SIUL_GPDI_8B_tag GPDI252; /* offset: 0x08FC size: 8 bit */
2968  SIUL_GPDI_8B_tag GPDI253; /* offset: 0x08FD size: 8 bit */
2969  SIUL_GPDI_8B_tag GPDI254; /* offset: 0x08FE size: 8 bit */
2970  SIUL_GPDI_8B_tag GPDI255; /* offset: 0x08FF size: 8 bit */
2971  SIUL_GPDI_8B_tag GPDI256; /* offset: 0x0900 size: 8 bit */
2972  SIUL_GPDI_8B_tag GPDI257; /* offset: 0x0901 size: 8 bit */
2973  SIUL_GPDI_8B_tag GPDI258; /* offset: 0x0902 size: 8 bit */
2974  SIUL_GPDI_8B_tag GPDI259; /* offset: 0x0903 size: 8 bit */
2975  SIUL_GPDI_8B_tag GPDI260; /* offset: 0x0904 size: 8 bit */
2976  SIUL_GPDI_8B_tag GPDI261; /* offset: 0x0905 size: 8 bit */
2977  SIUL_GPDI_8B_tag GPDI262; /* offset: 0x0906 size: 8 bit */
2978  SIUL_GPDI_8B_tag GPDI263; /* offset: 0x0907 size: 8 bit */
2979  SIUL_GPDI_8B_tag GPDI264; /* offset: 0x0908 size: 8 bit */
2980  SIUL_GPDI_8B_tag GPDI265; /* offset: 0x0909 size: 8 bit */
2981  SIUL_GPDI_8B_tag GPDI266; /* offset: 0x090A size: 8 bit */
2982  SIUL_GPDI_8B_tag GPDI267; /* offset: 0x090B size: 8 bit */
2983  SIUL_GPDI_8B_tag GPDI268; /* offset: 0x090C size: 8 bit */
2984  SIUL_GPDI_8B_tag GPDI269; /* offset: 0x090D size: 8 bit */
2985  SIUL_GPDI_8B_tag GPDI270; /* offset: 0x090E size: 8 bit */
2986  SIUL_GPDI_8B_tag GPDI271; /* offset: 0x090F size: 8 bit */
2987  SIUL_GPDI_8B_tag GPDI272; /* offset: 0x0910 size: 8 bit */
2988  SIUL_GPDI_8B_tag GPDI273; /* offset: 0x0911 size: 8 bit */
2989  SIUL_GPDI_8B_tag GPDI274; /* offset: 0x0912 size: 8 bit */
2990  SIUL_GPDI_8B_tag GPDI275; /* offset: 0x0913 size: 8 bit */
2991  SIUL_GPDI_8B_tag GPDI276; /* offset: 0x0914 size: 8 bit */
2992  SIUL_GPDI_8B_tag GPDI277; /* offset: 0x0915 size: 8 bit */
2993  SIUL_GPDI_8B_tag GPDI278; /* offset: 0x0916 size: 8 bit */
2994  SIUL_GPDI_8B_tag GPDI279; /* offset: 0x0917 size: 8 bit */
2995  SIUL_GPDI_8B_tag GPDI280; /* offset: 0x0918 size: 8 bit */
2996  SIUL_GPDI_8B_tag GPDI281; /* offset: 0x0919 size: 8 bit */
2997  SIUL_GPDI_8B_tag GPDI282; /* offset: 0x091A size: 8 bit */
2998  SIUL_GPDI_8B_tag GPDI283; /* offset: 0x091B size: 8 bit */
2999  SIUL_GPDI_8B_tag GPDI284; /* offset: 0x091C size: 8 bit */
3000  SIUL_GPDI_8B_tag GPDI285; /* offset: 0x091D size: 8 bit */
3001  SIUL_GPDI_8B_tag GPDI286; /* offset: 0x091E size: 8 bit */
3002  SIUL_GPDI_8B_tag GPDI287; /* offset: 0x091F size: 8 bit */
3003  SIUL_GPDI_8B_tag GPDI288; /* offset: 0x0920 size: 8 bit */
3004  SIUL_GPDI_8B_tag GPDI289; /* offset: 0x0921 size: 8 bit */
3005  SIUL_GPDI_8B_tag GPDI290; /* offset: 0x0922 size: 8 bit */
3006  SIUL_GPDI_8B_tag GPDI291; /* offset: 0x0923 size: 8 bit */
3007  SIUL_GPDI_8B_tag GPDI292; /* offset: 0x0924 size: 8 bit */
3008  SIUL_GPDI_8B_tag GPDI293; /* offset: 0x0925 size: 8 bit */
3009  SIUL_GPDI_8B_tag GPDI294; /* offset: 0x0926 size: 8 bit */
3010  SIUL_GPDI_8B_tag GPDI295; /* offset: 0x0927 size: 8 bit */
3011  SIUL_GPDI_8B_tag GPDI296; /* offset: 0x0928 size: 8 bit */
3012  SIUL_GPDI_8B_tag GPDI297; /* offset: 0x0929 size: 8 bit */
3013  SIUL_GPDI_8B_tag GPDI298; /* offset: 0x092A size: 8 bit */
3014  SIUL_GPDI_8B_tag GPDI299; /* offset: 0x092B size: 8 bit */
3015  SIUL_GPDI_8B_tag GPDI300; /* offset: 0x092C size: 8 bit */
3016  SIUL_GPDI_8B_tag GPDI301; /* offset: 0x092D size: 8 bit */
3017  SIUL_GPDI_8B_tag GPDI302; /* offset: 0x092E size: 8 bit */
3018  SIUL_GPDI_8B_tag GPDI303; /* offset: 0x092F size: 8 bit */
3019  SIUL_GPDI_8B_tag GPDI304; /* offset: 0x0930 size: 8 bit */
3020  SIUL_GPDI_8B_tag GPDI305; /* offset: 0x0931 size: 8 bit */
3021  SIUL_GPDI_8B_tag GPDI306; /* offset: 0x0932 size: 8 bit */
3022  SIUL_GPDI_8B_tag GPDI307; /* offset: 0x0933 size: 8 bit */
3023  SIUL_GPDI_8B_tag GPDI308; /* offset: 0x0934 size: 8 bit */
3024  SIUL_GPDI_8B_tag GPDI309; /* offset: 0x0935 size: 8 bit */
3025  SIUL_GPDI_8B_tag GPDI310; /* offset: 0x0936 size: 8 bit */
3026  SIUL_GPDI_8B_tag GPDI311; /* offset: 0x0937 size: 8 bit */
3027  SIUL_GPDI_8B_tag GPDI312; /* offset: 0x0938 size: 8 bit */
3028  SIUL_GPDI_8B_tag GPDI313; /* offset: 0x0939 size: 8 bit */
3029  SIUL_GPDI_8B_tag GPDI314; /* offset: 0x093A size: 8 bit */
3030  SIUL_GPDI_8B_tag GPDI315; /* offset: 0x093B size: 8 bit */
3031  SIUL_GPDI_8B_tag GPDI316; /* offset: 0x093C size: 8 bit */
3032  SIUL_GPDI_8B_tag GPDI317; /* offset: 0x093D size: 8 bit */
3033  SIUL_GPDI_8B_tag GPDI318; /* offset: 0x093E size: 8 bit */
3034  SIUL_GPDI_8B_tag GPDI319; /* offset: 0x093F size: 8 bit */
3035  SIUL_GPDI_8B_tag GPDI320; /* offset: 0x0940 size: 8 bit */
3036  SIUL_GPDI_8B_tag GPDI321; /* offset: 0x0941 size: 8 bit */
3037  SIUL_GPDI_8B_tag GPDI322; /* offset: 0x0942 size: 8 bit */
3038  SIUL_GPDI_8B_tag GPDI323; /* offset: 0x0943 size: 8 bit */
3039  SIUL_GPDI_8B_tag GPDI324; /* offset: 0x0944 size: 8 bit */
3040  SIUL_GPDI_8B_tag GPDI325; /* offset: 0x0945 size: 8 bit */
3041  SIUL_GPDI_8B_tag GPDI326; /* offset: 0x0946 size: 8 bit */
3042  SIUL_GPDI_8B_tag GPDI327; /* offset: 0x0947 size: 8 bit */
3043  SIUL_GPDI_8B_tag GPDI328; /* offset: 0x0948 size: 8 bit */
3044  SIUL_GPDI_8B_tag GPDI329; /* offset: 0x0949 size: 8 bit */
3045  SIUL_GPDI_8B_tag GPDI330; /* offset: 0x094A size: 8 bit */
3046  SIUL_GPDI_8B_tag GPDI331; /* offset: 0x094B size: 8 bit */
3047  SIUL_GPDI_8B_tag GPDI332; /* offset: 0x094C size: 8 bit */
3048  SIUL_GPDI_8B_tag GPDI333; /* offset: 0x094D size: 8 bit */
3049  SIUL_GPDI_8B_tag GPDI334; /* offset: 0x094E size: 8 bit */
3050  SIUL_GPDI_8B_tag GPDI335; /* offset: 0x094F size: 8 bit */
3051  SIUL_GPDI_8B_tag GPDI336; /* offset: 0x0950 size: 8 bit */
3052  SIUL_GPDI_8B_tag GPDI337; /* offset: 0x0951 size: 8 bit */
3053  SIUL_GPDI_8B_tag GPDI338; /* offset: 0x0952 size: 8 bit */
3054  SIUL_GPDI_8B_tag GPDI339; /* offset: 0x0953 size: 8 bit */
3055  SIUL_GPDI_8B_tag GPDI340; /* offset: 0x0954 size: 8 bit */
3056  SIUL_GPDI_8B_tag GPDI341; /* offset: 0x0955 size: 8 bit */
3057  SIUL_GPDI_8B_tag GPDI342; /* offset: 0x0956 size: 8 bit */
3058  SIUL_GPDI_8B_tag GPDI343; /* offset: 0x0957 size: 8 bit */
3059  SIUL_GPDI_8B_tag GPDI344; /* offset: 0x0958 size: 8 bit */
3060  SIUL_GPDI_8B_tag GPDI345; /* offset: 0x0959 size: 8 bit */
3061  SIUL_GPDI_8B_tag GPDI346; /* offset: 0x095A size: 8 bit */
3062  SIUL_GPDI_8B_tag GPDI347; /* offset: 0x095B size: 8 bit */
3063  SIUL_GPDI_8B_tag GPDI348; /* offset: 0x095C size: 8 bit */
3064  SIUL_GPDI_8B_tag GPDI349; /* offset: 0x095D size: 8 bit */
3065  SIUL_GPDI_8B_tag GPDI350; /* offset: 0x095E size: 8 bit */
3066  SIUL_GPDI_8B_tag GPDI351; /* offset: 0x095F size: 8 bit */
3067  SIUL_GPDI_8B_tag GPDI352; /* offset: 0x0960 size: 8 bit */
3068  SIUL_GPDI_8B_tag GPDI353; /* offset: 0x0961 size: 8 bit */
3069  SIUL_GPDI_8B_tag GPDI354; /* offset: 0x0962 size: 8 bit */
3070  SIUL_GPDI_8B_tag GPDI355; /* offset: 0x0963 size: 8 bit */
3071  SIUL_GPDI_8B_tag GPDI356; /* offset: 0x0964 size: 8 bit */
3072  SIUL_GPDI_8B_tag GPDI357; /* offset: 0x0965 size: 8 bit */
3073  SIUL_GPDI_8B_tag GPDI358; /* offset: 0x0966 size: 8 bit */
3074  SIUL_GPDI_8B_tag GPDI359; /* offset: 0x0967 size: 8 bit */
3075  SIUL_GPDI_8B_tag GPDI360; /* offset: 0x0968 size: 8 bit */
3076  SIUL_GPDI_8B_tag GPDI361; /* offset: 0x0969 size: 8 bit */
3077  SIUL_GPDI_8B_tag GPDI362; /* offset: 0x096A size: 8 bit */
3078  SIUL_GPDI_8B_tag GPDI363; /* offset: 0x096B size: 8 bit */
3079  SIUL_GPDI_8B_tag GPDI364; /* offset: 0x096C size: 8 bit */
3080  SIUL_GPDI_8B_tag GPDI365; /* offset: 0x096D size: 8 bit */
3081  SIUL_GPDI_8B_tag GPDI366; /* offset: 0x096E size: 8 bit */
3082  SIUL_GPDI_8B_tag GPDI367; /* offset: 0x096F size: 8 bit */
3083  SIUL_GPDI_8B_tag GPDI368; /* offset: 0x0970 size: 8 bit */
3084  SIUL_GPDI_8B_tag GPDI369; /* offset: 0x0971 size: 8 bit */
3085  SIUL_GPDI_8B_tag GPDI370; /* offset: 0x0972 size: 8 bit */
3086  SIUL_GPDI_8B_tag GPDI371; /* offset: 0x0973 size: 8 bit */
3087  SIUL_GPDI_8B_tag GPDI372; /* offset: 0x0974 size: 8 bit */
3088  SIUL_GPDI_8B_tag GPDI373; /* offset: 0x0975 size: 8 bit */
3089  SIUL_GPDI_8B_tag GPDI374; /* offset: 0x0976 size: 8 bit */
3090  SIUL_GPDI_8B_tag GPDI375; /* offset: 0x0977 size: 8 bit */
3091  SIUL_GPDI_8B_tag GPDI376; /* offset: 0x0978 size: 8 bit */
3092  SIUL_GPDI_8B_tag GPDI377; /* offset: 0x0979 size: 8 bit */
3093  SIUL_GPDI_8B_tag GPDI378; /* offset: 0x097A size: 8 bit */
3094  SIUL_GPDI_8B_tag GPDI379; /* offset: 0x097B size: 8 bit */
3095  SIUL_GPDI_8B_tag GPDI380; /* offset: 0x097C size: 8 bit */
3096  SIUL_GPDI_8B_tag GPDI381; /* offset: 0x097D size: 8 bit */
3097  SIUL_GPDI_8B_tag GPDI382; /* offset: 0x097E size: 8 bit */
3098  SIUL_GPDI_8B_tag GPDI383; /* offset: 0x097F size: 8 bit */
3099  SIUL_GPDI_8B_tag GPDI384; /* offset: 0x0980 size: 8 bit */
3100  SIUL_GPDI_8B_tag GPDI385; /* offset: 0x0981 size: 8 bit */
3101  SIUL_GPDI_8B_tag GPDI386; /* offset: 0x0982 size: 8 bit */
3102  SIUL_GPDI_8B_tag GPDI387; /* offset: 0x0983 size: 8 bit */
3103  SIUL_GPDI_8B_tag GPDI388; /* offset: 0x0984 size: 8 bit */
3104  SIUL_GPDI_8B_tag GPDI389; /* offset: 0x0985 size: 8 bit */
3105  SIUL_GPDI_8B_tag GPDI390; /* offset: 0x0986 size: 8 bit */
3106  SIUL_GPDI_8B_tag GPDI391; /* offset: 0x0987 size: 8 bit */
3107  SIUL_GPDI_8B_tag GPDI392; /* offset: 0x0988 size: 8 bit */
3108  SIUL_GPDI_8B_tag GPDI393; /* offset: 0x0989 size: 8 bit */
3109  SIUL_GPDI_8B_tag GPDI394; /* offset: 0x098A size: 8 bit */
3110  SIUL_GPDI_8B_tag GPDI395; /* offset: 0x098B size: 8 bit */
3111  SIUL_GPDI_8B_tag GPDI396; /* offset: 0x098C size: 8 bit */
3112  SIUL_GPDI_8B_tag GPDI397; /* offset: 0x098D size: 8 bit */
3113  SIUL_GPDI_8B_tag GPDI398; /* offset: 0x098E size: 8 bit */
3114  SIUL_GPDI_8B_tag GPDI399; /* offset: 0x098F size: 8 bit */
3115  SIUL_GPDI_8B_tag GPDI400; /* offset: 0x0990 size: 8 bit */
3116  SIUL_GPDI_8B_tag GPDI401; /* offset: 0x0991 size: 8 bit */
3117  SIUL_GPDI_8B_tag GPDI402; /* offset: 0x0992 size: 8 bit */
3118  SIUL_GPDI_8B_tag GPDI403; /* offset: 0x0993 size: 8 bit */
3119  SIUL_GPDI_8B_tag GPDI404; /* offset: 0x0994 size: 8 bit */
3120  SIUL_GPDI_8B_tag GPDI405; /* offset: 0x0995 size: 8 bit */
3121  SIUL_GPDI_8B_tag GPDI406; /* offset: 0x0996 size: 8 bit */
3122  SIUL_GPDI_8B_tag GPDI407; /* offset: 0x0997 size: 8 bit */
3123  SIUL_GPDI_8B_tag GPDI408; /* offset: 0x0998 size: 8 bit */
3124  SIUL_GPDI_8B_tag GPDI409; /* offset: 0x0999 size: 8 bit */
3125  SIUL_GPDI_8B_tag GPDI410; /* offset: 0x099A size: 8 bit */
3126  SIUL_GPDI_8B_tag GPDI411; /* offset: 0x099B size: 8 bit */
3127  SIUL_GPDI_8B_tag GPDI412; /* offset: 0x099C size: 8 bit */
3128  SIUL_GPDI_8B_tag GPDI413; /* offset: 0x099D size: 8 bit */
3129  SIUL_GPDI_8B_tag GPDI414; /* offset: 0x099E size: 8 bit */
3130  SIUL_GPDI_8B_tag GPDI415; /* offset: 0x099F size: 8 bit */
3131  SIUL_GPDI_8B_tag GPDI416; /* offset: 0x09A0 size: 8 bit */
3132  SIUL_GPDI_8B_tag GPDI417; /* offset: 0x09A1 size: 8 bit */
3133  SIUL_GPDI_8B_tag GPDI418; /* offset: 0x09A2 size: 8 bit */
3134  SIUL_GPDI_8B_tag GPDI419; /* offset: 0x09A3 size: 8 bit */
3135  SIUL_GPDI_8B_tag GPDI420; /* offset: 0x09A4 size: 8 bit */
3136  SIUL_GPDI_8B_tag GPDI421; /* offset: 0x09A5 size: 8 bit */
3137  SIUL_GPDI_8B_tag GPDI422; /* offset: 0x09A6 size: 8 bit */
3138  SIUL_GPDI_8B_tag GPDI423; /* offset: 0x09A7 size: 8 bit */
3139  SIUL_GPDI_8B_tag GPDI424; /* offset: 0x09A8 size: 8 bit */
3140  SIUL_GPDI_8B_tag GPDI425; /* offset: 0x09A9 size: 8 bit */
3141  SIUL_GPDI_8B_tag GPDI426; /* offset: 0x09AA size: 8 bit */
3142  SIUL_GPDI_8B_tag GPDI427; /* offset: 0x09AB size: 8 bit */
3143  SIUL_GPDI_8B_tag GPDI428; /* offset: 0x09AC size: 8 bit */
3144  SIUL_GPDI_8B_tag GPDI429; /* offset: 0x09AD size: 8 bit */
3145  SIUL_GPDI_8B_tag GPDI430; /* offset: 0x09AE size: 8 bit */
3146  SIUL_GPDI_8B_tag GPDI431; /* offset: 0x09AF size: 8 bit */
3147  SIUL_GPDI_8B_tag GPDI432; /* offset: 0x09B0 size: 8 bit */
3148  SIUL_GPDI_8B_tag GPDI433; /* offset: 0x09B1 size: 8 bit */
3149  SIUL_GPDI_8B_tag GPDI434; /* offset: 0x09B2 size: 8 bit */
3150  SIUL_GPDI_8B_tag GPDI435; /* offset: 0x09B3 size: 8 bit */
3151  SIUL_GPDI_8B_tag GPDI436; /* offset: 0x09B4 size: 8 bit */
3152  SIUL_GPDI_8B_tag GPDI437; /* offset: 0x09B5 size: 8 bit */
3153  SIUL_GPDI_8B_tag GPDI438; /* offset: 0x09B6 size: 8 bit */
3154  SIUL_GPDI_8B_tag GPDI439; /* offset: 0x09B7 size: 8 bit */
3155  SIUL_GPDI_8B_tag GPDI440; /* offset: 0x09B8 size: 8 bit */
3156  SIUL_GPDI_8B_tag GPDI441; /* offset: 0x09B9 size: 8 bit */
3157  SIUL_GPDI_8B_tag GPDI442; /* offset: 0x09BA size: 8 bit */
3158  SIUL_GPDI_8B_tag GPDI443; /* offset: 0x09BB size: 8 bit */
3159  SIUL_GPDI_8B_tag GPDI444; /* offset: 0x09BC size: 8 bit */
3160  SIUL_GPDI_8B_tag GPDI445; /* offset: 0x09BD size: 8 bit */
3161  SIUL_GPDI_8B_tag GPDI446; /* offset: 0x09BE size: 8 bit */
3162  SIUL_GPDI_8B_tag GPDI447; /* offset: 0x09BF size: 8 bit */
3163  SIUL_GPDI_8B_tag GPDI448; /* offset: 0x09C0 size: 8 bit */
3164  SIUL_GPDI_8B_tag GPDI449; /* offset: 0x09C1 size: 8 bit */
3165  SIUL_GPDI_8B_tag GPDI450; /* offset: 0x09C2 size: 8 bit */
3166  SIUL_GPDI_8B_tag GPDI451; /* offset: 0x09C3 size: 8 bit */
3167  SIUL_GPDI_8B_tag GPDI452; /* offset: 0x09C4 size: 8 bit */
3168  SIUL_GPDI_8B_tag GPDI453; /* offset: 0x09C5 size: 8 bit */
3169  SIUL_GPDI_8B_tag GPDI454; /* offset: 0x09C6 size: 8 bit */
3170  SIUL_GPDI_8B_tag GPDI455; /* offset: 0x09C7 size: 8 bit */
3171  SIUL_GPDI_8B_tag GPDI456; /* offset: 0x09C8 size: 8 bit */
3172  SIUL_GPDI_8B_tag GPDI457; /* offset: 0x09C9 size: 8 bit */
3173  SIUL_GPDI_8B_tag GPDI458; /* offset: 0x09CA size: 8 bit */
3174  SIUL_GPDI_8B_tag GPDI459; /* offset: 0x09CB size: 8 bit */
3175  SIUL_GPDI_8B_tag GPDI460; /* offset: 0x09CC size: 8 bit */
3176  SIUL_GPDI_8B_tag GPDI461; /* offset: 0x09CD size: 8 bit */
3177  SIUL_GPDI_8B_tag GPDI462; /* offset: 0x09CE size: 8 bit */
3178  SIUL_GPDI_8B_tag GPDI463; /* offset: 0x09CF size: 8 bit */
3179  SIUL_GPDI_8B_tag GPDI464; /* offset: 0x09D0 size: 8 bit */
3180  SIUL_GPDI_8B_tag GPDI465; /* offset: 0x09D1 size: 8 bit */
3181  SIUL_GPDI_8B_tag GPDI466; /* offset: 0x09D2 size: 8 bit */
3182  SIUL_GPDI_8B_tag GPDI467; /* offset: 0x09D3 size: 8 bit */
3183  SIUL_GPDI_8B_tag GPDI468; /* offset: 0x09D4 size: 8 bit */
3184  SIUL_GPDI_8B_tag GPDI469; /* offset: 0x09D5 size: 8 bit */
3185  SIUL_GPDI_8B_tag GPDI470; /* offset: 0x09D6 size: 8 bit */
3186  SIUL_GPDI_8B_tag GPDI471; /* offset: 0x09D7 size: 8 bit */
3187  SIUL_GPDI_8B_tag GPDI472; /* offset: 0x09D8 size: 8 bit */
3188  SIUL_GPDI_8B_tag GPDI473; /* offset: 0x09D9 size: 8 bit */
3189  SIUL_GPDI_8B_tag GPDI474; /* offset: 0x09DA size: 8 bit */
3190  SIUL_GPDI_8B_tag GPDI475; /* offset: 0x09DB size: 8 bit */
3191  SIUL_GPDI_8B_tag GPDI476; /* offset: 0x09DC size: 8 bit */
3192  SIUL_GPDI_8B_tag GPDI477; /* offset: 0x09DD size: 8 bit */
3193  SIUL_GPDI_8B_tag GPDI478; /* offset: 0x09DE size: 8 bit */
3194  SIUL_GPDI_8B_tag GPDI479; /* offset: 0x09DF size: 8 bit */
3195  SIUL_GPDI_8B_tag GPDI480; /* offset: 0x09E0 size: 8 bit */
3196  SIUL_GPDI_8B_tag GPDI481; /* offset: 0x09E1 size: 8 bit */
3197  SIUL_GPDI_8B_tag GPDI482; /* offset: 0x09E2 size: 8 bit */
3198  SIUL_GPDI_8B_tag GPDI483; /* offset: 0x09E3 size: 8 bit */
3199  SIUL_GPDI_8B_tag GPDI484; /* offset: 0x09E4 size: 8 bit */
3200  SIUL_GPDI_8B_tag GPDI485; /* offset: 0x09E5 size: 8 bit */
3201  SIUL_GPDI_8B_tag GPDI486; /* offset: 0x09E6 size: 8 bit */
3202  SIUL_GPDI_8B_tag GPDI487; /* offset: 0x09E7 size: 8 bit */
3203  SIUL_GPDI_8B_tag GPDI488; /* offset: 0x09E8 size: 8 bit */
3204  SIUL_GPDI_8B_tag GPDI489; /* offset: 0x09E9 size: 8 bit */
3205  SIUL_GPDI_8B_tag GPDI490; /* offset: 0x09EA size: 8 bit */
3206  SIUL_GPDI_8B_tag GPDI491; /* offset: 0x09EB size: 8 bit */
3207  SIUL_GPDI_8B_tag GPDI492; /* offset: 0x09EC size: 8 bit */
3208  SIUL_GPDI_8B_tag GPDI493; /* offset: 0x09ED size: 8 bit */
3209  SIUL_GPDI_8B_tag GPDI494; /* offset: 0x09EE size: 8 bit */
3210  SIUL_GPDI_8B_tag GPDI495; /* offset: 0x09EF size: 8 bit */
3211  SIUL_GPDI_8B_tag GPDI496; /* offset: 0x09F0 size: 8 bit */
3212  SIUL_GPDI_8B_tag GPDI497; /* offset: 0x09F1 size: 8 bit */
3213  SIUL_GPDI_8B_tag GPDI498; /* offset: 0x09F2 size: 8 bit */
3214  SIUL_GPDI_8B_tag GPDI499; /* offset: 0x09F3 size: 8 bit */
3215  SIUL_GPDI_8B_tag GPDI500; /* offset: 0x09F4 size: 8 bit */
3216  SIUL_GPDI_8B_tag GPDI501; /* offset: 0x09F5 size: 8 bit */
3217  SIUL_GPDI_8B_tag GPDI502; /* offset: 0x09F6 size: 8 bit */
3218  SIUL_GPDI_8B_tag GPDI503; /* offset: 0x09F7 size: 8 bit */
3219  SIUL_GPDI_8B_tag GPDI504; /* offset: 0x09F8 size: 8 bit */
3220  SIUL_GPDI_8B_tag GPDI505; /* offset: 0x09F9 size: 8 bit */
3221  SIUL_GPDI_8B_tag GPDI506; /* offset: 0x09FA size: 8 bit */
3222  SIUL_GPDI_8B_tag GPDI507; /* offset: 0x09FB size: 8 bit */
3223  SIUL_GPDI_8B_tag GPDI508; /* offset: 0x09FC size: 8 bit */
3224  SIUL_GPDI_8B_tag GPDI509; /* offset: 0x09FD size: 8 bit */
3225  SIUL_GPDI_8B_tag GPDI510; /* offset: 0x09FE size: 8 bit */
3226  SIUL_GPDI_8B_tag GPDI511; /* offset: 0x09FF size: 8 bit */
3227  };
3228 
3229  };
3230  int8_t SIUL_reserved_0A00_C[512];
3231  union {
3232  /* PGPDO - Parallel GPIO Pad Data Out Register */
3233  SIUL_PGPDO_16B_tag PGPDO[32]; /* offset: 0x0C00 (0x0002 x 32) */
3234 
3235  struct {
3236  /* PGPDO - Parallel GPIO Pad Data Out Register */
3237  SIUL_PGPDO_16B_tag PGPDO0; /* offset: 0x0C00 size: 16 bit */
3238  SIUL_PGPDO_16B_tag PGPDO1; /* offset: 0x0C02 size: 16 bit */
3239  SIUL_PGPDO_16B_tag PGPDO2; /* offset: 0x0C04 size: 16 bit */
3240  SIUL_PGPDO_16B_tag PGPDO3; /* offset: 0x0C06 size: 16 bit */
3241  SIUL_PGPDO_16B_tag PGPDO4; /* offset: 0x0C08 size: 16 bit */
3242  SIUL_PGPDO_16B_tag PGPDO5; /* offset: 0x0C0A size: 16 bit */
3243  SIUL_PGPDO_16B_tag PGPDO6; /* offset: 0x0C0C size: 16 bit */
3244  SIUL_PGPDO_16B_tag PGPDO7; /* offset: 0x0C0E size: 16 bit */
3245  SIUL_PGPDO_16B_tag PGPDO8; /* offset: 0x0C10 size: 16 bit */
3246  SIUL_PGPDO_16B_tag PGPDO9; /* offset: 0x0C12 size: 16 bit */
3247  SIUL_PGPDO_16B_tag PGPDO10; /* offset: 0x0C14 size: 16 bit */
3248  SIUL_PGPDO_16B_tag PGPDO11; /* offset: 0x0C16 size: 16 bit */
3249  SIUL_PGPDO_16B_tag PGPDO12; /* offset: 0x0C18 size: 16 bit */
3250  SIUL_PGPDO_16B_tag PGPDO13; /* offset: 0x0C1A size: 16 bit */
3251  SIUL_PGPDO_16B_tag PGPDO14; /* offset: 0x0C1C size: 16 bit */
3252  SIUL_PGPDO_16B_tag PGPDO15; /* offset: 0x0C1E size: 16 bit */
3253  SIUL_PGPDO_16B_tag PGPDO16; /* offset: 0x0C20 size: 16 bit */
3254  SIUL_PGPDO_16B_tag PGPDO17; /* offset: 0x0C22 size: 16 bit */
3255  SIUL_PGPDO_16B_tag PGPDO18; /* offset: 0x0C24 size: 16 bit */
3256  SIUL_PGPDO_16B_tag PGPDO19; /* offset: 0x0C26 size: 16 bit */
3257  SIUL_PGPDO_16B_tag PGPDO20; /* offset: 0x0C28 size: 16 bit */
3258  SIUL_PGPDO_16B_tag PGPDO21; /* offset: 0x0C2A size: 16 bit */
3259  SIUL_PGPDO_16B_tag PGPDO22; /* offset: 0x0C2C size: 16 bit */
3260  SIUL_PGPDO_16B_tag PGPDO23; /* offset: 0x0C2E size: 16 bit */
3261  SIUL_PGPDO_16B_tag PGPDO24; /* offset: 0x0C30 size: 16 bit */
3262  SIUL_PGPDO_16B_tag PGPDO25; /* offset: 0x0C32 size: 16 bit */
3263  SIUL_PGPDO_16B_tag PGPDO26; /* offset: 0x0C34 size: 16 bit */
3264  SIUL_PGPDO_16B_tag PGPDO27; /* offset: 0x0C36 size: 16 bit */
3265  SIUL_PGPDO_16B_tag PGPDO28; /* offset: 0x0C38 size: 16 bit */
3266  SIUL_PGPDO_16B_tag PGPDO29; /* offset: 0x0C3A size: 16 bit */
3267  SIUL_PGPDO_16B_tag PGPDO30; /* offset: 0x0C3C size: 16 bit */
3268  SIUL_PGPDO_16B_tag PGPDO31; /* offset: 0x0C3E size: 16 bit */
3269  };
3270 
3271  };
3272  union {
3273  /* PGPDI - Parallel GPIO Pad Data In Register */
3274  SIUL_PGPDI_16B_tag PGPDI[32]; /* offset: 0x0C40 (0x0002 x 32) */
3275 
3276  struct {
3277  /* PGPDI - Parallel GPIO Pad Data In Register */
3278  SIUL_PGPDI_16B_tag PGPDI0; /* offset: 0x0C40 size: 16 bit */
3279  SIUL_PGPDI_16B_tag PGPDI1; /* offset: 0x0C42 size: 16 bit */
3280  SIUL_PGPDI_16B_tag PGPDI2; /* offset: 0x0C44 size: 16 bit */
3281  SIUL_PGPDI_16B_tag PGPDI3; /* offset: 0x0C46 size: 16 bit */
3282  SIUL_PGPDI_16B_tag PGPDI4; /* offset: 0x0C48 size: 16 bit */
3283  SIUL_PGPDI_16B_tag PGPDI5; /* offset: 0x0C4A size: 16 bit */
3284  SIUL_PGPDI_16B_tag PGPDI6; /* offset: 0x0C4C size: 16 bit */
3285  SIUL_PGPDI_16B_tag PGPDI7; /* offset: 0x0C4E size: 16 bit */
3286  SIUL_PGPDI_16B_tag PGPDI8; /* offset: 0x0C50 size: 16 bit */
3287  SIUL_PGPDI_16B_tag PGPDI9; /* offset: 0x0C52 size: 16 bit */
3288  SIUL_PGPDI_16B_tag PGPDI10; /* offset: 0x0C54 size: 16 bit */
3289  SIUL_PGPDI_16B_tag PGPDI11; /* offset: 0x0C56 size: 16 bit */
3290  SIUL_PGPDI_16B_tag PGPDI12; /* offset: 0x0C58 size: 16 bit */
3291  SIUL_PGPDI_16B_tag PGPDI13; /* offset: 0x0C5A size: 16 bit */
3292  SIUL_PGPDI_16B_tag PGPDI14; /* offset: 0x0C5C size: 16 bit */
3293  SIUL_PGPDI_16B_tag PGPDI15; /* offset: 0x0C5E size: 16 bit */
3294  SIUL_PGPDI_16B_tag PGPDI16; /* offset: 0x0C60 size: 16 bit */
3295  SIUL_PGPDI_16B_tag PGPDI17; /* offset: 0x0C62 size: 16 bit */
3296  SIUL_PGPDI_16B_tag PGPDI18; /* offset: 0x0C64 size: 16 bit */
3297  SIUL_PGPDI_16B_tag PGPDI19; /* offset: 0x0C66 size: 16 bit */
3298  SIUL_PGPDI_16B_tag PGPDI20; /* offset: 0x0C68 size: 16 bit */
3299  SIUL_PGPDI_16B_tag PGPDI21; /* offset: 0x0C6A size: 16 bit */
3300  SIUL_PGPDI_16B_tag PGPDI22; /* offset: 0x0C6C size: 16 bit */
3301  SIUL_PGPDI_16B_tag PGPDI23; /* offset: 0x0C6E size: 16 bit */
3302  SIUL_PGPDI_16B_tag PGPDI24; /* offset: 0x0C70 size: 16 bit */
3303  SIUL_PGPDI_16B_tag PGPDI25; /* offset: 0x0C72 size: 16 bit */
3304  SIUL_PGPDI_16B_tag PGPDI26; /* offset: 0x0C74 size: 16 bit */
3305  SIUL_PGPDI_16B_tag PGPDI27; /* offset: 0x0C76 size: 16 bit */
3306  SIUL_PGPDI_16B_tag PGPDI28; /* offset: 0x0C78 size: 16 bit */
3307  SIUL_PGPDI_16B_tag PGPDI29; /* offset: 0x0C7A size: 16 bit */
3308  SIUL_PGPDI_16B_tag PGPDI30; /* offset: 0x0C7C size: 16 bit */
3309  SIUL_PGPDI_16B_tag PGPDI31; /* offset: 0x0C7E size: 16 bit */
3310  };
3311 
3312  };
3313  union {
3314  /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */
3315  SIUL_MPGPDO_32B_tag MPGPDO[32]; /* offset: 0x0C80 (0x0004 x 32) */
3316 
3317  struct {
3318  /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */
3319  SIUL_MPGPDO_32B_tag MPGPDO0; /* offset: 0x0C80 size: 32 bit */
3320  SIUL_MPGPDO_32B_tag MPGPDO1; /* offset: 0x0C84 size: 32 bit */
3321  SIUL_MPGPDO_32B_tag MPGPDO2; /* offset: 0x0C88 size: 32 bit */
3322  SIUL_MPGPDO_32B_tag MPGPDO3; /* offset: 0x0C8C size: 32 bit */
3323  SIUL_MPGPDO_32B_tag MPGPDO4; /* offset: 0x0C90 size: 32 bit */
3324  SIUL_MPGPDO_32B_tag MPGPDO5; /* offset: 0x0C94 size: 32 bit */
3325  SIUL_MPGPDO_32B_tag MPGPDO6; /* offset: 0x0C98 size: 32 bit */
3326  SIUL_MPGPDO_32B_tag MPGPDO7; /* offset: 0x0C9C size: 32 bit */
3327  SIUL_MPGPDO_32B_tag MPGPDO8; /* offset: 0x0CA0 size: 32 bit */
3328  SIUL_MPGPDO_32B_tag MPGPDO9; /* offset: 0x0CA4 size: 32 bit */
3329  SIUL_MPGPDO_32B_tag MPGPDO10; /* offset: 0x0CA8 size: 32 bit */
3330  SIUL_MPGPDO_32B_tag MPGPDO11; /* offset: 0x0CAC size: 32 bit */
3331  SIUL_MPGPDO_32B_tag MPGPDO12; /* offset: 0x0CB0 size: 32 bit */
3332  SIUL_MPGPDO_32B_tag MPGPDO13; /* offset: 0x0CB4 size: 32 bit */
3333  SIUL_MPGPDO_32B_tag MPGPDO14; /* offset: 0x0CB8 size: 32 bit */
3334  SIUL_MPGPDO_32B_tag MPGPDO15; /* offset: 0x0CBC size: 32 bit */
3335  SIUL_MPGPDO_32B_tag MPGPDO16; /* offset: 0x0CC0 size: 32 bit */
3336  SIUL_MPGPDO_32B_tag MPGPDO17; /* offset: 0x0CC4 size: 32 bit */
3337  SIUL_MPGPDO_32B_tag MPGPDO18; /* offset: 0x0CC8 size: 32 bit */
3338  SIUL_MPGPDO_32B_tag MPGPDO19; /* offset: 0x0CCC size: 32 bit */
3339  SIUL_MPGPDO_32B_tag MPGPDO20; /* offset: 0x0CD0 size: 32 bit */
3340  SIUL_MPGPDO_32B_tag MPGPDO21; /* offset: 0x0CD4 size: 32 bit */
3341  SIUL_MPGPDO_32B_tag MPGPDO22; /* offset: 0x0CD8 size: 32 bit */
3342  SIUL_MPGPDO_32B_tag MPGPDO23; /* offset: 0x0CDC size: 32 bit */
3343  SIUL_MPGPDO_32B_tag MPGPDO24; /* offset: 0x0CE0 size: 32 bit */
3344  SIUL_MPGPDO_32B_tag MPGPDO25; /* offset: 0x0CE4 size: 32 bit */
3345  SIUL_MPGPDO_32B_tag MPGPDO26; /* offset: 0x0CE8 size: 32 bit */
3346  SIUL_MPGPDO_32B_tag MPGPDO27; /* offset: 0x0CEC size: 32 bit */
3347  SIUL_MPGPDO_32B_tag MPGPDO28; /* offset: 0x0CF0 size: 32 bit */
3348  SIUL_MPGPDO_32B_tag MPGPDO29; /* offset: 0x0CF4 size: 32 bit */
3349  SIUL_MPGPDO_32B_tag MPGPDO30; /* offset: 0x0CF8 size: 32 bit */
3350  SIUL_MPGPDO_32B_tag MPGPDO31; /* offset: 0x0CFC size: 32 bit */
3351  };
3352 
3353  };
3354  int8_t SIUL_reserved_0D00_C[768];
3355  union {
3356  /* IFMC - Interrupt Filter Maximum Counter Register */
3357  SIUL_IFMC_32B_tag IFMC[32]; /* offset: 0x1000 (0x0004 x 32) */
3358 
3359  struct {
3360  /* IFMC - Interrupt Filter Maximum Counter Register */
3361  SIUL_IFMC_32B_tag IFMC0; /* offset: 0x1000 size: 32 bit */
3362  SIUL_IFMC_32B_tag IFMC1; /* offset: 0x1004 size: 32 bit */
3363  SIUL_IFMC_32B_tag IFMC2; /* offset: 0x1008 size: 32 bit */
3364  SIUL_IFMC_32B_tag IFMC3; /* offset: 0x100C size: 32 bit */
3365  SIUL_IFMC_32B_tag IFMC4; /* offset: 0x1010 size: 32 bit */
3366  SIUL_IFMC_32B_tag IFMC5; /* offset: 0x1014 size: 32 bit */
3367  SIUL_IFMC_32B_tag IFMC6; /* offset: 0x1018 size: 32 bit */
3368  SIUL_IFMC_32B_tag IFMC7; /* offset: 0x101C size: 32 bit */
3369  SIUL_IFMC_32B_tag IFMC8; /* offset: 0x1020 size: 32 bit */
3370  SIUL_IFMC_32B_tag IFMC9; /* offset: 0x1024 size: 32 bit */
3371  SIUL_IFMC_32B_tag IFMC10; /* offset: 0x1028 size: 32 bit */
3372  SIUL_IFMC_32B_tag IFMC11; /* offset: 0x102C size: 32 bit */
3373  SIUL_IFMC_32B_tag IFMC12; /* offset: 0x1030 size: 32 bit */
3374  SIUL_IFMC_32B_tag IFMC13; /* offset: 0x1034 size: 32 bit */
3375  SIUL_IFMC_32B_tag IFMC14; /* offset: 0x1038 size: 32 bit */
3376  SIUL_IFMC_32B_tag IFMC15; /* offset: 0x103C size: 32 bit */
3377  SIUL_IFMC_32B_tag IFMC16; /* offset: 0x1040 size: 32 bit */
3378  SIUL_IFMC_32B_tag IFMC17; /* offset: 0x1044 size: 32 bit */
3379  SIUL_IFMC_32B_tag IFMC18; /* offset: 0x1048 size: 32 bit */
3380  SIUL_IFMC_32B_tag IFMC19; /* offset: 0x104C size: 32 bit */
3381  SIUL_IFMC_32B_tag IFMC20; /* offset: 0x1050 size: 32 bit */
3382  SIUL_IFMC_32B_tag IFMC21; /* offset: 0x1054 size: 32 bit */
3383  SIUL_IFMC_32B_tag IFMC22; /* offset: 0x1058 size: 32 bit */
3384  SIUL_IFMC_32B_tag IFMC23; /* offset: 0x105C size: 32 bit */
3385  SIUL_IFMC_32B_tag IFMC24; /* offset: 0x1060 size: 32 bit */
3386  SIUL_IFMC_32B_tag IFMC25; /* offset: 0x1064 size: 32 bit */
3387  SIUL_IFMC_32B_tag IFMC26; /* offset: 0x1068 size: 32 bit */
3388  SIUL_IFMC_32B_tag IFMC27; /* offset: 0x106C size: 32 bit */
3389  SIUL_IFMC_32B_tag IFMC28; /* offset: 0x1070 size: 32 bit */
3390  SIUL_IFMC_32B_tag IFMC29; /* offset: 0x1074 size: 32 bit */
3391  SIUL_IFMC_32B_tag IFMC30; /* offset: 0x1078 size: 32 bit */
3392  SIUL_IFMC_32B_tag IFMC31; /* offset: 0x107C size: 32 bit */
3393  };
3394 
3395  };
3396  /* IFCPR - Inerrupt Filter Clock Prescaler Register */
3397  SIUL_IFCPR_32B_tag IFCPR; /* offset: 0x1080 size: 32 bit */
3398  } SIUL_tag;
3399 
3400 
3401 #define SIUL (*(volatile SIUL_tag *) 0xC3F90000UL)
3402 
3403 
3404 
3405 /****************************************************************/
3406 /* */
3407 /* Module: WKPU */
3408 /* */
3409 /****************************************************************/
3410 
3411  typedef union { /* WKPU_NSR - NMI Status Flag Register */
3412  vuint32_t R;
3413  struct {
3414  vuint32_t NIF0:1; /* NMI Status Flag 0 */
3415  vuint32_t NOVF0:1; /* NMI Overrun Status Flag 0 */
3416  vuint32_t:6;
3417  vuint32_t NIF1:1; /* NMI Status Flag 1 */
3418  vuint32_t NOVF1:1; /* NMI Overrun Status Flag 1 */
3419  vuint32_t:6;
3420  vuint32_t NIF2:1; /* NMI Status Flag 2 */
3421  vuint32_t NOVF2:1; /* NMI Overrun Status Flag 2 */
3422  vuint32_t:6;
3423  vuint32_t NIF3:1; /* NMI Status Flag 3 */
3424  vuint32_t NOVF3:1; /* NMI Overrun Status Flag 3 */
3425  vuint32_t:6;
3426  } B;
3427  } WKPU_NSR_32B_tag;
3428 
3429  typedef union { /* WKPU_NCR - NMI Configuration Register */
3430  vuint32_t R;
3431  struct {
3432  vuint32_t NLOCK0:1; /* NMI Configuration Lock Register 0 */
3433  vuint32_t NDSS0:2; /* NMI Desination Source Select 0 */
3434  vuint32_t NWRE0:1; /* NMI Wakeup Request Enable 0 */
3435  vuint32_t:1;
3436  vuint32_t NREE0:1; /* NMI Rising Edge Events Enable 0 */
3437  vuint32_t NFEE0:1; /* NMI Falling Edge Events Enable 0 */
3438  vuint32_t NFE0:1; /* NMI Filter Enable 0 */
3439  vuint32_t NLOCK1:1; /* NMI Configuration Lock Register 1 */
3440  vuint32_t NDSS1:2; /* NMI Desination Source Select 1 */
3441  vuint32_t NWRE1:1; /* NMI Wakeup Request Enable 1 */
3442  vuint32_t:1;
3443  vuint32_t NREE1:1; /* NMI Rising Edge Events Enable 1 */
3444  vuint32_t NFEE1:1; /* NMI Falling Edge Events Enable 1 */
3445  vuint32_t NFE1:1; /* NMI Filter Enable 1 */
3446  vuint32_t NLOCK2:1; /* NMI Configuration Lock Register 2 */
3447  vuint32_t NDSS2:2; /* NMI Desination Source Select 2 */
3448  vuint32_t NWRE2:1; /* NMI Wakeup Request Enable 2 */
3449  vuint32_t:1;
3450  vuint32_t NREE2:1; /* NMI Rising Edge Events Enable 2 */
3451  vuint32_t NFEE2:1; /* NMI Falling Edge Events Enable 2 */
3452  vuint32_t NFE2:1; /* NMI Filter Enable 2 */
3453  vuint32_t NLOCK3:1; /* NMI Configuration Lock Register 3 */
3454  vuint32_t NDSS3:2; /* NMI Desination Source Select 3 */
3455  vuint32_t NWRE3:1; /* NMI Wakeup Request Enable 3 */
3456  vuint32_t:1;
3457  vuint32_t NREE3:1; /* NMI Rising Edge Events Enable 3 */
3458  vuint32_t NFEE3:1; /* NMI Falling Edge Events Enable 3 */
3459  vuint32_t NFE3:1; /* NMI Filter Enable 3 */
3460  } B;
3461  } WKPU_NCR_32B_tag;
3462 
3463  typedef union { /* WKPU_WISR - Wakeup/Interrupt Status Flag Register */
3464  vuint32_t R;
3465  struct {
3466  vuint32_t EIF:32; /* External Wakeup/Interrupt Status Flag */
3467  } B;
3468  } WKPU_WISR_32B_tag;
3469 
3470  typedef union { /* WKPU_IRER - Interrupt Request Enable Register */
3471  vuint32_t R;
3472  struct {
3473  vuint32_t EIRE:32; /* Enable External Interrupt Requests */
3474  } B;
3475  } WKPU_IRER_32B_tag;
3476 
3477  typedef union { /* WKPU_WRER - Wakeup Request Enable Register */
3478  vuint32_t R;
3479  struct {
3480  vuint32_t WRE:32; /* Enable Wakeup requests to the mode entry module */
3481  } B;
3482  } WKPU_WRER_32B_tag;
3483 
3484  typedef union { /* WKPU_WIREER - Wakeup/Interrupt Rising-Edge Event Enable Register */
3485  vuint32_t R;
3486  struct {
3487  vuint32_t IREE:32; /* Enable rising-edge events to cause EIF[x] to be set */
3488  } B;
3489  } WKPU_WIREER_32B_tag;
3490 
3491  typedef union { /* WKPU_WIFEER - Wakeup/Interrupt Falling-Edge Event Enable Register */
3492  vuint32_t R;
3493  struct {
3494  vuint32_t IFEE:32; /* Enable Falling-edge events to cause EIF[x] to be set */
3495  } B;
3496  } WKPU_WIFEER_32B_tag;
3497 
3498  typedef union { /* WKPU_WIFER - Wakeup/Interrupt Filter Enable Register */
3499  vuint32_t R;
3500  struct {
3501  vuint32_t IFE:32; /* Enable Digital glitch filter on the interrupt pad input */
3502  } B;
3503  } WKPU_WIFER_32B_tag;
3504 
3505  typedef union { /* WKPU_WIPUER - Wakeup/Interrupt Pullup Enable Register */
3506  vuint32_t R;
3507  struct {
3508  vuint32_t IPUE:32; /* Enable a pullup on the interrupt pad input */
3509  } B;
3510  } WKPU_WIPUER_32B_tag;
3511 
3512 
3513 
3514  typedef struct WKPU_struct_tag { /* start of WKPU_tag */
3515  /* WKPU_NSR - NMI Status Flag Register */
3516  WKPU_NSR_32B_tag NSR; /* offset: 0x0000 size: 32 bit */
3517  int8_t WKPU_reserved_0004[4];
3518  /* WKPU_NCR - NMI Configuration Register */
3519  WKPU_NCR_32B_tag NCR; /* offset: 0x0008 size: 32 bit */
3520  int8_t WKPU_reserved_000C[8];
3521  /* WKPU_WISR - Wakeup/Interrupt Status Flag Register */
3522  WKPU_WISR_32B_tag WISR; /* offset: 0x0014 size: 32 bit */
3523  /* WKPU_IRER - Interrupt Request Enable Register */
3524  WKPU_IRER_32B_tag IRER; /* offset: 0x0018 size: 32 bit */
3525  /* WKPU_WRER - Wakeup Request Enable Register */
3526  WKPU_WRER_32B_tag WRER; /* offset: 0x001C size: 32 bit */
3527  int8_t WKPU_reserved_0020[8];
3528  /* WKPU_WIREER - Wakeup/Interrupt Rising-Edge Event Enable Register */
3529  WKPU_WIREER_32B_tag WIREER; /* offset: 0x0028 size: 32 bit */
3530  /* WKPU_WIFEER - Wakeup/Interrupt Falling-Edge Event Enable Register */
3531  WKPU_WIFEER_32B_tag WIFEER; /* offset: 0x002C size: 32 bit */
3532  /* WKPU_WIFER - Wakeup/Interrupt Filter Enable Register */
3533  WKPU_WIFER_32B_tag WIFER; /* offset: 0x0030 size: 32 bit */
3534  /* WKPU_WIPUER - Wakeup/Interrupt Pullup Enable Register */
3535  WKPU_WIPUER_32B_tag WIPUER; /* offset: 0x0034 size: 32 bit */
3536  } WKPU_tag;
3537 
3538 
3539 #define WKPU (*(volatile WKPU_tag *) 0xC3F94000UL)
3540 
3541 
3542 
3543 /****************************************************************/
3544 /* */
3545 /* Module: SSCM */
3546 /* */
3547 /****************************************************************/
3548 
3549  typedef union { /* SSCM_STATUS - System Status Register */
3550  vuint16_t R;
3551  struct {
3552  vuint16_t LSM:1; /* Lock Step Mode */
3553  vuint16_t:2;
3554  vuint16_t NXEN1:1; /* Processor 1 Nexus enabled */
3555  vuint16_t NXEN:1; /* Processor 0 Nexus enabled */
3556  vuint16_t PUB:1; /* Public Serial Access Status */
3557  vuint16_t SEC:1; /* Security Status */
3558  vuint16_t:1;
3559  vuint16_t BMODE:3; /* Device Boot Mode */
3560 #ifndef USE_FIELD_ALIASES_SSCM
3561  vuint16_t VLE:1; /* Variable Length Instruction Mode */
3562 #else
3563  vuint16_t DMID:1; /* deprecated name - please avoid */
3564 #endif
3565  vuint16_t ABD:1; /* Autobaud detection */
3566  vuint16_t:3;
3567  } B;
3568  } SSCM_STATUS_16B_tag;
3569 
3570  typedef union { /* SSCM_MEMCONFIG - System Memory Configuration Register */
3571  vuint16_t R;
3572  struct {
3573  vuint16_t JPIN:10; /* JTAG Part ID Number */
3574  vuint16_t IVLD:1; /* Instruction Flash Valid */
3575  vuint16_t MREV:4; /* Minor Mask Revision */
3576  vuint16_t DVLD:1; /* Data Flash Valid */
3577  } B;
3578  } SSCM_MEMCONFIG_16B_tag;
3579 
3580  typedef union { /* SSCM_ERROR - Error Configuration */
3581  vuint16_t R;
3582  struct {
3583  vuint16_t:14;
3584  vuint16_t PAE:1; /* Peripheral Bus Abort Enable */
3585  vuint16_t RAE:1; /* Register Bus Abort Enable */
3586  } B;
3587  } SSCM_ERROR_16B_tag;
3588 
3589  typedef union { /* SSCM_DEBUGPORT - Debug Status Port Register */
3590  vuint16_t R;
3591  struct {
3592  vuint16_t:13;
3593  vuint16_t DEBUG_MODE:3; /* Debug Status Port Mode */
3594  } B;
3595  } SSCM_DEBUGPORT_16B_tag;
3596 
3597  typedef union { /* SSCM_PWCMPH - Password Comparison Register High */
3598  vuint32_t R;
3599  struct {
3600  vuint32_t PWD_HI:32; /* Password High */
3601  } B;
3602  } SSCM_PWCMPH_32B_tag;
3603 
3604  typedef union { /* SSCM_PWCMPL - Password Comparison Register Low */
3605  vuint32_t R;
3606  struct {
3607  vuint32_t PWD_LO:32; /* Password Low */
3608  } B;
3609  } SSCM_PWCMPL_32B_tag;
3610 
3611  typedef union { /* SSCM_DPMBOOT - Decoupled Parallel Boot Register */
3612  vuint32_t R;
3613  struct {
3614  vuint32_t P2BOOT:30; /* boot location 2nd processor */
3615  vuint32_t DVLE:1; /* VLE mode for 2nd processor */
3616  vuint32_t:1;
3617  } B;
3618  } SSCM_DPMBOOT_32B_tag;
3619 
3620  typedef union { /* SSCM_DPMKEY - Boot Key Register */
3621  vuint32_t R;
3622  struct {
3623  vuint32_t KEY:32; /* Boot Control Key */
3624  } B;
3625  } SSCM_DPMKEY_32B_tag;
3626 
3627  typedef union { /* SSCM_UOPS - User Option Status Register */
3628  vuint32_t R;
3629  struct {
3630  vuint32_t UOPT:32; /* User Option Bits */
3631  } B;
3632  } SSCM_UOPS_32B_tag;
3633 
3634  typedef union { /* SSCM_SCTR - SSCM Control Register */
3635  vuint32_t R;
3636  struct {
3637  vuint32_t:29;
3638  vuint32_t TFE:1; /* Test Flash Enable */
3639  vuint32_t DSL:1; /* Disable Software-Controlled MBIST */
3640  vuint32_t DSM:1; /* Disable Software-Controlled LBIST */
3641  } B;
3642  } SSCM_SCTR_32B_tag;
3643 
3644  typedef union { /* SSCM_TF_INFO0 - TestFlash Information Register 0 */
3645  vuint32_t R;
3646  struct {
3647  vuint32_t TINFO0:32; /* General purpose TestFlash word 0 */
3648  } B;
3649  } SSCM_TF_INFO0_32B_tag;
3650 
3651  typedef union { /* SSCM_TF_INFO1 - TestFlash Information Register 1 */
3652  vuint32_t R;
3653  struct {
3654  vuint32_t TINFO1:32; /* General purpose TestFlash word 1 */
3655  } B;
3656  } SSCM_TF_INFO1_32B_tag;
3657 
3658  typedef union { /* SSCM_TF_INFO2 - TestFlash Information Register 2 */
3659  vuint32_t R;
3660  struct {
3661  vuint32_t TINFO2:32; /* General purpose TestFlash word 2 */
3662  } B;
3663  } SSCM_TF_INFO2_32B_tag;
3664 
3665  typedef union { /* SSCM_TF_INFO3 - TestFlash Information Register 3 */
3666  vuint32_t R;
3667  struct {
3668  vuint32_t TINFO3:32; /* General purpose TestFlash word */
3669  } B;
3670  } SSCM_TF_INFO3_32B_tag;
3671 
3672 
3673 
3674  typedef struct SSCM_struct_tag { /* start of SSCM_tag */
3675  /* SSCM_STATUS - System Status Register */
3676  SSCM_STATUS_16B_tag STATUS; /* offset: 0x0000 size: 16 bit */
3677  /* SSCM_MEMCONFIG - System Memory Configuration Register */
3678  SSCM_MEMCONFIG_16B_tag MEMCONFIG; /* offset: 0x0002 size: 16 bit */
3679  int8_t SSCM_reserved_0004[2];
3680  /* SSCM_ERROR - Error Configuration */
3681  SSCM_ERROR_16B_tag ERROR; /* offset: 0x0006 size: 16 bit */
3682  /* SSCM_DEBUGPORT - Debug Status Port Register */
3683  SSCM_DEBUGPORT_16B_tag DEBUGPORT; /* offset: 0x0008 size: 16 bit */
3684  int8_t SSCM_reserved_000A[2];
3685  /* SSCM_PWCMPH - Password Comparison Register High */
3686  SSCM_PWCMPH_32B_tag PWCMPH; /* offset: 0x000C size: 32 bit */
3687  /* SSCM_PWCMPL - Password Comparison Register Low */
3688  SSCM_PWCMPL_32B_tag PWCMPL; /* offset: 0x0010 size: 32 bit */
3689  int8_t SSCM_reserved_0014[4];
3690  /* SSCM_DPMBOOT - Decoupled Parallel Boot Register */
3691  SSCM_DPMBOOT_32B_tag DPMBOOT; /* offset: 0x0018 size: 32 bit */
3692  /* SSCM_DPMKEY - Boot Key Register */
3693  SSCM_DPMKEY_32B_tag DPMKEY; /* offset: 0x001C size: 32 bit */
3694  /* SSCM_UOPS - User Option Status Register */
3695  SSCM_UOPS_32B_tag UOPS; /* offset: 0x0020 size: 32 bit */
3696  /* SSCM_SCTR - SSCM Control Register */
3697  SSCM_SCTR_32B_tag SCTR; /* offset: 0x0024 size: 32 bit */
3698  /* SSCM_TF_INFO0 - TestFlash Information Register 0 */
3699  SSCM_TF_INFO0_32B_tag TF_INFO0; /* offset: 0x0028 size: 32 bit */
3700  /* SSCM_TF_INFO1 - TestFlash Information Register 1 */
3701  SSCM_TF_INFO1_32B_tag TF_INFO1; /* offset: 0x002C size: 32 bit */
3702  /* SSCM_TF_INFO2 - TestFlash Information Register 2 */
3703  SSCM_TF_INFO2_32B_tag TF_INFO2; /* offset: 0x0030 size: 32 bit */
3704  /* SSCM_TF_INFO3 - TestFlash Information Register 3 */
3705  SSCM_TF_INFO3_32B_tag TF_INFO3; /* offset: 0x0034 size: 32 bit */
3706  } SSCM_tag;
3707 
3708 
3709 #define SSCM (*(volatile SSCM_tag *) 0xC3FD8000UL)
3710 
3711 
3712 
3713 /****************************************************************/
3714 /* */
3715 /* Module: ME */
3716 /* */
3717 /****************************************************************/
3718 
3719  typedef union { /* ME_GS - Global Status Register */
3720  vuint32_t R;
3721  struct {
3722 #ifndef USE_FIELD_ALIASES_ME
3723  vuint32_t S_CURRENT_MODE:4; /* Current device mode status */
3724 #else
3725  vuint32_t S_CURRENTMODE:4; /* deprecated name - please avoid */
3726 #endif
3727  vuint32_t S_MTRANS:1; /* Mode transition status */
3728  vuint32_t:3;
3729  vuint32_t S_PDO:1; /* Output power-down status */
3730  vuint32_t:2;
3731  vuint32_t S_MVR:1; /* Main voltage regulator status */
3732  vuint32_t:2;
3733 #ifndef USE_FIELD_ALIASES_ME
3734  vuint32_t S_FLA:2; /* Flash availability status */
3735 #else
3736  vuint32_t S_CFLA:2; /* deprecated name - please avoid */
3737 #endif
3738  vuint32_t:8;
3739  vuint32_t S_PLL1:1; /* Secondary PLL status */
3740  vuint32_t S_PLL0:1; /* System PLL status */
3741 #ifndef USE_FIELD_ALIASES_ME
3742  vuint32_t S_XOSC:1; /* System crystal oscillator status */
3743 #else
3744  vuint32_t S_OSC:1; /* deprecated name - please avoid */
3745 #endif
3746 #ifndef USE_FIELD_ALIASES_ME
3747  vuint32_t S_IRCOSC:1; /* System RC oscillator status */
3748 #else
3749  vuint32_t S_RC:1; /* deprecated name - please avoid */
3750 #endif
3751  vuint32_t S_SYSCLK:4; /* System clock switch status */
3752  } B;
3753  } ME_GS_32B_tag;
3754 
3755  typedef union { /* ME_MCTL - Mode Control Register */
3756  vuint32_t R;
3757  struct {
3758  vuint32_t TARGET_MODE:4; /* Target device mode */
3759  vuint32_t:12;
3760  vuint32_t KEY:16; /* Control key */
3761  } B;
3762  } ME_MCTL_32B_tag;
3763 
3764  typedef union { /* ME_MEN - Mode Enable Register */
3765  vuint32_t R;
3766  struct {
3767  vuint32_t:21;
3768  vuint32_t STOP0:1; /* STOP0 mode enable */
3769  vuint32_t:1;
3770  vuint32_t HALT0:1; /* HALT0 mode enable */
3771  vuint32_t RUN3:1; /* RUN3 mode enable */
3772  vuint32_t RUN2:1; /* RUN2 mode enable */
3773  vuint32_t RUN1:1; /* RUN1 mode enable */
3774  vuint32_t RUN0:1; /* RUN0 mode enable */
3775  vuint32_t DRUN:1; /* DRUN mode enable */
3776  vuint32_t SAFE:1; /* SAFE mode enable */
3777  vuint32_t:1;
3778  vuint32_t RESET:1; /* RESET mode enable */
3779  } B;
3780  } ME_MEN_32B_tag;
3781 
3782  typedef union { /* ME_IS - Interrupt Status Register */
3783  vuint32_t R;
3784  struct {
3785  vuint32_t:28;
3786 #ifndef USE_FIELD_ALIASES_ME
3787  vuint32_t I_ICONF:1; /* Invalid mode config interrupt */
3788 #else
3789  vuint32_t I_CONF:1; /* deprecated name - please avoid */
3790 #endif
3791 #ifndef USE_FIELD_ALIASES_ME
3792  vuint32_t I_IMODE:1; /* Invalid mode interrupt */
3793 #else
3794  vuint32_t I_MODE:1; /* deprecated name - please avoid */
3795 #endif
3796 #ifndef USE_FIELD_ALIASES_ME
3797  vuint32_t I_SAFE:1; /* SAFE mode interrupt */
3798 #else
3799  vuint32_t I_AFE:1; /* deprecated name - please avoid */
3800 #endif
3801 #ifndef USE_FIELD_ALIASES_ME
3802  vuint32_t I_MTC:1; /* Mode transition complete interrupt */
3803 #else
3804  vuint32_t I_TC:1; /* deprecated name - please avoid */
3805 #endif
3806  } B;
3807  } ME_IS_32B_tag;
3808 
3809  typedef union { /* ME_IM - Interrupt Mask Register */
3810  vuint32_t R;
3811  struct {
3812  vuint32_t:28;
3813 #ifndef USE_FIELD_ALIASES_ME
3814  vuint32_t M_ICONF:1; /* Invalid mode config interrupt mask */
3815 #else
3816  vuint32_t M_CONF:1; /* deprecated name - please avoid */
3817 #endif
3818 #ifndef USE_FIELD_ALIASES_ME
3819  vuint32_t M_IMODE:1; /* Invalid mode interrupt mask */
3820 #else
3821  vuint32_t M_MODE:1; /* deprecated name - please avoid */
3822 #endif
3823 #ifndef USE_FIELD_ALIASES_ME
3824  vuint32_t M_SAFE:1; /* SAFE mode interrupt mask */
3825 #else
3826  vuint32_t M_AFE:1; /* deprecated name - please avoid */
3827 #endif
3828 #ifndef USE_FIELD_ALIASES_ME
3829  vuint32_t M_MTC:1; /* Mode transition complete interrupt mask */
3830 #else
3831  vuint32_t M_TC:1; /* deprecated name - please avoid */
3832 #endif
3833  } B;
3834  } ME_IM_32B_tag;
3835 
3836  typedef union { /* ME_IMTS - Invalid Mode Transition Status Register */
3837  vuint32_t R;
3838  struct {
3839  vuint32_t:27;
3840  vuint32_t S_MTI:1; /* Mode Transition Illegal status */
3841  vuint32_t S_MRI:1; /* Mode Request Illegal status */
3842  vuint32_t S_DMA:1; /* Disabled Mode Access status */
3843  vuint32_t S_NMA:1; /* Non-existing Mode Access status */
3844  vuint32_t S_SEA:1; /* Safe Event Active status */
3845  } B;
3846  } ME_IMTS_32B_tag;
3847 
3848  typedef union { /* ME_DMTS - Debug Mode Transition Status Register */
3849  vuint32_t R;
3850  struct {
3851  vuint32_t PREVIOUS_MODE:4; /* Previous Device Mode */
3852  vuint32_t:4;
3853  vuint32_t MPH_BUSY:1; /* MC_ME/MC_PCU Handshake Busy Indicator */
3854  vuint32_t:2;
3855  vuint32_t PMC_PROG:1; /* MC_PCU Mode Change in Process Indicator */
3856  vuint32_t CORE_DBG:1; /* Processor is in Debug Mode Indicator */
3857  vuint32_t:2;
3858  vuint32_t SMR:1; /* SAFE Mode Request */
3859  vuint32_t:1;
3860  vuint32_t VREG_CSRC_SC:1; /* Main VREG Clock Source State Change Indicator */
3861  vuint32_t CSRC_CSRC_SC:1; /* Other Clock Source State Change Indicator */
3862  vuint32_t IRCOSC_SC:1; /* IRCOSC State Change Indicator */
3863  vuint32_t SCSRC_SC:1; /* Secondary System Clock Sources State Change Indicator */
3864  vuint32_t SYSCLK_SW:1; /* System Clock Switching pending Status Indicator */
3865  vuint32_t:1;
3866  vuint32_t FLASH_SC:1; /* FLASH State Change Indicator */
3867  vuint32_t CDP_PRPH_0_143:1; /* Clock Disable Process Pending Status for Periph. 0-143 */
3868  vuint32_t:4;
3869  vuint32_t CDP_PRPH_64_95:1; /* Clock Disable Process Pending Status for Periph. 64-95 */
3870  vuint32_t CDP_PRPH_32_63:1; /* Clock Disable Process Pending Status for Periph. 32-63 */
3871  vuint32_t CDP_PRPH_0_31:1; /* Clock Disable Process Pending Status for Periph. 0-31 */
3872  } B;
3873  } ME_DMTS_32B_tag;
3874 
3875  typedef union { /* ME_RESET_MC - RESET Mode Configuration Register */
3876  vuint32_t R;
3877  struct {
3878  vuint32_t:8;
3879  vuint32_t PDO:1; /* IOs output power-down control */
3880  vuint32_t:2;
3881  vuint32_t MVRON:1; /* Main voltage regulator control */
3882  vuint32_t:2;
3883 #ifndef USE_FIELD_ALIASES_ME
3884  vuint32_t FLAON:2; /* Code flash power-down control */
3885 #else
3886  vuint32_t CFLAON:2; /* deprecated name - please avoid */
3887 #endif
3888  vuint32_t:8;
3889 #ifndef USE_FIELD_ALIASES_ME
3890  vuint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
3891 #else
3892  vuint32_t PLL2ON:1; /* deprecated name - please avoid */
3893 #endif
3894 #ifndef USE_FIELD_ALIASES_ME
3895  vuint32_t PLL0ON:1; /* System PLL control */
3896 #else
3897  vuint32_t PLL1ON:1; /* deprecated name - please avoid */
3898 #endif
3899 #ifndef USE_FIELD_ALIASES_ME
3900  vuint32_t XOSCON:1; /* System crystal oscillator control */
3901 #else
3902  vuint32_t XOSC0ON:1; /* deprecated name - please avoid */
3903 #endif
3904 #ifndef USE_FIELD_ALIASES_ME
3905  vuint32_t IRCOSCON:1; /* System RC oscillator control */
3906 #else
3907  vuint32_t IRCON:1; /* deprecated name - please avoid */
3908 #endif
3909  vuint32_t SYSCLK:4; /* System clock switch control */
3910  } B;
3911  } ME_RESET_MC_32B_tag;
3912 
3913  typedef union { /* ME_SAFE_MC - Mode Configuration Register */
3914  vuint32_t R;
3915  struct {
3916  vuint32_t:8;
3917  vuint32_t PDO:1; /* IOs output power-down control */
3918  vuint32_t:2;
3919  vuint32_t MVRON:1; /* Main voltage regulator control */
3920  vuint32_t:2;
3921 #ifndef USE_FIELD_ALIASES_ME
3922  vuint32_t FLAON:2; /* Code flash power-down control */
3923 #else
3924  vuint32_t CFLAON:2; /* deprecated name - please avoid */
3925 #endif
3926  vuint32_t:8;
3927 #ifndef USE_FIELD_ALIASES_ME
3928  vuint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
3929 #else
3930  vuint32_t PLL2ON:1; /* deprecated name - please avoid */
3931 #endif
3932 #ifndef USE_FIELD_ALIASES_ME
3933  vuint32_t PLL0ON:1; /* System PLL control */
3934 #else
3935  vuint32_t PLL1ON:1; /* deprecated name - please avoid */
3936 #endif
3937 #ifndef USE_FIELD_ALIASES_ME
3938  vuint32_t XOSCON:1; /* System crystal oscillator control */
3939 #else
3940  vuint32_t XOSC0ON:1; /* deprecated name - please avoid */
3941 #endif
3942 #ifndef USE_FIELD_ALIASES_ME
3943  vuint32_t IRCOSCON:1; /* System RC oscillator control */
3944 #else
3945  vuint32_t IRCON:1; /* deprecated name - please avoid */
3946 #endif
3947  vuint32_t SYSCLK:4; /* System clock switch control */
3948  } B;
3949  } ME_SAFE_MC_32B_tag;
3950 
3951  typedef union { /* ME_DRUN_MC - DRUN Mode Configuration Register */
3952  vuint32_t R;
3953  struct {
3954  vuint32_t:8;
3955  vuint32_t PDO:1; /* IOs output power-down control */
3956  vuint32_t:2;
3957  vuint32_t MVRON:1; /* Main voltage regulator control */
3958  vuint32_t:2;
3959 #ifndef USE_FIELD_ALIASES_ME
3960  vuint32_t FLAON:2; /* Code flash power-down control */
3961 #else
3962  vuint32_t CFLAON:2; /* deprecated name - please avoid */
3963 #endif
3964  vuint32_t:8;
3965 #ifndef USE_FIELD_ALIASES_ME
3966  vuint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
3967 #else
3968  vuint32_t PLL2ON:1; /* deprecated name - please avoid */
3969 #endif
3970 #ifndef USE_FIELD_ALIASES_ME
3971  vuint32_t PLL0ON:1; /* System PLL control */
3972 #else
3973  vuint32_t PLL1ON:1; /* deprecated name - please avoid */
3974 #endif
3975 #ifndef USE_FIELD_ALIASES_ME
3976  vuint32_t XOSCON:1; /* System crystal oscillator control */
3977 #else
3978  vuint32_t XOSC0ON:1; /* deprecated name - please avoid */
3979 #endif
3980 #ifndef USE_FIELD_ALIASES_ME
3981  vuint32_t IRCOSCON:1; /* System RC oscillator control */
3982 #else
3983  vuint32_t IRCON:1; /* deprecated name - please avoid */
3984 #endif
3985  vuint32_t SYSCLK:4; /* System clock switch control */
3986  } B;
3987  } ME_DRUN_MC_32B_tag;
3988 
3989 
3990  /* Register layout for all registers RUN_MC... */
3991 
3992  typedef union { /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */
3993  vuint32_t R;
3994  struct {
3995  vuint32_t:8;
3996  vuint32_t PDO:1; /* IOs output power-down control */
3997  vuint32_t:2;
3998  vuint32_t MVRON:1; /* Main voltage regulator control */
3999  vuint32_t:2;
4000  vuint32_t FLAON:2; /* Code flash power-down control */
4001  vuint32_t:8;
4002  vuint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
4003  vuint32_t PLL0ON:1; /* System PLL control */
4004  vuint32_t XOSCON:1; /* System crystal oscillator control */
4005  vuint32_t IRCOSCON:1; /* System RC oscillator control */
4006  vuint32_t SYSCLK:4; /* System clock switch control */
4007  } B;
4008  } ME_RUN_MC_32B_tag;
4009 
4010  typedef union { /* ME_HALT0_MC - HALT0 Mode Configuration Register */
4011  vuint32_t R;
4012  struct {
4013  vuint32_t:8;
4014  vuint32_t PDO:1; /* IOs output power-down control */
4015  vuint32_t:2;
4016  vuint32_t MVRON:1; /* Main voltage regulator control */
4017  vuint32_t:2;
4018 #ifndef USE_FIELD_ALIASES_ME
4019  vuint32_t FLAON:2; /* Code flash power-down control */
4020 #else
4021  vuint32_t CFLAON:2; /* deprecated name - please avoid */
4022 #endif
4023  vuint32_t:8;
4024 #ifndef USE_FIELD_ALIASES_ME
4025  vuint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
4026 #else
4027  vuint32_t PLL2ON:1; /* deprecated name - please avoid */
4028 #endif
4029 #ifndef USE_FIELD_ALIASES_ME
4030  vuint32_t PLL0ON:1; /* System PLL control */
4031 #else
4032  vuint32_t PLL1ON:1; /* deprecated name - please avoid */
4033 #endif
4034 #ifndef USE_FIELD_ALIASES_ME
4035  vuint32_t XOSCON:1; /* System crystal oscillator control */
4036 #else
4037  vuint32_t XOSC0ON:1; /* deprecated name - please avoid */
4038 #endif
4039 #ifndef USE_FIELD_ALIASES_ME
4040  vuint32_t IRCOSCON:1; /* System RC oscillator control */
4041 #else
4042  vuint32_t IRCON:1; /* deprecated name - please avoid */
4043 #endif
4044  vuint32_t SYSCLK:4; /* System clock switch control */
4045  } B;
4046  } ME_HALT0_MC_32B_tag;
4047 
4048  typedef union { /* ME_STOP0_MC - STOP0 Mode Configration Register */
4049  vuint32_t R;
4050  struct {
4051  vuint32_t:8;
4052  vuint32_t PDO:1; /* IOs output power-down control */
4053  vuint32_t:2;
4054  vuint32_t MVRON:1; /* Main voltage regulator control */
4055  vuint32_t:2;
4056 #ifndef USE_FIELD_ALIASES_ME
4057  vuint32_t FLAON:2; /* Code flash power-down control */
4058 #else
4059  vuint32_t CFLAON:2; /* deprecated name - please avoid */
4060 #endif
4061  vuint32_t:8;
4062 #ifndef USE_FIELD_ALIASES_ME
4063  vuint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
4064 #else
4065  vuint32_t PLL2ON:1; /* deprecated name - please avoid */
4066 #endif
4067 #ifndef USE_FIELD_ALIASES_ME
4068  vuint32_t PLL0ON:1; /* System PLL control */
4069 #else
4070  vuint32_t PLL1ON:1; /* deprecated name - please avoid */
4071 #endif
4072 #ifndef USE_FIELD_ALIASES_ME
4073  vuint32_t XOSCON:1; /* System crystal oscillator control */
4074 #else
4075  vuint32_t XOSC0ON:1; /* deprecated name - please avoid */
4076 #endif
4077 #ifndef USE_FIELD_ALIASES_ME
4078  vuint32_t IRCOSCON:1; /* System RC oscillator control */
4079 #else
4080  vuint32_t IRCON:1; /* deprecated name - please avoid */
4081 #endif
4082  vuint32_t SYSCLK:4; /* System clock switch control */
4083  } B;
4084  } ME_STOP0_MC_32B_tag;
4085 
4086  typedef union { /* ME_STANDBY0_MC - STANDBY0 Mode Configration Register */
4087  vuint32_t R;
4088  struct {
4089  vuint32_t:8;
4090  vuint32_t PDO:1; /* IOs output power-down control */
4091  vuint32_t:2;
4092  vuint32_t MVRON:1; /* Main voltage regulator control */
4093  vuint32_t:2;
4094 #ifndef USE_FIELD_ALIASES_ME
4095  vuint32_t FLAON:2; /* Code flash power-down control */
4096 #else
4097  vuint32_t CFLAON:2; /* deprecated name - please avoid */
4098 #endif
4099  vuint32_t:8;
4100 #ifndef USE_FIELD_ALIASES_ME
4101  vuint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
4102 #else
4103  vuint32_t PLL2ON:1; /* deprecated name - please avoid */
4104 #endif
4105 #ifndef USE_FIELD_ALIASES_ME
4106  vuint32_t PLL0ON:1; /* System PLL control */
4107 #else
4108  vuint32_t PLL1ON:1; /* deprecated name - please avoid */
4109 #endif
4110 #ifndef USE_FIELD_ALIASES_ME
4111  vuint32_t XOSCON:1; /* System crystal oscillator control */
4112 #else
4113  vuint32_t XOSC0ON:1; /* deprecated name - please avoid */
4114 #endif
4115 #ifndef USE_FIELD_ALIASES_ME
4116  vuint32_t IRCOSCON:1; /* System RC oscillator control */
4117 #else
4118  vuint32_t IRCON:1; /* deprecated name - please avoid */
4119 #endif
4120  vuint32_t SYSCLK:4; /* System clock switch control */
4121  } B;
4122  } ME_STANDBY0_MC_32B_tag;
4123 
4124  typedef union { /* ME_PS0 - Peripheral Status Register 0 */
4125  vuint32_t R;
4126  struct {
4127  vuint32_t:7;
4128  vuint32_t S_FLEXRAY:1; /* FlexRay status */
4129  vuint32_t:6;
4130  vuint32_t S_FLEXCAN1:1; /* FlexCAN1 status */
4131  vuint32_t S_FLEXCAN0:1; /* FlexCAN0 status */
4132  vuint32_t:9;
4133  vuint32_t S_DSPI2:1; /* DSPI2 status */
4134  vuint32_t S_DSPI1:1; /* DSPI1 status */
4135  vuint32_t S_DSPI0:1; /* DSPI0 status */
4136  vuint32_t:4;
4137  } B;
4138  } ME_PS0_32B_tag;
4139 
4140  typedef union { /* ME_PS1 - Peripheral Status Register 1 */
4141  vuint32_t R;
4142  struct {
4143  vuint32_t:1;
4144  vuint32_t S_SWG:1; /* SWG status */
4145  vuint32_t:3;
4146  vuint32_t S_CRC:1; /* CRC status */
4147  vuint32_t:8;
4148  vuint32_t S_LIN_FLEX1:1; /* LinFlex1 status */
4149  vuint32_t S_LIN_FLEX0:1; /* LinFlex0 status */
4150  vuint32_t:5;
4151  vuint32_t S_FLEXPWM1:1; /* FlexPWM1 status */
4152  vuint32_t S_FLEXPWM0:1; /* FlexPWM0 status */
4153  vuint32_t S_ETIMER2:1; /* eTimer2 status */
4154  vuint32_t S_ETIMER1:1; /* eTimer1 status */
4155  vuint32_t S_ETIMER0:1; /* eTimer0 status */
4156  vuint32_t:2;
4157  vuint32_t S_CTU:1; /* CTU status */
4158  vuint32_t:1;
4159  vuint32_t S_ADC1:1; /* ADC1 status */
4160  vuint32_t S_ADC0:1; /* ADC0 status */
4161  } B;
4162  } ME_PS1_32B_tag;
4163 
4164  typedef union { /* ME_PS2 - Peripheral Status Register 2 */
4165  vuint32_t R;
4166  struct {
4167  vuint32_t:3;
4168  vuint32_t S_PIT:1; /* PIT status */
4169  vuint32_t:28;
4170  } B;
4171  } ME_PS2_32B_tag;
4172 
4173 
4174  /* Register layout for all registers RUN_PC... */
4175 
4176  typedef union { /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */
4177  vuint32_t R;
4178  struct {
4179  vuint32_t:24;
4180  vuint32_t RUN3:1; /* Peripheral control during RUN3 */
4181  vuint32_t RUN2:1; /* Peripheral control during RUN2 */
4182  vuint32_t RUN1:1; /* Peripheral control during RUN1 */
4183  vuint32_t RUN0:1; /* Peripheral control during RUN0 */
4184  vuint32_t DRUN:1; /* Peripheral control during DRUN */
4185  vuint32_t SAFE:1; /* Peripheral control during SAFE */
4186  vuint32_t TEST:1; /* Peripheral control during TEST */
4187  vuint32_t RESET:1; /* Peripheral control during RESET */
4188  } B;
4189  } ME_RUN_PC_32B_tag;
4190 
4191 
4192  /* Register layout for all registers LP_PC... */
4193 
4194  typedef union { /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */
4195  vuint32_t R;
4196  struct {
4197  vuint32_t:21;
4198  vuint32_t STOP0:1; /* Peripheral control during STOP0 */
4199  vuint32_t:1;
4200  vuint32_t HALT0:1; /* Peripheral control during HALT0 */
4201  vuint32_t:8;
4202  } B;
4203  } ME_LP_PC_32B_tag;
4204 
4205 
4206  /* Register layout for all registers PCTL... */
4207 
4208  typedef union { /* ME_PCTL[0...143] - Peripheral Control Registers */
4209  vuint8_t R;
4210  struct {
4211  vuint8_t:1;
4212  vuint8_t DBG_F:1; /* Peripheral control in debug mode */
4213  vuint8_t LP_CFG:3; /* Peripheral configuration select for non-RUN modes */
4214  vuint8_t RUN_CFG:3; /* Peripheral configuration select for RUN modes */
4215  } B;
4216  } ME_PCTL_8B_tag;
4217 
4218 
4219 
4220 
4221  /* Register layout for generated register(s) PS... */
4222 
4223  typedef union { /* */
4224  vuint32_t R;
4225  } ME_PS_32B_tag;
4226 
4227 
4228 
4229 
4230 
4231 
4232  typedef struct ME_struct_tag { /* start of ME_tag */
4233  /* ME_GS - Global Status Register */
4234  ME_GS_32B_tag GS; /* offset: 0x0000 size: 32 bit */
4235  /* ME_MCTL - Mode Control Register */
4236  ME_MCTL_32B_tag MCTL; /* offset: 0x0004 size: 32 bit */
4237  union {
4238  ME_MEN_32B_tag MER; /* deprecated - please avoid */
4239 
4240  /* ME_MEN - Mode Enable Register */
4241  ME_MEN_32B_tag MEN; /* offset: 0x0008 size: 32 bit */
4242 
4243  };
4244  /* ME_IS - Interrupt Status Register */
4245  ME_IS_32B_tag IS; /* offset: 0x000C size: 32 bit */
4246  /* ME_IM - Interrupt Mask Register */
4247  ME_IM_32B_tag IM; /* offset: 0x0010 size: 32 bit */
4248  /* ME_IMTS - Invalid Mode Transition Status Register */
4249  ME_IMTS_32B_tag IMTS; /* offset: 0x0014 size: 32 bit */
4250  /* ME_DMTS - Debug Mode Transition Status Register */
4251  ME_DMTS_32B_tag DMTS; /* offset: 0x0018 size: 32 bit */
4252  int8_t ME_reserved_001C_C[4];
4253  union {
4254  /* ME_RESET_MC - RESET Mode Configuration Register */
4255  ME_RESET_MC_32B_tag RESET_MC; /* offset: 0x0020 size: 32 bit */
4256 
4257  ME_RESET_MC_32B_tag RESET; /* deprecated - please avoid */
4258 
4259  };
4260  int8_t ME_reserved_0024_C[4];
4261  union {
4262  /* ME_SAFE_MC - Mode Configuration Register */
4263  ME_SAFE_MC_32B_tag SAFE_MC; /* offset: 0x0028 size: 32 bit */
4264 
4265  ME_SAFE_MC_32B_tag SAFE; /* deprecated - please avoid */
4266 
4267  };
4268  union {
4269  /* ME_DRUN_MC - DRUN Mode Configuration Register */
4270  ME_DRUN_MC_32B_tag DRUN_MC; /* offset: 0x002C size: 32 bit */
4271 
4272  ME_DRUN_MC_32B_tag DRUN; /* deprecated - please avoid */
4273 
4274  };
4275  union {
4276  /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */
4277  ME_RUN_MC_32B_tag RUN_MC[4]; /* offset: 0x0030 (0x0004 x 4) */
4278 
4279  ME_RUN_MC_32B_tag RUN[4]; /* offset: 0x0030 (0x0004 x 4) */ /* deprecated - please avoid */
4280 
4281  struct {
4282  /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */
4283  ME_RUN_MC_32B_tag RUN0_MC; /* offset: 0x0030 size: 32 bit */
4284  ME_RUN_MC_32B_tag RUN1_MC; /* offset: 0x0034 size: 32 bit */
4285  ME_RUN_MC_32B_tag RUN2_MC; /* offset: 0x0038 size: 32 bit */
4286  ME_RUN_MC_32B_tag RUN3_MC; /* offset: 0x003C size: 32 bit */
4287  };
4288 
4289  };
4290  union {
4291  /* ME_HALT0_MC - HALT0 Mode Configuration Register */
4292  ME_HALT0_MC_32B_tag HALT0_MC; /* offset: 0x0040 size: 32 bit */
4293 
4294  ME_HALT0_MC_32B_tag HALT0; /* deprecated - please avoid */
4295 
4296  };
4297  int8_t ME_reserved_0044_C[4];
4298  union {
4299  /* ME_STOP0_MC - STOP0 Mode Configration Register */
4300  ME_STOP0_MC_32B_tag STOP0_MC; /* offset: 0x0048 size: 32 bit */
4301 
4302  ME_STOP0_MC_32B_tag STOP0; /* deprecated - please avoid */
4303 
4304  };
4305  int8_t ME_reserved_004C_C[8];
4306  union {
4307  /* ME_STANDBY0_MC - STANDBY0 Mode Configration Register */
4308  ME_STANDBY0_MC_32B_tag STANDBY0_MC; /* offset: 0x0054 size: 32 bit */
4309 
4310  ME_STANDBY0_MC_32B_tag STANDBY0; /* deprecated - please avoid */
4311 
4312  };
4313  int8_t ME_reserved_0058_C[8];
4314  union {
4315  ME_PS_32B_tag PS[3]; /* offset: 0x0060 (0x0004 x 3) */
4316 
4317  struct {
4318  /* ME_PS0 - Peripheral Status Register 0 */
4319  ME_PS0_32B_tag PS0; /* offset: 0x0060 size: 32 bit */
4320  /* ME_PS1 - Peripheral Status Register 1 */
4321  ME_PS1_32B_tag PS1; /* offset: 0x0064 size: 32 bit */
4322  /* ME_PS2 - Peripheral Status Register 2 */
4323  ME_PS2_32B_tag PS2; /* offset: 0x0068 size: 32 bit */
4324  };
4325 
4326  };
4327  int8_t ME_reserved_006C_C[20];
4328  union {
4329  ME_RUN_PC_32B_tag RUNPC[8]; /* offset: 0x0080 (0x0004 x 8) */
4330 
4331  /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */
4332  ME_RUN_PC_32B_tag RUN_PC[8]; /* offset: 0x0080 (0x0004 x 8) */
4333 
4334  struct {
4335  /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */
4336  ME_RUN_PC_32B_tag RUN_PC0; /* offset: 0x0080 size: 32 bit */
4337  ME_RUN_PC_32B_tag RUN_PC1; /* offset: 0x0084 size: 32 bit */
4338  ME_RUN_PC_32B_tag RUN_PC2; /* offset: 0x0088 size: 32 bit */
4339  ME_RUN_PC_32B_tag RUN_PC3; /* offset: 0x008C size: 32 bit */
4340  ME_RUN_PC_32B_tag RUN_PC4; /* offset: 0x0090 size: 32 bit */
4341  ME_RUN_PC_32B_tag RUN_PC5; /* offset: 0x0094 size: 32 bit */
4342  ME_RUN_PC_32B_tag RUN_PC6; /* offset: 0x0098 size: 32 bit */
4343  ME_RUN_PC_32B_tag RUN_PC7; /* offset: 0x009C size: 32 bit */
4344  };
4345 
4346  };
4347  union {
4348  ME_LP_PC_32B_tag LPPC[8]; /* offset: 0x00A0 (0x0004 x 8) */
4349 
4350  /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */
4351  ME_LP_PC_32B_tag LP_PC[8]; /* offset: 0x00A0 (0x0004 x 8) */
4352 
4353  struct {
4354  /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */
4355  ME_LP_PC_32B_tag LP_PC0; /* offset: 0x00A0 size: 32 bit */
4356  ME_LP_PC_32B_tag LP_PC1; /* offset: 0x00A4 size: 32 bit */
4357  ME_LP_PC_32B_tag LP_PC2; /* offset: 0x00A8 size: 32 bit */
4358  ME_LP_PC_32B_tag LP_PC3; /* offset: 0x00AC size: 32 bit */
4359  ME_LP_PC_32B_tag LP_PC4; /* offset: 0x00B0 size: 32 bit */
4360  ME_LP_PC_32B_tag LP_PC5; /* offset: 0x00B4 size: 32 bit */
4361  ME_LP_PC_32B_tag LP_PC6; /* offset: 0x00B8 size: 32 bit */
4362  ME_LP_PC_32B_tag LP_PC7; /* offset: 0x00BC size: 32 bit */
4363  };
4364 
4365  };
4366  union {
4367  /* ME_PCTL[0...143] - Peripheral Control Registers */
4368  ME_PCTL_8B_tag PCTL[144]; /* offset: 0x00C0 (0x0001 x 144) */
4369 
4370  struct {
4371  /* ME_PCTL[0...143] - Peripheral Control Registers */
4372  ME_PCTL_8B_tag PCTL0; /* offset: 0x00C0 size: 8 bit */
4373  ME_PCTL_8B_tag PCTL1; /* offset: 0x00C1 size: 8 bit */
4374  ME_PCTL_8B_tag PCTL2; /* offset: 0x00C2 size: 8 bit */
4375  ME_PCTL_8B_tag PCTL3; /* offset: 0x00C3 size: 8 bit */
4376  ME_PCTL_8B_tag PCTL4; /* offset: 0x00C4 size: 8 bit */
4377  ME_PCTL_8B_tag PCTL5; /* offset: 0x00C5 size: 8 bit */
4378  ME_PCTL_8B_tag PCTL6; /* offset: 0x00C6 size: 8 bit */
4379  ME_PCTL_8B_tag PCTL7; /* offset: 0x00C7 size: 8 bit */
4380  ME_PCTL_8B_tag PCTL8; /* offset: 0x00C8 size: 8 bit */
4381  ME_PCTL_8B_tag PCTL9; /* offset: 0x00C9 size: 8 bit */
4382  ME_PCTL_8B_tag PCTL10; /* offset: 0x00CA size: 8 bit */
4383  ME_PCTL_8B_tag PCTL11; /* offset: 0x00CB size: 8 bit */
4384  ME_PCTL_8B_tag PCTL12; /* offset: 0x00CC size: 8 bit */
4385  ME_PCTL_8B_tag PCTL13; /* offset: 0x00CD size: 8 bit */
4386  ME_PCTL_8B_tag PCTL14; /* offset: 0x00CE size: 8 bit */
4387  ME_PCTL_8B_tag PCTL15; /* offset: 0x00CF size: 8 bit */
4388  ME_PCTL_8B_tag PCTL16; /* offset: 0x00D0 size: 8 bit */
4389  ME_PCTL_8B_tag PCTL17; /* offset: 0x00D1 size: 8 bit */
4390  ME_PCTL_8B_tag PCTL18; /* offset: 0x00D2 size: 8 bit */
4391  ME_PCTL_8B_tag PCTL19; /* offset: 0x00D3 size: 8 bit */
4392  ME_PCTL_8B_tag PCTL20; /* offset: 0x00D4 size: 8 bit */
4393  ME_PCTL_8B_tag PCTL21; /* offset: 0x00D5 size: 8 bit */
4394  ME_PCTL_8B_tag PCTL22; /* offset: 0x00D6 size: 8 bit */
4395  ME_PCTL_8B_tag PCTL23; /* offset: 0x00D7 size: 8 bit */
4396  ME_PCTL_8B_tag PCTL24; /* offset: 0x00D8 size: 8 bit */
4397  ME_PCTL_8B_tag PCTL25; /* offset: 0x00D9 size: 8 bit */
4398  ME_PCTL_8B_tag PCTL26; /* offset: 0x00DA size: 8 bit */
4399  ME_PCTL_8B_tag PCTL27; /* offset: 0x00DB size: 8 bit */
4400  ME_PCTL_8B_tag PCTL28; /* offset: 0x00DC size: 8 bit */
4401  ME_PCTL_8B_tag PCTL29; /* offset: 0x00DD size: 8 bit */
4402  ME_PCTL_8B_tag PCTL30; /* offset: 0x00DE size: 8 bit */
4403  ME_PCTL_8B_tag PCTL31; /* offset: 0x00DF size: 8 bit */
4404  ME_PCTL_8B_tag PCTL32; /* offset: 0x00E0 size: 8 bit */
4405  ME_PCTL_8B_tag PCTL33; /* offset: 0x00E1 size: 8 bit */
4406  ME_PCTL_8B_tag PCTL34; /* offset: 0x00E2 size: 8 bit */
4407  ME_PCTL_8B_tag PCTL35; /* offset: 0x00E3 size: 8 bit */
4408  ME_PCTL_8B_tag PCTL36; /* offset: 0x00E4 size: 8 bit */
4409  ME_PCTL_8B_tag PCTL37; /* offset: 0x00E5 size: 8 bit */
4410  ME_PCTL_8B_tag PCTL38; /* offset: 0x00E6 size: 8 bit */
4411  ME_PCTL_8B_tag PCTL39; /* offset: 0x00E7 size: 8 bit */
4412  ME_PCTL_8B_tag PCTL40; /* offset: 0x00E8 size: 8 bit */
4413  ME_PCTL_8B_tag PCTL41; /* offset: 0x00E9 size: 8 bit */
4414  ME_PCTL_8B_tag PCTL42; /* offset: 0x00EA size: 8 bit */
4415  ME_PCTL_8B_tag PCTL43; /* offset: 0x00EB size: 8 bit */
4416  ME_PCTL_8B_tag PCTL44; /* offset: 0x00EC size: 8 bit */
4417  ME_PCTL_8B_tag PCTL45; /* offset: 0x00ED size: 8 bit */
4418  ME_PCTL_8B_tag PCTL46; /* offset: 0x00EE size: 8 bit */
4419  ME_PCTL_8B_tag PCTL47; /* offset: 0x00EF size: 8 bit */
4420  ME_PCTL_8B_tag PCTL48; /* offset: 0x00F0 size: 8 bit */
4421  ME_PCTL_8B_tag PCTL49; /* offset: 0x00F1 size: 8 bit */
4422  ME_PCTL_8B_tag PCTL50; /* offset: 0x00F2 size: 8 bit */
4423  ME_PCTL_8B_tag PCTL51; /* offset: 0x00F3 size: 8 bit */
4424  ME_PCTL_8B_tag PCTL52; /* offset: 0x00F4 size: 8 bit */
4425  ME_PCTL_8B_tag PCTL53; /* offset: 0x00F5 size: 8 bit */
4426  ME_PCTL_8B_tag PCTL54; /* offset: 0x00F6 size: 8 bit */
4427  ME_PCTL_8B_tag PCTL55; /* offset: 0x00F7 size: 8 bit */
4428  ME_PCTL_8B_tag PCTL56; /* offset: 0x00F8 size: 8 bit */
4429  ME_PCTL_8B_tag PCTL57; /* offset: 0x00F9 size: 8 bit */
4430  ME_PCTL_8B_tag PCTL58; /* offset: 0x00FA size: 8 bit */
4431  ME_PCTL_8B_tag PCTL59; /* offset: 0x00FB size: 8 bit */
4432  ME_PCTL_8B_tag PCTL60; /* offset: 0x00FC size: 8 bit */
4433  ME_PCTL_8B_tag PCTL61; /* offset: 0x00FD size: 8 bit */
4434  ME_PCTL_8B_tag PCTL62; /* offset: 0x00FE size: 8 bit */
4435  ME_PCTL_8B_tag PCTL63; /* offset: 0x00FF size: 8 bit */
4436  ME_PCTL_8B_tag PCTL64; /* offset: 0x0100 size: 8 bit */
4437  ME_PCTL_8B_tag PCTL65; /* offset: 0x0101 size: 8 bit */
4438  ME_PCTL_8B_tag PCTL66; /* offset: 0x0102 size: 8 bit */
4439  ME_PCTL_8B_tag PCTL67; /* offset: 0x0103 size: 8 bit */
4440  ME_PCTL_8B_tag PCTL68; /* offset: 0x0104 size: 8 bit */
4441  ME_PCTL_8B_tag PCTL69; /* offset: 0x0105 size: 8 bit */
4442  ME_PCTL_8B_tag PCTL70; /* offset: 0x0106 size: 8 bit */
4443  ME_PCTL_8B_tag PCTL71; /* offset: 0x0107 size: 8 bit */
4444  ME_PCTL_8B_tag PCTL72; /* offset: 0x0108 size: 8 bit */
4445  ME_PCTL_8B_tag PCTL73; /* offset: 0x0109 size: 8 bit */
4446  ME_PCTL_8B_tag PCTL74; /* offset: 0x010A size: 8 bit */
4447  ME_PCTL_8B_tag PCTL75; /* offset: 0x010B size: 8 bit */
4448  ME_PCTL_8B_tag PCTL76; /* offset: 0x010C size: 8 bit */
4449  ME_PCTL_8B_tag PCTL77; /* offset: 0x010D size: 8 bit */
4450  ME_PCTL_8B_tag PCTL78; /* offset: 0x010E size: 8 bit */
4451  ME_PCTL_8B_tag PCTL79; /* offset: 0x010F size: 8 bit */
4452  ME_PCTL_8B_tag PCTL80; /* offset: 0x0110 size: 8 bit */
4453  ME_PCTL_8B_tag PCTL81; /* offset: 0x0111 size: 8 bit */
4454  ME_PCTL_8B_tag PCTL82; /* offset: 0x0112 size: 8 bit */
4455  ME_PCTL_8B_tag PCTL83; /* offset: 0x0113 size: 8 bit */
4456  ME_PCTL_8B_tag PCTL84; /* offset: 0x0114 size: 8 bit */
4457  ME_PCTL_8B_tag PCTL85; /* offset: 0x0115 size: 8 bit */
4458  ME_PCTL_8B_tag PCTL86; /* offset: 0x0116 size: 8 bit */
4459  ME_PCTL_8B_tag PCTL87; /* offset: 0x0117 size: 8 bit */
4460  ME_PCTL_8B_tag PCTL88; /* offset: 0x0118 size: 8 bit */
4461  ME_PCTL_8B_tag PCTL89; /* offset: 0x0119 size: 8 bit */
4462  ME_PCTL_8B_tag PCTL90; /* offset: 0x011A size: 8 bit */
4463  ME_PCTL_8B_tag PCTL91; /* offset: 0x011B size: 8 bit */
4464  ME_PCTL_8B_tag PCTL92; /* offset: 0x011C size: 8 bit */
4465  ME_PCTL_8B_tag PCTL93; /* offset: 0x011D size: 8 bit */
4466  ME_PCTL_8B_tag PCTL94; /* offset: 0x011E size: 8 bit */
4467  ME_PCTL_8B_tag PCTL95; /* offset: 0x011F size: 8 bit */
4468  ME_PCTL_8B_tag PCTL96; /* offset: 0x0120 size: 8 bit */
4469  ME_PCTL_8B_tag PCTL97; /* offset: 0x0121 size: 8 bit */
4470  ME_PCTL_8B_tag PCTL98; /* offset: 0x0122 size: 8 bit */
4471  ME_PCTL_8B_tag PCTL99; /* offset: 0x0123 size: 8 bit */
4472  ME_PCTL_8B_tag PCTL100; /* offset: 0x0124 size: 8 bit */
4473  ME_PCTL_8B_tag PCTL101; /* offset: 0x0125 size: 8 bit */
4474  ME_PCTL_8B_tag PCTL102; /* offset: 0x0126 size: 8 bit */
4475  ME_PCTL_8B_tag PCTL103; /* offset: 0x0127 size: 8 bit */
4476  ME_PCTL_8B_tag PCTL104; /* offset: 0x0128 size: 8 bit */
4477  ME_PCTL_8B_tag PCTL105; /* offset: 0x0129 size: 8 bit */
4478  ME_PCTL_8B_tag PCTL106; /* offset: 0x012A size: 8 bit */
4479  ME_PCTL_8B_tag PCTL107; /* offset: 0x012B size: 8 bit */
4480  ME_PCTL_8B_tag PCTL108; /* offset: 0x012C size: 8 bit */
4481  ME_PCTL_8B_tag PCTL109; /* offset: 0x012D size: 8 bit */
4482  ME_PCTL_8B_tag PCTL110; /* offset: 0x012E size: 8 bit */
4483  ME_PCTL_8B_tag PCTL111; /* offset: 0x012F size: 8 bit */
4484  ME_PCTL_8B_tag PCTL112; /* offset: 0x0130 size: 8 bit */
4485  ME_PCTL_8B_tag PCTL113; /* offset: 0x0131 size: 8 bit */
4486  ME_PCTL_8B_tag PCTL114; /* offset: 0x0132 size: 8 bit */
4487  ME_PCTL_8B_tag PCTL115; /* offset: 0x0133 size: 8 bit */
4488  ME_PCTL_8B_tag PCTL116; /* offset: 0x0134 size: 8 bit */
4489  ME_PCTL_8B_tag PCTL117; /* offset: 0x0135 size: 8 bit */
4490  ME_PCTL_8B_tag PCTL118; /* offset: 0x0136 size: 8 bit */
4491  ME_PCTL_8B_tag PCTL119; /* offset: 0x0137 size: 8 bit */
4492  ME_PCTL_8B_tag PCTL120; /* offset: 0x0138 size: 8 bit */
4493  ME_PCTL_8B_tag PCTL121; /* offset: 0x0139 size: 8 bit */
4494  ME_PCTL_8B_tag PCTL122; /* offset: 0x013A size: 8 bit */
4495  ME_PCTL_8B_tag PCTL123; /* offset: 0x013B size: 8 bit */
4496  ME_PCTL_8B_tag PCTL124; /* offset: 0x013C size: 8 bit */
4497  ME_PCTL_8B_tag PCTL125; /* offset: 0x013D size: 8 bit */
4498  ME_PCTL_8B_tag PCTL126; /* offset: 0x013E size: 8 bit */
4499  ME_PCTL_8B_tag PCTL127; /* offset: 0x013F size: 8 bit */
4500  ME_PCTL_8B_tag PCTL128; /* offset: 0x0140 size: 8 bit */
4501  ME_PCTL_8B_tag PCTL129; /* offset: 0x0141 size: 8 bit */
4502  ME_PCTL_8B_tag PCTL130; /* offset: 0x0142 size: 8 bit */
4503  ME_PCTL_8B_tag PCTL131; /* offset: 0x0143 size: 8 bit */
4504  ME_PCTL_8B_tag PCTL132; /* offset: 0x0144 size: 8 bit */
4505  ME_PCTL_8B_tag PCTL133; /* offset: 0x0145 size: 8 bit */
4506  ME_PCTL_8B_tag PCTL134; /* offset: 0x0146 size: 8 bit */
4507  ME_PCTL_8B_tag PCTL135; /* offset: 0x0147 size: 8 bit */
4508  ME_PCTL_8B_tag PCTL136; /* offset: 0x0148 size: 8 bit */
4509  ME_PCTL_8B_tag PCTL137; /* offset: 0x0149 size: 8 bit */
4510  ME_PCTL_8B_tag PCTL138; /* offset: 0x014A size: 8 bit */
4511  ME_PCTL_8B_tag PCTL139; /* offset: 0x014B size: 8 bit */
4512  ME_PCTL_8B_tag PCTL140; /* offset: 0x014C size: 8 bit */
4513  ME_PCTL_8B_tag PCTL141; /* offset: 0x014D size: 8 bit */
4514  ME_PCTL_8B_tag PCTL142; /* offset: 0x014E size: 8 bit */
4515  ME_PCTL_8B_tag PCTL143; /* offset: 0x014F size: 8 bit */
4516  };
4517 
4518  };
4519  } ME_tag;
4520 
4521 
4522 #define ME (*(volatile ME_tag *) 0xC3FDC000UL)
4523 
4524 
4525 
4526 /****************************************************************/
4527 /* */
4528 /* Module: OSC */
4529 /* */
4530 /****************************************************************/
4531 
4532  typedef union { /* OSC_CTL - Control Register */
4533  vuint32_t R;
4534  struct {
4535  vuint32_t OSCBYP:1; /* High Frequency Oscillator Bypass */
4536  vuint32_t:7;
4537  vuint32_t EOCV:8; /* End of Count Value */
4538  vuint32_t M_OSC:1; /* High Frequency Oscillator Clock Interrupt Mask */
4539  vuint32_t:2;
4540  vuint32_t OSCDIV:5; /* High Frequency Oscillator Division Factor */
4541  vuint32_t I_OSC:1; /* High Frequency Oscillator Clock Interrupt */
4542  vuint32_t:5;
4543  vuint32_t S_OSC:1;
4544  vuint32_t OSCON:1; } B;
4545  } OSC_CTL_32B_tag;
4546 
4547 
4548 
4549  typedef struct OSC_struct_tag { /* start of OSC_tag */
4550  /* OSC_CTL - Control Register */
4551  OSC_CTL_32B_tag CTL; /* offset: 0x0000 size: 32 bit */
4552  } OSC_tag;
4553 
4554 
4555 #define OSC (*(volatile OSC_tag *) 0xC3FE0000UL)
4556 
4557 
4558 
4559 /****************************************************************/
4560 /* */
4561 /* Module: RC */
4562 /* */
4563 /****************************************************************/
4564 
4565  typedef union { /* RC_CTL - Control Register */
4566  vuint32_t R;
4567  struct {
4568  vuint32_t:10;
4569  vuint32_t RCTRIM:6; /* Main RC Trimming Bits */
4570  vuint32_t:3;
4571  vuint32_t RCDIV:5; /* Main RC Clock Division Factor */
4572  vuint32_t:2;
4573  vuint32_t S_RC_STDBY:1; /* MRC Oscillator Powerdown Status */
4574  vuint32_t:5;
4575  } B;
4576  } RC_CTL_32B_tag;
4577 
4578 
4579 
4580  typedef struct RC_struct_tag { /* start of RC_tag */
4581  /* RC_CTL - Control Register */
4582  RC_CTL_32B_tag CTL; /* offset: 0x0000 size: 32 bit */
4583  } RC_tag;
4584 
4585 
4586 #define RC (*(volatile RC_tag *) 0xC3FE0060UL)
4587 
4588 
4589 
4590 /****************************************************************/
4591 /* */
4592 /* Module: PLLD */
4593 /* */
4594 /****************************************************************/
4595 
4596  typedef union { /* PLLD_CR - Control Register */
4597  vuint32_t R;
4598  struct {
4599  vuint32_t:2;
4600  vuint32_t IDF:4; /* PLL Input Division Factor */
4601  vuint32_t ODF:2; /* PLL Output Division Factor */
4602  vuint32_t:1;
4603  vuint32_t NDIV:7; /* PLL Loop Division Factor */
4604  vuint32_t:7;
4605  vuint32_t EN_PLL_SW:1; /* Enable Progressive Clock Switching */
4606  vuint32_t MODE:1; /* Activate 1:1 Mode */
4607  vuint32_t UNLOCK_ONCE:1; /* PLL Loss of Lock */
4608  vuint32_t M_LOCK:1; /* Mask for the i_lock Output Interrupt */
4609  vuint32_t I_LOCK:1; /* PLL Lock Signal Toggle Indicator */
4610  vuint32_t S_LOCK:1; /* PLL has Aquired Lock */
4611  vuint32_t PLL_FAIL_MASK:1; /* PLL Fail Mask */
4612  vuint32_t PLL_FAIL_FLAG:1; /* PLL Fail Flag */
4613  vuint32_t PLL_ON:1; /* PLL ON Bit */
4614  } B;
4615  } PLLD_CR_32B_tag;
4616 
4617  typedef union { /* PLLD_MR - PLLD Modulation Register */
4618  vuint32_t R;
4619  struct {
4620  vuint32_t STRB_BYPASS:1; /* Strobe Bypass */
4621  vuint32_t:1;
4622  vuint32_t SPRD_SEL:1; /* Spread Type Selection */
4623  vuint32_t MOD_PERIOD:13; /* Modulation Period */
4624  vuint32_t SSCG_EN:1; /* Spread Spectrum Clock Generation Enable */
4625  vuint32_t INC_STEP:15; /* Increment Step */
4626  } B;
4627  } PLLD_MR_32B_tag;
4628 
4629 
4630 
4631  typedef struct PLLD_struct_tag { /* start of PLLD_tag */
4632  /* PLLD_CR - Control Register */
4633  PLLD_CR_32B_tag CR; /* offset: 0x0000 size: 32 bit */
4634  /* PLLD_MR - PLLD Modulation Register */
4635  PLLD_MR_32B_tag MR; /* offset: 0x0004 size: 32 bit */
4636 
4637  vuint32_t plld_reserved[6];
4638  } PLLD_tag;
4639 
4640 
4641 #define PLLD0 (*(volatile PLLD_tag *) 0xC3FE00A0UL)
4642 #define PLLD1 (*(volatile PLLD_tag *) 0xC3FE00C0UL)
4643 
4644 
4645 
4646 /****************************************************************/
4647 /* */
4648 /* Module: CMU */
4649 /* */
4650 /****************************************************************/
4651 
4652  typedef union { /* CMU_CSR - Control Status Register */
4653  vuint32_t R;
4654  struct {
4655  vuint32_t:8;
4656  vuint32_t SFM:1; /* Start Frequency Measure */
4657  vuint32_t:13;
4658  vuint32_t CKSEL1:2; /* RC Oscillator(s) Selection Bit */
4659  vuint32_t:5;
4660  vuint32_t RCDIV:2; /* RCfast Clock Division Factor */
4661  vuint32_t CME_A:1; /* PLL_A Clock Monitor Enable */
4662  } B;
4663  } CMU_CSR_32B_tag;
4664 
4665  typedef union { /* CMU_FDR - Frequency Display Register */
4666  vuint32_t R;
4667  struct {
4668  vuint32_t:12;
4669  vuint32_t FD:20; /* Measured Frequency Bits */
4670  } B;
4671  } CMU_FDR_32B_tag;
4672 
4673  typedef union { /* CMU_HFREFR_A - High Frequency Reference Register */
4674  vuint32_t R;
4675  struct {
4676  vuint32_t:20;
4677  vuint32_t HFREF_A:12; /* High Frequency Reference Value */
4678  } B;
4679  } CMU_HFREFR_A_32B_tag;
4680 
4681  typedef union { /* CMU_LFREFR_A - Low Frequency Reference Register */
4682  vuint32_t R;
4683  struct {
4684  vuint32_t:20;
4685  vuint32_t LFREF_A:12; /* Low Frequency Reference Value */
4686  } B;
4687  } CMU_LFREFR_A_32B_tag;
4688 
4689  typedef union { /* CMU_ISR - Interrupt Status Register */
4690  vuint32_t R;
4691  struct {
4692  vuint32_t:28;
4693  vuint32_t FLCI_A:1; /* PLL_A Clock Frequency less than Reference Clock Interrupt */
4694  vuint32_t FHH_AI:1; /* PLL_A Clock Frequency higher than high Reference Interrupt */
4695  vuint32_t FLLI_A:1; /* PLL_A Clock Frequency less than low Reference Interrupt */
4696  vuint32_t OLRI:1; /* Oscillator Frequency less than RC Frequency Interrupt */
4697  } B;
4698  } CMU_ISR_32B_tag;
4699 
4700  typedef union { /* CMU_IMR - Interrupt Mask Register */
4701  vuint32_t R;
4702  } CMU_IMR_32B_tag;
4703 
4704  typedef union { /* CMU_MDR - Measurement Duration Register */
4705  vuint32_t R;
4706  struct {
4707  vuint32_t:12;
4708  vuint32_t MD:20; /* Measurment Duration Bits */
4709  } B;
4710  } CMU_MDR_32B_tag;
4711 
4712 
4713 
4714  typedef struct CMU_struct_tag { /* start of CMU_tag */
4715  /* CMU_CSR - Control Status Register */
4716  CMU_CSR_32B_tag CSR; /* offset: 0x0000 size: 32 bit */
4717  /* CMU_FDR - Frequency Display Register */
4718  CMU_FDR_32B_tag FDR; /* offset: 0x0004 size: 32 bit */
4719  /* CMU_HFREFR_A - High Frequency Reference Register */
4720  CMU_HFREFR_A_32B_tag HFREFR_A; /* offset: 0x0008 size: 32 bit */
4721  /* CMU_LFREFR_A - Low Frequency Reference Register */
4722  CMU_LFREFR_A_32B_tag LFREFR_A; /* offset: 0x000C size: 32 bit */
4723  /* CMU_ISR - Interrupt Status Register */
4724  CMU_ISR_32B_tag ISR; /* offset: 0x0010 size: 32 bit */
4725  /* CMU_IMR - Interrupt Mask Register */
4726  CMU_IMR_32B_tag IMR; /* offset: 0x0014 size: 32 bit */
4727  /* CMU_MDR - Measurement Duration Register */
4728  CMU_MDR_32B_tag MDR; /* offset: 0x0018 size: 32 bit */
4729  } CMU_tag;
4730 
4731 
4732 #define CMU0 (*(volatile CMU_tag *) 0xC3FE0100UL)
4733 #define CMU1 (*(volatile CMU_tag *) 0xC3FE0120UL)
4734 #define CMU2 (*(volatile CMU_tag *) 0xC3FE0140UL)
4735 
4736 
4737 
4738 /****************************************************************/
4739 /* */
4740 /* Module: CGM */
4741 /* */
4742 /****************************************************************/
4743 
4744  typedef union { /* Output Clock Enable Register */
4745  vuint32_t R;
4746  vuint8_t BYTE[4]; /* individual bytes can be accessed */
4747  vuint16_t HALF[2]; /* individual halfwords can be accessed */
4748  vuint32_t WORD; /* individual words can be accessed */
4749  struct {
4750  vuint32_t:31;
4751  vuint32_t EN:1; /* Clock Enable Bit */
4752  } B;
4753  } CGM_OC_EN_32B_tag;
4754 
4755  typedef union { /* Output Clock Division Select Register */
4756  vuint32_t R;
4757  vuint8_t BYTE[4]; /* individual bytes can be accessed */
4758  vuint16_t HALF[2]; /* individual halfwords can be accessed */
4759  vuint32_t WORD; /* individual words can be accessed */
4760  struct {
4761  vuint32_t:2;
4762  vuint32_t SELDIV:2; /* Output Clock Division Select */
4763  vuint32_t SELCTL:4; /* Output Clock Source Selection Control */
4764  vuint32_t:24;
4765  } B;
4766  } CGM_OCDS_SC_32B_tag;
4767 
4768  typedef union { /* System Clock Select Status Register */
4769  vuint32_t R;
4770  vuint8_t BYTE[4]; /* individual bytes can be accessed */
4771  vuint16_t HALF[2]; /* individual halfwords can be accessed */
4772  vuint32_t WORD; /* individual words can be accessed */
4773  struct {
4774  vuint32_t:4;
4775  vuint32_t SELSTAT:4; /* System Clock Source Selection Status */
4776  vuint32_t:24;
4777  } B;
4778  } CGM_SC_SS_32B_tag;
4779 
4780  typedef union { /* System Clock Divider Configuration Register */
4781  vuint32_t R;
4782  vuint8_t BYTE[4]; /* individual bytes can be accessed */
4783  vuint16_t HALF[2]; /* individual halfwords can be accessed */
4784  vuint32_t WORD; /* individual words can be accessed */
4785  struct {
4786  vuint32_t DE0:1; /* Divider 0 Enable */
4787  vuint32_t:3;
4788  vuint32_t DIV0:4; /* Divider 0 Value */
4789  vuint32_t:24;
4790  } B;
4791  } CGM_SC_DC0_3_32B_tag;
4792 
4793 
4794  /* Register layout for all registers SC_DC... */
4795 
4796  typedef union { /* System Clock Divider Configuration Register */
4797  vuint8_t R;
4798  struct {
4799  vuint8_t DE:1; /* Divider Enable */
4800  vuint8_t:3;
4801  vuint8_t DIV:4; /* Divider Division Value */
4802  } B;
4803  } CGM_SC_DC_8B_tag;
4804 
4805 
4806  /* Register layout for all registers AC_SC... */
4807 
4808  typedef union { /* Auxiliary Clock Select Control Registers */
4809  vuint32_t R;
4810  vuint8_t BYTE[4]; /* individual bytes can be accessed */
4811  vuint16_t HALF[2]; /* individual halfwords can be accessed */
4812  vuint32_t WORD; /* individual words can be accessed */
4813  struct {
4814  vuint32_t:4;
4815  vuint32_t SELCTL:4; /* Auxliary Clock Source Selection Control */
4816  vuint32_t:24;
4817  } B;
4818  } CGM_AC_SC_32B_tag;
4819 
4820 
4821  /* Register layout for all registers AC_DC0_3... */
4822 
4823  typedef union { /* Auxiliary Clock Divider Configuration Registers */
4824  vuint32_t R;
4825  struct {
4826  vuint32_t DE0:1; /* Divider 0 Enable */
4827  vuint32_t:3;
4828  vuint32_t DIV0:4; /* Divider 0 Value */
4829  vuint32_t DE1:1; /* Divider 1 Enable */
4830  vuint32_t:3;
4831  vuint32_t DIV1:4; /* Divider 1 Value */
4832  vuint32_t:16;
4833  } B;
4834  } CGM_AC_DC0_3_32B_tag;
4835 
4836 
4837  typedef struct CGM_AUXCLK_struct_tag {
4838 
4839  /* Auxiliary Clock Select Control Registers */
4840  CGM_AC_SC_32B_tag AC_SC; /* relative offset: 0x0000 */
4841  /* Auxiliary Clock Divider Configuration Registers */
4842  CGM_AC_DC0_3_32B_tag AC_DC0_3; /* relative offset: 0x0004 */
4843 
4844  } CGM_AUXCLK_tag;
4845 
4846 
4847  typedef struct CGM_struct_tag { /* start of CGM_tag */
4848  OSC_CTL_32B_tag OSC_CTL; /* offset: 0x0000 size: 32 bit */
4849  int8_t CGM_reserved_0004[92];
4850  RC_CTL_32B_tag RC_CTL; /* offset: 0x0060 size: 32 bit */
4851  int8_t CGM_reserved_0064[60];
4852  PLLD_tag FMPLL[2]; /* offset: 0x00A0 (0x0020 x 2) */
4853  int8_t CGM_reserved_00E0[32];
4854  CMU_CSR_32B_tag CMU_0_CSR; /* offset: 0x0100 size: 32 bit */
4855  CMU_FDR_32B_tag CMU_0_FDR; /* offset: 0x0104 size: 32 bit */
4856  CMU_HFREFR_A_32B_tag CMU_0_HFREFR_A; /* offset: 0x0108 size: 32 bit */
4857  CMU_LFREFR_A_32B_tag CMU_0_LFREFR_A; /* offset: 0x010C size: 32 bit */
4858  CMU_ISR_32B_tag CMU_0_ISR; /* offset: 0x0110 size: 32 bit */
4859  CMU_IMR_32B_tag CMU_0_IMR; /* offset: 0x0114 size: 32 bit */
4860  CMU_MDR_32B_tag CMU_0_MDR; /* offset: 0x0118 size: 32 bit */
4861  int8_t CGM_reserved_011C[4];
4862  CMU_CSR_32B_tag CMU_1_CSR; /* offset: 0x0120 size: 32 bit */
4863  int8_t CGM_reserved_0124[4];
4864  CMU_HFREFR_A_32B_tag CMU_1_HFREFR_A; /* offset: 0x0128 size: 32 bit */
4865  CMU_LFREFR_A_32B_tag CMU_1_LFREFR_A; /* offset: 0x012C size: 32 bit */
4866  CMU_ISR_32B_tag CMU_1_ISR; /* offset: 0x0130 size: 32 bit */
4867  int8_t CGM_reserved_0134[572];
4868  /* Output Clock Enable Register */
4869  CGM_OC_EN_32B_tag OC_EN; /* offset: 0x0370 size: 32 bit */
4870  /* Output Clock Division Select Register */
4871  CGM_OCDS_SC_32B_tag OCDS_SC; /* offset: 0x0374 size: 32 bit */
4872  /* System Clock Select Status Register */
4873  CGM_SC_SS_32B_tag SC_SS; /* offset: 0x0378 size: 32 bit */
4874  union {
4875  struct {
4876  /* System Clock Divider Configuration Register */
4877  CGM_SC_DC_8B_tag SC_DC[2]; /* offset: 0x037C (0x0001 x 2) */
4878  int8_t CGM_reserved_037E_E0[2];
4879  };
4880 
4881  struct {
4882  /* System Clock Divider Configuration Register */
4883  CGM_SC_DC_8B_tag SC_DC0; /* offset: 0x037C size: 8 bit */
4884  CGM_SC_DC_8B_tag SC_DC1; /* offset: 0x037D size: 8 bit */
4885  int8_t CGM_reserved_037E_E1[2];
4886  };
4887 
4888  /* System Clock Divider Configuration Register */
4889  CGM_SC_DC0_3_32B_tag SC_DC0_3; /* offset: 0x037C size: 32 bit */
4890 
4891  };
4892  union {
4893  /* Register set AUXCLK */
4894  CGM_AUXCLK_tag AUXCLK[6]; /* offset: 0x0380 (0x0008 x 6) */
4895 
4896  struct {
4897  /* Auxiliary Clock Select Control Registers */
4898  CGM_AC_SC_32B_tag AC0_SC; /* offset: 0x0380 size: 32 bit */
4899  /* Auxiliary Clock Divider Configuration Registers */
4900  CGM_AC_DC0_3_32B_tag AC0_DC0_3; /* offset: 0x0384 size: 32 bit */
4901  /* Auxiliary Clock Select Control Registers */
4902  CGM_AC_SC_32B_tag AC1_SC; /* offset: 0x0388 size: 32 bit */
4903  /* Auxiliary Clock Divider Configuration Registers */
4904  CGM_AC_DC0_3_32B_tag AC1_DC0_3; /* offset: 0x038C size: 32 bit */
4905  /* Auxiliary Clock Select Control Registers */
4906  CGM_AC_SC_32B_tag AC2_SC; /* offset: 0x0390 size: 32 bit */
4907  /* Auxiliary Clock Divider Configuration Registers */
4908  CGM_AC_DC0_3_32B_tag AC2_DC0_3; /* offset: 0x0394 size: 32 bit */
4909  /* Auxiliary Clock Select Control Registers */
4910  CGM_AC_SC_32B_tag AC3_SC; /* offset: 0x0398 size: 32 bit */
4911  /* Auxiliary Clock Divider Configuration Registers */
4912  CGM_AC_DC0_3_32B_tag AC3_DC0_3; /* offset: 0x039C size: 32 bit */
4913  /* Auxiliary Clock Select Control Registers */
4914  CGM_AC_SC_32B_tag AC4_SC; /* offset: 0x03A0 size: 32 bit */
4915  /* Auxiliary Clock Divider Configuration Registers */
4916  CGM_AC_DC0_3_32B_tag AC4_DC0_3; /* offset: 0x03A4 size: 32 bit */
4917  /* Auxiliary Clock Select Control Registers */
4918  CGM_AC_SC_32B_tag AC5_SC; /* offset: 0x03A8 size: 32 bit */
4919  /* Auxiliary Clock Divider Configuration Registers */
4920  CGM_AC_DC0_3_32B_tag AC5_DC0_3; /* offset: 0x03AC size: 32 bit */
4921  };
4922 
4923  };
4924  } CGM_tag;
4925 
4926 
4927 #define CGM (*(volatile CGM_tag *) 0xC3FE0000UL)
4928 
4929 
4930 
4931 /****************************************************************/
4932 /* */
4933 /* Module: RGM */
4934 /* */
4935 /****************************************************************/
4936 
4937  typedef union { /* Functional Event Status Register */
4938  vuint16_t R;
4939  struct {
4940  vuint16_t F_EXR:1; /* Flag for External Reset */
4941  vuint16_t F_FCCU_HARD:1; /* Flag for FCCU hard reaction request */
4942  vuint16_t F_FCCU_SOFT:1; /* Flag for FCCU soft reaction request */
4943  vuint16_t F_ST_DONE:1; /* Flag for self-test completed */
4944 #ifndef USE_FIELD_ALIASES_RGM
4945  vuint16_t F_CMU12_FHL:1; /* Flag for CMU 1/2 clock freq. too high/low */
4946 #else
4947  vuint16_t F_CMU1_FHL:1; /* deprecated name - please avoid */
4948 #endif
4949  vuint16_t F_FL_ECC_RCC:1; /* Flag for Flash, ECC, or lock-step error */
4950  vuint16_t F_PLL1:1; /* Flag for PLL1 fail */
4951  vuint16_t F_SWT:1; /* Flag for Software Watchdog Timer */
4952  vuint16_t F_FCCU_SAFE:1; /* Flag for FCCU SAFE mode request */
4953  vuint16_t F_CMU0_FHL:1; /* Flag for CMU 0 clock freq. too high/low */
4954  vuint16_t F_CMU0_OLR:1; /* Flag for oscillator freq. too low */
4955  vuint16_t F_PLL0:1; /* Flag for PLL0 fail */
4956  vuint16_t F_CWD:1; /* Flag for Core Watchdog Reset */
4957  vuint16_t F_SOFT:1; /* Flag for software reset */
4958  vuint16_t F_CORE:1; /* Flag for core reset */
4959  vuint16_t F_JTAG:1; /* Flag for JTAG initiated reset */
4960  } B;
4961  } RGM_FES_16B_tag;
4962 
4963  typedef union { /* Destructive Event Status Register */
4964  vuint16_t R;
4965  struct {
4966 #ifndef USE_FIELD_ALIASES_RGM
4967  vuint16_t F_POR:1; /* Flag for Power on Reset */
4968 #else
4969  vuint16_t POR:1; /* deprecated name - please avoid */
4970 #endif
4971  vuint16_t:7;
4972  vuint16_t F_COMP:1; /* Flag for comparator error */
4973  vuint16_t F_LVD27_IO:1; /* Flag for 2.7V low-voltage detected (I/O) */
4974  vuint16_t F_LVD27_FLASH:1; /* Flag for 2.7V low-voltage detected (Flash) */
4975  vuint16_t F_LVD27_VREG:1; /* Flag for 2.7V low-voltage detected (VREG) */
4976  vuint16_t:2;
4977  vuint16_t F_HVD12:1; /* Flag for 1.2V high-voltage detected */
4978 #ifndef USE_FIELD_ALIASES_RGM
4979  vuint16_t F_LVD12:1; /* Flag for 1.2V low-voltage detected */
4980 #else
4981  vuint16_t F_LVD12_PD0:1; /* deprecated name - please avoid */
4982 #endif
4983  } B;
4984  } RGM_DES_16B_tag;
4985 
4986  typedef union { /* Functional Event Reset Disable Register */
4987  vuint16_t R;
4988  struct {
4989  vuint16_t D_EXR:1; /* Disable External Pad Event Reset */
4990  vuint16_t D_FCCU_HARD:1; /* Disable FCCU hard reaction request */
4991  vuint16_t D_FCCU_SOFT:1; /* Disable FCCU soft reaction request */
4992  vuint16_t D_ST_DONE:1; /* Disable self-test completed */
4993 #ifndef USE_FIELD_ALIASES_RGM
4994  vuint16_t D_CMU12_FHL:1; /* Disable CMU 1/2 clock freq. too high/low */
4995 #else
4996  vuint16_t D_CMU1_FHL:1; /* deprecated name - please avoid */
4997 #endif
4998  vuint16_t D_FL_ECC_RCC:1; /* Disable Flash, ECC, or lock-step error */
4999  vuint16_t D_PLL1:1; /* Disable PLL1 fail */
5000  vuint16_t D_SWT:1; /* Disable Software Watchdog Timer */
5001  vuint16_t D_FCCU_SAFE:1; /* Disable FCCU SAFE mode request */
5002  vuint16_t D_CMU0_FHL:1; /* Disable CMU 0 clock freq. too high/low */
5003  vuint16_t D_CMU0_OLR:1; /* Disable oscillator freq. too low */
5004  vuint16_t D_PLL0:1; /* Disable PLL0 fail */
5005  vuint16_t D_CWD:1; /* Disable Core Watchdog Reset */
5006  vuint16_t D_SOFT:1; /* Disable software reset */
5007  vuint16_t D_CORE:1; /* Disable core reset */
5008  vuint16_t D_JTAG:1; /* Disable JTAG initiated reset */
5009  } B;
5010  } RGM_FERD_16B_tag;
5011 
5012  typedef union { /* Destructive Event Reset Disable Register */
5013  vuint16_t R;
5014  struct {
5015  vuint16_t:8;
5016  vuint16_t D_COMP:1; /* Disable comparator error */
5017  vuint16_t D_LVD27_IO:1; /* Disable 2.7V low-voltage detected (I/O) */
5018  vuint16_t D_LVD27_FLASH:1; /* Disable 2.7V low-voltage detected (Flash) */
5019  vuint16_t D_LVD27_VREG:1; /* Disable 2.7V low-voltage detected (VREG) */
5020  vuint16_t:2;
5021  vuint16_t D_HVD12:1; /* Disable 1.2V high-voltage detected */
5022 #ifndef USE_FIELD_ALIASES_RGM
5023  vuint16_t D_LVD12:1; /* Disable 1.2V low-voltage detected */
5024 #else
5025  vuint16_t D_LVD12_PD0:1; /* deprecated name - please avoid */
5026 #endif
5027  } B;
5028  } RGM_DERD_16B_tag;
5029 
5030  typedef union { /* Functional Event Alternate Request Register */
5031  vuint16_t R;
5032  struct {
5033  vuint16_t:4;
5034 #ifndef USE_FIELD_ALIASES_RGM
5035  vuint16_t AR_CMU12_FHL:1; /* Alternate Request for CMU1/2 clock freq. too high/low */
5036 #else
5037  vuint16_t AR_CMU1_FHL:1; /* deprecated name - please avoid */
5038 #endif
5039  vuint16_t:1;
5040  vuint16_t AR_PLL1:1; /* Alternate Request for PLL1 fail */
5041  vuint16_t:1;
5042  vuint16_t AR_FCCU_SAVE:1; /* Alternate Request for FCCU SAFE mode request */
5043  vuint16_t AR_CMU0_FHL:1; /* Alternate Request for CMU0 clock freq.
5044  too high/low */
5045  vuint16_t AR_CMU0_OLR:1; /* Alternate Request for oscillator freq. too low */
5046  vuint16_t AR_PLL0:1; /* Alternate Request for PLL0 fail */
5047  vuint16_t AR_CWD:1; /* Alternate Request for core watchdog reset */
5048  vuint16_t:3;
5049  } B;
5050  } RGM_FEAR_16B_tag;
5051 
5052  typedef union { /* Functional Event Short Sequence Register */
5053  vuint16_t R;
5054  struct {
5055  vuint16_t SS_EXR:1; /* Short Sequence for External Reset */
5056  vuint16_t SS_FCCU_HARD:1; /* Short Sequence for FCCU hard reaction request */
5057  vuint16_t SS_FCCU_SOFT:1; /* Short Sequence for FCCU soft reaction request */
5058  vuint16_t SS_ST_DONE:1; /* Short Sequence for self-test completed */
5059 #ifndef USE_FIELD_ALIASES_RGM
5060  vuint16_t SS_CMU12_FHL:1; /* Short Sequence for CMU 1/2 clock freq. too high/low */
5061 #else
5062  vuint16_t SS_CMU1_FHL:1; /* deprecated name - please avoid */
5063 #endif
5064  vuint16_t SS_FL_ECC_RCC:1; /* Short Sequence for Flash, ECC, or lock-step error */
5065  vuint16_t SS_PLL1:1; /* Short Sequence for PLL1 fail */
5066  vuint16_t SS_SWT:1; /* Short Sequence for Software Watchdog Timer */
5067  vuint16_t:1;
5068  vuint16_t SS_CMU0_FHL:1; /* Short Sequence for CMU 0 clock freq. too high/low */
5069  vuint16_t SS_CMU0_OLR:1; /* Short Sequence for oscillator freq. too low */
5070  vuint16_t SS_PLL0:1; /* Short Sequence for PLL0 fail */
5071  vuint16_t SS_CWD:1; /* Short Sequence for Core Watchdog Reset */
5072  vuint16_t SS_SOFT:1; /* Short Sequence for software reset */
5073  vuint16_t SS_CORE:1; /* Short Sequence for core reset */
5074  vuint16_t SS_JTAG:1; /* Short Sequence for JTAG initiated reset */
5075  } B;
5076  } RGM_FESS_16B_tag;
5077 
5078  typedef union { /* Functional Bidirectional Reset Enable Register */
5079  vuint16_t R;
5080  struct {
5081  vuint16_t BE_EXR:1; /* Bidirectional Reset Enable for External Reset */
5082  vuint16_t BE_FCCU_HARD:1; /* Bidirectional Reset Enable for FCCU hard reaction request */
5083  vuint16_t BE_FCCU_SOFT:1; /* Bidirectional Reset Enable for FCCU soft reaction request */
5084  vuint16_t BE_ST_DONE:1; /* Bidirectional Reset Enable for self-test completed */
5085 #ifndef USE_FIELD_ALIASES_RGM
5086  vuint16_t BE_CMU12_FHL:1; /* Bidirectional Reset Enable for CMU 1/2 clock freq. too high/low */
5087 #else
5088  vuint16_t BE_CMU1_FHL:1; /* deprecated name - please avoid */
5089 #endif
5090  vuint16_t BE_FL_ECC_RCC:1; /* Bidirectional Reset Enable for Flash, ECC, or lock-step error */
5091  vuint16_t BE_PLL1:1; /* Bidirectional Reset Enable for PLL1 fail */
5092  vuint16_t BE_SWT:1; /* Bidirectional Reset Enable for Software Watchdog Timer */
5093  vuint16_t:1;
5094  vuint16_t BE_CMU0_FHL:1; /* Bidirectional Reset Enable for CMU 0 clock freq. too high/low */
5095  vuint16_t BE_CMU0_OLR:1; /* Bidirectional Reset Enable for oscillator freq. too low */
5096  vuint16_t BE_PLL0:1; /* Bidirectional Reset Enable for PLL0 fail */
5097  vuint16_t BE_CWD:1; /* Bidirectional Reset Enable for Core Watchdog Reset */
5098  vuint16_t BE_SOFT:1; /* Bidirectional Reset Enable for software reset */
5099  vuint16_t BE_CORE:1; /* Bidirectional Reset Enable for core reset */
5100  vuint16_t BE_JTAG:1; /* Bidirectional Reset Enable for JTAG initiated reset */
5101  } B;
5102  } RGM_FBRE_16B_tag;
5103 
5104 
5105 
5106  typedef struct RGM_struct_tag { /* start of RGM_tag */
5107  /* Functional Event Status Register */
5108  RGM_FES_16B_tag FES; /* offset: 0x0000 size: 16 bit */
5109  /* Destructive Event Status Register */
5110  RGM_DES_16B_tag DES; /* offset: 0x0002 size: 16 bit */
5111  /* Functional Event Reset Disable Register */
5112  RGM_FERD_16B_tag FERD; /* offset: 0x0004 size: 16 bit */
5113  /* Destructive Event Reset Disable Register */
5114  RGM_DERD_16B_tag DERD; /* offset: 0x0006 size: 16 bit */
5115  int8_t RGM_reserved_0008[8];
5116  /* Functional Event Alternate Request Register */
5117  RGM_FEAR_16B_tag FEAR; /* offset: 0x0010 size: 16 bit */
5118  int8_t RGM_reserved_0012[6];
5119  /* Functional Event Short Sequence Register */
5120  RGM_FESS_16B_tag FESS; /* offset: 0x0018 size: 16 bit */
5121  int8_t RGM_reserved_001A[2];
5122  /* Functional Bidirectional Reset Enable Register */
5123  RGM_FBRE_16B_tag FBRE; /* offset: 0x001C size: 16 bit */
5124  } RGM_tag;
5125 
5126 
5127 #define RGM (*(volatile RGM_tag *) 0xC3FE4000UL)
5128 
5129 
5130 
5131 /****************************************************************/
5132 /* */
5133 /* Module: PCU */
5134 /* */
5135 /****************************************************************/
5136 
5137 
5138  /* Register layout for all registers PCONF... */
5139 
5140  typedef union { /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */
5141  vuint32_t R;
5142  struct {
5143  vuint32_t:18;
5144  vuint32_t STBY0:1; /* Power domain control during STBY0 */
5145  vuint32_t:2;
5146  vuint32_t STOP0:1; /* Power domain control during STOP0 */
5147  vuint32_t:1;
5148  vuint32_t HALT0:1; /* Power domain control during HALT0 */
5149  vuint32_t RUN3:1; /* Power domain control during RUN3 */
5150  vuint32_t RUN2:1; /* Power domain control during RUN2 */
5151  vuint32_t RUN1:1; /* Power domain control during RUN1 */
5152  vuint32_t RUN0:1; /* Power domain control during RUN0 */
5153  vuint32_t DRUN:1; /* Power domain control during DRUN */
5154  vuint32_t SAFE:1; /* Power domain control during SAFE */
5155  vuint32_t TEST:1; /* Power domain control during TEST */
5156  vuint32_t RST:1; /* Power domain control during RST */
5157  } B;
5158  } PCU_PCONF_32B_tag;
5159 
5160  typedef union { /* PCU_PSTAT - Power Domain Status Register */
5161  vuint32_t R;
5162  struct {
5163  vuint32_t:16;
5164  vuint32_t PD15:1; /* Power Status for Power Domain 15 */
5165  vuint32_t PD14:1; /* Power Status for Power Domain 14 */
5166  vuint32_t PD13:1; /* Power Status for Power Domain 13 */
5167  vuint32_t PD12:1; /* Power Status for Power Domain 12 */
5168  vuint32_t PD11:1; /* Power Status for Power Domain 11 */
5169  vuint32_t PD10:1; /* Power Status for Power Domain 10 */
5170  vuint32_t PD9:1; /* Power Status for Power Domain 9 */
5171  vuint32_t PD8:1; /* Power Status for Power Domain 8 */
5172  vuint32_t PD7:1; /* Power Status for Power Domain 7 */
5173  vuint32_t PD6:1; /* Power Status for Power Domain 6 */
5174  vuint32_t PD5:1; /* Power Status for Power Domain 5 */
5175  vuint32_t PD4:1; /* Power Status for Power Domain 4 */
5176  vuint32_t PD3:1; /* Power Status for Power Domain 3 */
5177  vuint32_t PD2:1; /* Power Status for Power Domain 2 */
5178  vuint32_t PD1:1; /* Power Status for Power Domain 1 */
5179  vuint32_t PD0:1; /* Power Status for Power Domain 0 */
5180  } B;
5181  } PCU_PSTAT_32B_tag;
5182 
5183 
5184 
5185  typedef struct PCU_struct_tag { /* start of PCU_tag */
5186  union {
5187  /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */
5188  PCU_PCONF_32B_tag PCONF[16]; /* offset: 0x0000 (0x0004 x 16) */
5189 
5190  struct {
5191  /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */
5192  PCU_PCONF_32B_tag PCONF0; /* offset: 0x0000 size: 32 bit */
5193  PCU_PCONF_32B_tag PCONF1; /* offset: 0x0004 size: 32 bit */
5194  PCU_PCONF_32B_tag PCONF2; /* offset: 0x0008 size: 32 bit */
5195  PCU_PCONF_32B_tag PCONF3; /* offset: 0x000C size: 32 bit */
5196  PCU_PCONF_32B_tag PCONF4; /* offset: 0x0010 size: 32 bit */
5197  PCU_PCONF_32B_tag PCONF5; /* offset: 0x0014 size: 32 bit */
5198  PCU_PCONF_32B_tag PCONF6; /* offset: 0x0018 size: 32 bit */
5199  PCU_PCONF_32B_tag PCONF7; /* offset: 0x001C size: 32 bit */
5200  PCU_PCONF_32B_tag PCONF8; /* offset: 0x0020 size: 32 bit */
5201  PCU_PCONF_32B_tag PCONF9; /* offset: 0x0024 size: 32 bit */
5202  PCU_PCONF_32B_tag PCONF10; /* offset: 0x0028 size: 32 bit */
5203  PCU_PCONF_32B_tag PCONF11; /* offset: 0x002C size: 32 bit */
5204  PCU_PCONF_32B_tag PCONF12; /* offset: 0x0030 size: 32 bit */
5205  PCU_PCONF_32B_tag PCONF13; /* offset: 0x0034 size: 32 bit */
5206  PCU_PCONF_32B_tag PCONF14; /* offset: 0x0038 size: 32 bit */
5207  PCU_PCONF_32B_tag PCONF15; /* offset: 0x003C size: 32 bit */
5208  };
5209 
5210  };
5211  /* PCU_PSTAT - Power Domain Status Register */
5212  PCU_PSTAT_32B_tag PSTAT; /* offset: 0x0040 size: 32 bit */
5213  } PCU_tag;
5214 
5215 
5216 #define PCU (*(volatile PCU_tag *) 0xC3FE8000UL)
5217 
5218 
5219 
5220 /****************************************************************/
5221 /* */
5222 /* Module: PMUCTRL */
5223 /* */
5224 /****************************************************************/
5225 
5226  typedef union { /* PMUCTRL_STATHVD - PMU Status Register HVD */
5227  vuint32_t R;
5228  struct {
5229  vuint32_t:11;
5230  vuint32_t HVDT_LPB:5; /* High Voltage Detector trimming bits LPB bus */
5231  vuint32_t:6;
5232  vuint32_t HVD_M:1; /* High Voltage Detector Main */
5233  vuint32_t HVD_B:1; /* High Voltage Detector Backup */
5234  vuint32_t:4;
5235  vuint32_t HVD_LP:4; /* High Voltage Detector trimming bits LP bus */
5236  } B;
5237  } PMUCTRL_STATHVD_32B_tag;
5238 
5239  typedef union { /* PMUCTRL_STATLVD - PMU Status Register LVD */
5240  vuint32_t R;
5241  struct {
5242  vuint32_t:11;
5243  vuint32_t LVDT_LPB:5; /* Ligh Voltage Detector trimming bits LPB bus */
5244  vuint32_t:6;
5245  vuint32_t LVD_M:1; /* Ligh Voltage Detector Main */
5246  vuint32_t LVD_B:1; /* Ligh Voltage Detector Backup */
5247  vuint32_t:4;
5248  vuint32_t LVD_LP:4; /* Ligh Voltage Detector trimming bits LP bus */
5249  } B;
5250  } PMUCTRL_STATLVD_32B_tag;
5251 
5252  typedef union { /* PMUCTRL_STATIREG - PMU Status Register IREG */
5253  vuint32_t R;
5254  struct {
5255  vuint32_t:28;
5256  vuint32_t IIREG_HP:4; /* Internal ballast REGulator hpreg1 trimming bits */
5257  } B;
5258  } PMUCTRL_STATIREG_32B_tag;
5259 
5260  typedef union { /* PMUCTRL_STATEREG - PMU Status Register EREG */
5261  vuint32_t R;
5262  struct {
5263  vuint32_t:28;
5264  vuint32_t EEREG_HP:4; /* Internal ballast REGulator hpreg1 trimming bits */
5265  } B;
5266  } PMUCTRL_STATEREG_32B_tag;
5267 
5268  typedef union { /* PMUCTRL_STATUS - PMU Status Register STATUS */
5269  vuint32_t R;
5270  struct {
5271  vuint32_t EBMM:1; /* External Ballast Management Mode */
5272  vuint32_t AEBD:1; /* Automatic External Ballast Detection */
5273  vuint32_t ENPN:1; /* External NPN status flag */
5274  vuint32_t:13;
5275  vuint32_t CTB:2; /* Configuration Trace Bits */
5276  vuint32_t:6;
5277  vuint32_t CBS:4; /* Current BIST Status */
5278  vuint32_t CPCS:4; /* Current Pmu Configuration Status */
5279  } B;
5280  } PMUCTRL_STATUS_32B_tag;
5281 
5282  typedef union { /* PMUCTRL_CTRL - PMU Control Register */
5283  vuint32_t R;
5284  struct {
5285  vuint32_t:30;
5286  vuint32_t SILHT:2; /* Start Idle or LVD or HVD BIST Test */
5287  } B;
5288  } PMUCTRL_CTRL_32B_tag;
5289 
5290  typedef union { /* PMUCTRL_MASKF - PMU Mask Fault Register */
5291  vuint32_t R;
5292  struct {
5293  vuint32_t MF_BB:4; /* Mask Fault Bypass Balast */
5294  vuint32_t:28;
5295  } B;
5296  } PMUCTRL_MASKF_32B_tag;
5297 
5298  typedef union { /* PMUCTRL_FAULT - PMU Fault Monitor Register */
5299  vuint32_t R;
5300  struct {
5301  vuint32_t BB_LV:4; /* Bypass Ballast Low Voltage */
5302  vuint32_t:9;
5303  vuint32_t FLNCF:1; /* FLash voltage monitor Non Critical Fault */
5304  vuint32_t IONCF:1; /* IO voltage monitor Non Critical Fault */
5305  vuint32_t RENCF:1; /* REgulator voltage monitor Non Critical Fault */
5306  vuint32_t:13;
5307  vuint32_t LHCF:1; /* Low High voltage detector Critical Fault */
5308  vuint32_t LNCF:1; /* Low voltage detector Non Critical Fault */
5309  vuint32_t HNCF:1; /* High voltage detector Non Critical Fault */
5310  } B;
5311  } PMUCTRL_FAULT_32B_tag;
5312 
5313  typedef union { /* PMUCTRL_IRQS - PMU Interrupt Request Status Register */
5314  vuint32_t R;
5315  struct {
5316  vuint32_t:10;
5317  vuint32_t MFVMP:1; /* Main Flash Voltage Monitor interrupt Pending */
5318  vuint32_t BFVMP:1; /* Backup Flash Voltage Monitor interrupt Pending */
5319  vuint32_t MIVMP:1; /* MAin IO Voltage Monitor interrupt Pending */
5320  vuint32_t BIVMP:1; /* Backup IO Voltage Monitor interrupt Pending */
5321  vuint32_t MRVMP:1; /* Main Regulator Voltage Monitor interrupt Pending */
5322  vuint32_t BRVMP:1; /* Backup Regulator Voltage Monitor interrupt Pending */
5323  vuint32_t:12;
5324  vuint32_t MLVDP:1; /* Main Low Voltage Detector error interrupt Pending */
5325  vuint32_t BLVDP:1; /* Backup Low Voltage Detector error interrupt Pending */
5326  vuint32_t MHVDP:1; /* Main High Voltage Detector error interrupt Pending */
5327  vuint32_t BHVDP:1; /* Backup High Voltage Detector error interrupt Pending */
5328  } B;
5329  } PMUCTRL_IRQS_32B_tag;
5330 
5331  typedef union { /* PMUCTRL_IRQE - PMU Interrupt Request Enable Register */
5332  vuint32_t R;
5333  struct {
5334  vuint32_t:10;
5335  vuint32_t MFVME:1; /* Main Flash Voltage Monitor interrupt Enable */
5336  vuint32_t BFVME:1; /* Backup Flash Voltage Monitor interrupt Enable */
5337  vuint32_t MIVME:1; /* MAin IO Voltage Monitor interrupt Enable */
5338  vuint32_t BIVME:1; /* Backup IO Voltage Monitor interrupt Enable */
5339  vuint32_t MRVME:1; /* Main Regulator Voltage Monitor interrupt Enable */
5340  vuint32_t BRVME:1; /* Backup Regulator Voltage Monitor interrupt Enable */
5341  vuint32_t:12;
5342  vuint32_t MLVDE:1; /* Main Low Voltage Detector error interrupt Enable */
5343  vuint32_t BLVDE:1; /* Backup Low Voltage Detector error interrupt Enable */
5344  vuint32_t MHVDE:1; /* Main High Voltage Detector error interrupt Enable */
5345  vuint32_t BHVDE:1; /* Backup High Voltage Detector error interrupt Enable */
5346  } B;
5347  } PMUCTRL_IRQE_32B_tag;
5348 
5349 
5350 
5351  typedef struct PMUCTRL_struct_tag { /* start of PMUCTRL_tag */
5352  int8_t PMUCTRL_reserved_0000[4];
5353  /* PMUCTRL_STATHVD - PMU Status Register HVD */
5354  PMUCTRL_STATHVD_32B_tag STATHVD; /* offset: 0x0004 size: 32 bit */
5355  /* PMUCTRL_STATLVD - PMU Status Register LVD */
5356  PMUCTRL_STATLVD_32B_tag STATLVD; /* offset: 0x0008 size: 32 bit */
5357  int8_t PMUCTRL_reserved_000C[20];
5358  /* PMUCTRL_STATIREG - PMU Status Register IREG */
5359  PMUCTRL_STATIREG_32B_tag STATIREG; /* offset: 0x0020 size: 32 bit */
5360  /* PMUCTRL_STATEREG - PMU Status Register EREG */
5361  PMUCTRL_STATEREG_32B_tag STATEREG; /* offset: 0x0024 size: 32 bit */
5362  int8_t PMUCTRL_reserved_0028[24];
5363  /* PMUCTRL_STATUS - PMU Status Register STATUS */
5364  PMUCTRL_STATUS_32B_tag STATUS; /* offset: 0x0040 size: 32 bit */
5365  /* PMUCTRL_CTRL - PMU Control Register */
5366  PMUCTRL_CTRL_32B_tag CTRL; /* offset: 0x0044 size: 32 bit */
5367  int8_t PMUCTRL_reserved_0048[40];
5368  /* PMUCTRL_MASKF - PMU Mask Fault Register */
5369  PMUCTRL_MASKF_32B_tag MASKF; /* offset: 0x0070 size: 32 bit */
5370  /* PMUCTRL_FAULT - PMU Fault Monitor Register */
5371  PMUCTRL_FAULT_32B_tag FAULT; /* offset: 0x0074 size: 32 bit */
5372  /* PMUCTRL_IRQS - PMU Interrupt Request Status Register */
5373  PMUCTRL_IRQS_32B_tag IRQS; /* offset: 0x0078 size: 32 bit */
5374  /* PMUCTRL_IRQE - PMU Interrupt Request Enable Register */
5375  PMUCTRL_IRQE_32B_tag IRQE; /* offset: 0x007C size: 32 bit */
5376  } PMUCTRL_tag;
5377 
5378 
5379 #define PMUCTRL (*(volatile PMUCTRL_tag *) 0xC3FE8080UL)
5380 
5381 
5382 
5383 /****************************************************************/
5384 /* */
5385 /* Module: PIT_RTI */
5386 /* */
5387 /****************************************************************/
5388 
5389  typedef union { /* PIT_RTI_PITMCR - PIT Module Control Register */
5390  vuint32_t R;
5391  struct {
5392  vuint32_t:30;
5393  vuint32_t MDIS:1; /* Module Disable. Disable the module clock */
5394  vuint32_t FRZ:1; /* Freeze. Allows the timers to be stoppedwhen the device enters debug mode */
5395  } B;
5396  } PIT_RTI_PITMCR_32B_tag;
5397 
5398 
5399  /* Register layout for all registers LDVAL... */
5400 
5401  typedef union { /* PIT_RTI_LDVAL - Timer Load Value Register */
5402  vuint32_t R;
5403  struct {
5404  vuint32_t TSV:32; /* Time Start Value Bits */
5405  } B;
5406  } PIT_RTI_LDVAL_32B_tag;
5407 
5408 
5409  /* Register layout for all registers CVAL... */
5410 
5411  typedef union { /* PIT_RTI_CVAL - Current Timer Value Register */
5412  vuint32_t R;
5413  struct {
5414  vuint32_t TVL:32; /* Current Timer Value Bits */
5415  } B;
5416  } PIT_RTI_CVAL_32B_tag;
5417 
5418 
5419  /* Register layout for all registers TCTRL... */
5420 
5421  typedef union { /* PIT_RTI_TCTRL - Timer Control Register */
5422  vuint32_t R;
5423  struct {
5424  vuint32_t:30;
5425  vuint32_t TIE:1; /* Timer Interrupt Enable Bit */
5426  vuint32_t TEN:1; /* Timer Enable Bit */
5427  } B;
5428  } PIT_RTI_TCTRL_32B_tag;
5429 
5430 
5431  /* Register layout for all registers TFLG... */
5432 
5433  typedef union { /* PIT_RTI_TFLG - Timer Flag Register */
5434  vuint32_t R;
5435  struct {
5436  vuint32_t:31;
5437  vuint32_t TIF:1; /* Timer Interrupt Flag Bit */
5438  } B;
5439  } PIT_RTI_TFLG_32B_tag;
5440 
5441 
5442  typedef struct PIT_RTI_CHANNEL_struct_tag {
5443 
5444  /* PIT_RTI_LDVAL - Timer Load Value Register */
5445  PIT_RTI_LDVAL_32B_tag LDVAL; /* relative offset: 0x0000 */
5446  /* PIT_RTI_CVAL - Current Timer Value Register */
5447  PIT_RTI_CVAL_32B_tag CVAL; /* relative offset: 0x0004 */
5448  /* PIT_RTI_TCTRL - Timer Control Register */
5449  PIT_RTI_TCTRL_32B_tag TCTRL; /* relative offset: 0x0008 */
5450  /* PIT_RTI_TFLG - Timer Flag Register */
5451  PIT_RTI_TFLG_32B_tag TFLG; /* relative offset: 0x000C */
5452 
5453  } PIT_RTI_CHANNEL_tag;
5454 
5455 
5456  typedef struct PIT_RTI_struct_tag { /* start of PIT_RTI_tag */
5457  /* PIT_RTI_PITMCR - PIT Module Control Register */
5458  PIT_RTI_PITMCR_32B_tag PITMCR; /* offset: 0x0000 size: 32 bit */
5459  int8_t PIT_RTI_reserved_0004_C[252];
5460  union {
5461  /* Register set CHANNEL */
5462  PIT_RTI_CHANNEL_tag CHANNEL[4]; /* offset: 0x0100 (0x0010 x 4) */
5463 
5464  struct {
5465  /* PIT_RTI_LDVAL - Timer Load Value Register */
5466  PIT_RTI_LDVAL_32B_tag LDVAL0; /* offset: 0x0100 size: 32 bit */
5467  /* PIT_RTI_CVAL - Current Timer Value Register */
5468  PIT_RTI_CVAL_32B_tag CVAL0; /* offset: 0x0104 size: 32 bit */
5469  /* PIT_RTI_TCTRL - Timer Control Register */
5470  PIT_RTI_TCTRL_32B_tag TCTRL0; /* offset: 0x0108 size: 32 bit */
5471  /* PIT_RTI_TFLG - Timer Flag Register */
5472  PIT_RTI_TFLG_32B_tag TFLG0; /* offset: 0x010C size: 32 bit */
5473  /* PIT_RTI_LDVAL - Timer Load Value Register */
5474  PIT_RTI_LDVAL_32B_tag LDVAL1; /* offset: 0x0110 size: 32 bit */
5475  /* PIT_RTI_CVAL - Current Timer Value Register */
5476  PIT_RTI_CVAL_32B_tag CVAL1; /* offset: 0x0114 size: 32 bit */
5477  /* PIT_RTI_TCTRL - Timer Control Register */
5478  PIT_RTI_TCTRL_32B_tag TCTRL1; /* offset: 0x0118 size: 32 bit */
5479  /* PIT_RTI_TFLG - Timer Flag Register */
5480  PIT_RTI_TFLG_32B_tag TFLG1; /* offset: 0x011C size: 32 bit */
5481  /* PIT_RTI_LDVAL - Timer Load Value Register */
5482  PIT_RTI_LDVAL_32B_tag LDVAL2; /* offset: 0x0120 size: 32 bit */
5483  /* PIT_RTI_CVAL - Current Timer Value Register */
5484  PIT_RTI_CVAL_32B_tag CVAL2; /* offset: 0x0124 size: 32 bit */
5485  /* PIT_RTI_TCTRL - Timer Control Register */
5486  PIT_RTI_TCTRL_32B_tag TCTRL2; /* offset: 0x0128 size: 32 bit */
5487  /* PIT_RTI_TFLG - Timer Flag Register */
5488  PIT_RTI_TFLG_32B_tag TFLG2; /* offset: 0x012C size: 32 bit */
5489  /* PIT_RTI_LDVAL - Timer Load Value Register */
5490  PIT_RTI_LDVAL_32B_tag LDVAL3; /* offset: 0x0130 size: 32 bit */
5491  /* PIT_RTI_CVAL - Current Timer Value Register */
5492  PIT_RTI_CVAL_32B_tag CVAL3; /* offset: 0x0134 size: 32 bit */
5493  /* PIT_RTI_TCTRL - Timer Control Register */
5494  PIT_RTI_TCTRL_32B_tag TCTRL3; /* offset: 0x0138 size: 32 bit */
5495  /* PIT_RTI_TFLG - Timer Flag Register */
5496  PIT_RTI_TFLG_32B_tag TFLG3; /* offset: 0x013C size: 32 bit */
5497  };
5498 
5499  };
5500  } PIT_RTI_tag;
5501 
5502 
5503 #define PIT_RTI (*(volatile PIT_RTI_tag *) 0xC3FF0000UL)
5504 
5505 
5506 
5507 /****************************************************************/
5508 /* */
5509 /* Module: ADC */
5510 /* */
5511 /****************************************************************/
5512 
5513  typedef union { /* module configuration register */
5514  vuint32_t R;
5515  struct {
5516  vuint32_t OWREN:1; /* Overwrite enable */
5517  vuint32_t WLSIDE:1; /* Write Left/right Alligned */
5518  vuint32_t MODE:1; /* One Shot/Scan Mode Selectiom */
5519  vuint32_t EDGLEV:1; /* edge or level selection for external start trigger */
5520  vuint32_t TRGEN:1; /* external trigger enable */
5521  vuint32_t EDGE:1; /* start trigger egde /level detection */
5522  vuint32_t XSTRTEN:1; /* EXTERNAL START ENABLE */
5523  vuint32_t NSTART:1; /* start normal conversion */
5524  vuint32_t:1;
5525  vuint32_t JTRGEN:1; /* Injectin External Trigger Enable */
5526  vuint32_t JEDGE:1; /* start trigger egde /level detection for injected */
5527  vuint32_t JSTART:1; /* injected conversion start */
5528  vuint32_t:2;
5529  vuint32_t CTUEN:1; /* CTU enabaled */
5530  vuint32_t:8;
5531  vuint32_t ADCLKSEL:1; /* Select which clock for device */
5532  vuint32_t ABORTCHAIN:1; /* abort chain conversion */
5533  vuint32_t ABORT:1; /* abort current conversion */
5534 #ifndef USE_FIELD_ALIASES_ADC
5535  vuint32_t ACKO:1; /* Auto Clock Off Enable */
5536 #else
5537  vuint32_t ACK0:1; /* deprecated name - please avoid */
5538 #endif
5539  vuint32_t OFFREFRESH:1; /* offset phase selection */
5540  vuint32_t OFFCANC:1; /* offset phase cancellation selection */
5541  vuint32_t:2;
5542  vuint32_t PWDN:1; /* Power Down Enable */
5543  } B;
5544  } ADC_MCR_32B_tag;
5545 
5546  typedef union { /* module status register */
5547  vuint32_t R;
5548  struct {
5549  vuint32_t:7;
5550  vuint32_t NSTART:1; /* normal conversion status */
5551  vuint32_t JABORT:1; /* Injection chain abort status */
5552  vuint32_t:2;
5553  vuint32_t JSTART:1; /* Injection Start status */
5554  vuint32_t:3;
5555  vuint32_t CTUSTART:1; /* ctu start status */
5556  vuint32_t CHADDR:7; /* which address conv is goin on */
5557  vuint32_t:3;
5558 #ifndef USE_FIELD_ALIASES_ADC
5559  vuint32_t ACKO:1; /* Auto Clock Off Enable status */
5560 #else
5561  vuint32_t ACK0:1; /* deprecated name - please avoid */
5562 #endif
5563  vuint32_t OFFREFRESH:1; /* offset refresh status */
5564  vuint32_t OFFCANC:1; /* offset phase cancellation status */
5565  vuint32_t ADCSTATUS:3; /* status of ADC FSM */
5566  } B;
5567  } ADC_MSR_32B_tag;
5568 
5569  typedef union { /* Interrupt status register */
5570  vuint32_t R;
5571  struct {
5572  vuint32_t:25;
5573  vuint32_t OFFCANCOVR:1; /* Offset cancellation phase over */
5574  vuint32_t EOFFSET:1; /* error in offset refresh */
5575  vuint32_t EOCTU:1; /* end of CTU channel conversion */
5576  vuint32_t JEOC:1; /* end of injected channel conversion */
5577  vuint32_t JECH:1; /* end ofinjected chain conversion */
5578  vuint32_t EOC:1; /* end of channel conversion */
5579  vuint32_t ECH:1; /* end of chain conversion */
5580  } B;
5581  } ADC_ISR_32B_tag;
5582 
5583  typedef union { /* CHANNEL PENDING REGISTER 0 */
5584  vuint32_t R;
5585  struct {
5586 #ifndef USE_FIELD_ALIASES_ADC
5587  vuint32_t EOC_CH31:1; /* Channel 31 conversion over */
5588 #else
5589  vuint32_t EOC31:1; /* deprecated name - please avoid */
5590 #endif
5591 #ifndef USE_FIELD_ALIASES_ADC
5592  vuint32_t EOC_CH30:1; /* Channel 30 conversion over */
5593 #else
5594  vuint32_t EOC30:1; /* deprecated name - please avoid */
5595 #endif
5596 #ifndef USE_FIELD_ALIASES_ADC
5597  vuint32_t EOC_CH29:1; /* Channel 29 conversion over */
5598 #else
5599  vuint32_t EOC29:1; /* deprecated name - please avoid */
5600 #endif
5601 #ifndef USE_FIELD_ALIASES_ADC
5602  vuint32_t EOC_CH28:1; /* Channel 28 conversion over */
5603 #else
5604  vuint32_t EOC28:1; /* deprecated name - please avoid */
5605 #endif
5606 #ifndef USE_FIELD_ALIASES_ADC
5607  vuint32_t EOC_CH27:1; /* Channel 27 conversion over */
5608 #else
5609  vuint32_t EOC27:1; /* deprecated name - please avoid */
5610 #endif
5611 #ifndef USE_FIELD_ALIASES_ADC
5612  vuint32_t EOC_CH26:1; /* Channel 26 conversion over */
5613 #else
5614  vuint32_t EOC26:1; /* deprecated name - please avoid */
5615 #endif
5616 #ifndef USE_FIELD_ALIASES_ADC
5617  vuint32_t EOC_CH25:1; /* Channel 25 conversion over */
5618 #else
5619  vuint32_t EOC25:1; /* deprecated name - please avoid */
5620 #endif
5621 #ifndef USE_FIELD_ALIASES_ADC
5622  vuint32_t EOC_CH24:1; /* Channel 24 conversion over */
5623 #else
5624  vuint32_t EOC24:1; /* deprecated name - please avoid */
5625 #endif
5626 #ifndef USE_FIELD_ALIASES_ADC
5627  vuint32_t EOC_CH23:1; /* Channel 23 conversion over */
5628 #else
5629  vuint32_t EOC23:1; /* deprecated name - please avoid */
5630 #endif
5631 #ifndef USE_FIELD_ALIASES_ADC
5632  vuint32_t EOC_CH22:1; /* Channel 22 conversion over */
5633 #else
5634  vuint32_t EOC22:1; /* deprecated name - please avoid */
5635 #endif
5636 #ifndef USE_FIELD_ALIASES_ADC
5637  vuint32_t EOC_CH21:1; /* Channel 21 conversion over */
5638 #else
5639  vuint32_t EOC21:1; /* deprecated name - please avoid */
5640 #endif
5641 #ifndef USE_FIELD_ALIASES_ADC
5642  vuint32_t EOC_CH20:1; /* Channel 20 conversion over */
5643 #else
5644  vuint32_t EOC20:1; /* deprecated name - please avoid */
5645 #endif
5646 #ifndef USE_FIELD_ALIASES_ADC
5647  vuint32_t EOC_CH19:1; /* Channel 19 conversion over */
5648 #else
5649  vuint32_t EOC19:1; /* deprecated name - please avoid */
5650 #endif
5651 #ifndef USE_FIELD_ALIASES_ADC
5652  vuint32_t EOC_CH18:1; /* Channel 18 conversion over */
5653 #else
5654  vuint32_t EOC18:1; /* deprecated name - please avoid */
5655 #endif
5656 #ifndef USE_FIELD_ALIASES_ADC
5657  vuint32_t EOC_CH17:1; /* Channel 17 conversion over */
5658 #else
5659  vuint32_t EOC17:1; /* deprecated name - please avoid */
5660 #endif
5661 #ifndef USE_FIELD_ALIASES_ADC
5662  vuint32_t EOC_CH16:1; /* Channel 16 conversion over */
5663 #else
5664  vuint32_t EOC16:1; /* deprecated name - please avoid */
5665 #endif
5666 #ifndef USE_FIELD_ALIASES_ADC
5667  vuint32_t EOC_CH15:1; /* Channel 15 conversion over */
5668 #else
5669  vuint32_t EOC15:1; /* deprecated name - please avoid */
5670 #endif
5671 #ifndef USE_FIELD_ALIASES_ADC
5672  vuint32_t EOC_CH14:1; /* Channel 14 conversion over */
5673 #else
5674  vuint32_t EOC14:1; /* deprecated name - please avoid */
5675 #endif
5676 #ifndef USE_FIELD_ALIASES_ADC
5677  vuint32_t EOC_CH13:1; /* Channel 13 conversion over */
5678 #else
5679  vuint32_t EOC13:1; /* deprecated name - please avoid */
5680 #endif
5681 #ifndef USE_FIELD_ALIASES_ADC
5682  vuint32_t EOC_CH12:1; /* Channel 12 conversion over */
5683 #else
5684  vuint32_t EOC12:1; /* deprecated name - please avoid */
5685 #endif
5686 #ifndef USE_FIELD_ALIASES_ADC
5687  vuint32_t EOC_CH11:1; /* Channel 11 conversion over */
5688 #else
5689  vuint32_t EOC11:1; /* deprecated name - please avoid */
5690 #endif
5691 #ifndef USE_FIELD_ALIASES_ADC
5692  vuint32_t EOC_CH10:1; /* Channel 10 conversion over */
5693 #else
5694  vuint32_t EOC10:1; /* deprecated name - please avoid */
5695 #endif
5696 #ifndef USE_FIELD_ALIASES_ADC
5697  vuint32_t EOC_CH9:1; /* Channel 9 conversion over */
5698 #else
5699  vuint32_t EOC9:1; /* deprecated name - please avoid */
5700 #endif
5701 #ifndef USE_FIELD_ALIASES_ADC
5702  vuint32_t EOC_CH8:1; /* Channel 8 conversion over */
5703 #else
5704  vuint32_t EOC8:1; /* deprecated name - please avoid */
5705 #endif
5706 #ifndef USE_FIELD_ALIASES_ADC
5707  vuint32_t EOC_CH7:1; /* Channel 7 conversion over */
5708 #else
5709  vuint32_t EOC7:1; /* deprecated name - please avoid */
5710 #endif
5711 #ifndef USE_FIELD_ALIASES_ADC
5712  vuint32_t EOC_CH6:1; /* Channel 6 conversion over */
5713 #else
5714  vuint32_t EOC6:1; /* deprecated name - please avoid */
5715 #endif
5716 #ifndef USE_FIELD_ALIASES_ADC
5717  vuint32_t EOC_CH5:1; /* Channel 5 conversion over */
5718 #else
5719  vuint32_t EOC5:1; /* deprecated name - please avoid */
5720 #endif
5721 #ifndef USE_FIELD_ALIASES_ADC
5722  vuint32_t EOC_CH4:1; /* Channel 4 conversion over */
5723 #else
5724  vuint32_t EOC4:1; /* deprecated name - please avoid */
5725 #endif
5726 #ifndef USE_FIELD_ALIASES_ADC
5727  vuint32_t EOC_CH3:1; /* Channel 3 conversion over */
5728 #else
5729  vuint32_t EOC3:1; /* deprecated name - please avoid */
5730 #endif
5731 #ifndef USE_FIELD_ALIASES_ADC
5732  vuint32_t EOC_CH2:1; /* Channel 2 conversion over */
5733 #else
5734  vuint32_t EOC2:1; /* deprecated name - please avoid */
5735 #endif
5736 #ifndef USE_FIELD_ALIASES_ADC
5737  vuint32_t EOC_CH1:1; /* Channel 1 conversion over */
5738 #else
5739  vuint32_t EOC1:1; /* deprecated name - please avoid */
5740 #endif
5741 #ifndef USE_FIELD_ALIASES_ADC
5742  vuint32_t EOC_CH0:1; /* Channel 0 conversion over */
5743 #else
5744  vuint32_t EOC0:1; /* deprecated name - please avoid */
5745 #endif
5746  } B;
5747  } ADC_CEOCFR0_32B_tag;
5748 
5749  typedef union { /* CHANNEL PENDING REGISTER 1 */
5750  vuint32_t R;
5751  struct {
5752  vuint32_t EOC_CH63:1; /* Channel 63 conversion over */
5753  vuint32_t EOC_CH62:1; /* Channel 62 conversion over */
5754  vuint32_t EOC_CH61:1; /* Channel 61 conversion over */
5755  vuint32_t EOC_CH60:1; /* Channel 60 conversion over */
5756  vuint32_t EOC_CH59:1; /* Channel 59 conversion over */
5757  vuint32_t EOC_CH58:1; /* Channel 58 conversion over */
5758  vuint32_t EOC_CH57:1; /* Channel 57 conversion over */
5759  vuint32_t EOC_CH56:1; /* Channel 56 conversion over */
5760  vuint32_t EOC_CH55:1; /* Channel 55 conversion over */
5761  vuint32_t EOC_CH54:1; /* Channel 54 conversion over */
5762  vuint32_t EOC_CH53:1; /* Channel 53 conversion over */
5763  vuint32_t EOC_CH52:1; /* Channel 52 conversion over */
5764  vuint32_t EOC_CH51:1; /* Channel 51 conversion over */
5765  vuint32_t EOC_CH50:1; /* Channel 50 conversion over */
5766  vuint32_t EOC_CH49:1; /* Channel 49 conversion over */
5767  vuint32_t EOC_CH48:1; /* Channel 48 conversion over */
5768  vuint32_t EOC_CH47:1; /* Channel 47 conversion over */
5769  vuint32_t EOC_CH46:1; /* Channel 46 conversion over */
5770  vuint32_t EOC_CH45:1; /* Channel 45 conversion over */
5771  vuint32_t EOC_CH44:1; /* Channel 44 conversion over */
5772  vuint32_t EOC_CH43:1; /* Channel 43 conversion over */
5773  vuint32_t EOC_CH42:1; /* Channel 42 conversion over */
5774  vuint32_t EOC_CH41:1; /* Channel 41 conversion over */
5775  vuint32_t EOC_CH40:1; /* Channel 40 conversion over */
5776  vuint32_t EOC_CH39:1; /* Channel 39 conversion over */
5777  vuint32_t EOC_CH38:1; /* Channel 38 conversion over */
5778  vuint32_t EOC_CH37:1; /* Channel 37 conversion over */
5779  vuint32_t EOC_CH36:1; /* Channel 36 conversion over */
5780  vuint32_t EOC_CH35:1; /* Channel 35 conversion over */
5781  vuint32_t EOC_CH34:1; /* Channel 34 conversion over */
5782  vuint32_t EOC_CH33:1; /* Channel 33 conversion over */
5783  vuint32_t EOC_CH32:1; /* Channel 32 conversion over */
5784  } B;
5785  } ADC_CEOCFR1_32B_tag;
5786 
5787  typedef union { /* CHANNEL PENDING REGISTER 2 */
5788  vuint32_t R;
5789  struct {
5790  vuint32_t EOC_CH95:1; /* Channel 95 conversion over */
5791  vuint32_t EOC_CH94:1; /* Channel 94 conversion over */
5792  vuint32_t EOC_CH93:1; /* Channel 93 conversion over */
5793  vuint32_t EOC_CH92:1; /* Channel 92 conversion over */
5794  vuint32_t EOC_CH91:1; /* Channel 91 conversion over */
5795  vuint32_t EOC_CH90:1; /* Channel 90 conversion over */
5796  vuint32_t EOC_CH89:1; /* Channel 89 conversion over */
5797  vuint32_t EOC_CH88:1; /* Channel 88 conversion over */
5798  vuint32_t EOC_CH87:1; /* Channel 87 conversion over */
5799  vuint32_t EOC_CH86:1; /* Channel 86 conversion over */
5800  vuint32_t EOC_CH85:1; /* Channel 85 conversion over */
5801  vuint32_t EOC_CH84:1; /* Channel 84 conversion over */
5802  vuint32_t EOC_CH83:1; /* Channel 83 conversion over */
5803  vuint32_t EOC_CH82:1; /* Channel 82 conversion over */
5804  vuint32_t EOC_CH81:1; /* Channel 81 conversion over */
5805  vuint32_t EOC_CH80:1; /* Channel 80 conversion over */
5806  vuint32_t EOC_CH79:1; /* Channel 79 conversion over */
5807  vuint32_t EOC_CH78:1; /* Channel 78 conversion over */
5808  vuint32_t EOC_CH77:1; /* Channel 77 conversion over */
5809  vuint32_t EOC_CH76:1; /* Channel 76 conversion over */
5810  vuint32_t EOC_CH75:1; /* Channel 75 conversion over */
5811  vuint32_t EOC_CH74:1; /* Channel 74 conversion over */
5812  vuint32_t EOC_CH73:1; /* Channel 73 conversion over */
5813  vuint32_t EOC_CH72:1; /* Channel 72 conversion over */
5814  vuint32_t EOC_CH71:1; /* Channel 71 conversion over */
5815  vuint32_t EOC_CH70:1; /* Channel 70 conversion over */
5816  vuint32_t EOC_CH69:1; /* Channel 69 conversion over */
5817  vuint32_t EOC_CH68:1; /* Channel 68 conversion over */
5818  vuint32_t EOC_CH67:1; /* Channel 67 conversion over */
5819  vuint32_t EOC_CH66:1; /* Channel 66 conversion over */
5820  vuint32_t EOC_CH65:1; /* Channel 65 conversion over */
5821  vuint32_t EOC_CH64:1; /* Channel 64 conversion over */
5822  } B;
5823  } ADC_CEOCFR2_32B_tag;
5824 
5825  typedef union { /* interrupt mask register */
5826  vuint32_t R;
5827  struct {
5828  vuint32_t:25;
5829  vuint32_t MSKOFFCANCOVR:1; /* mask bit for Calibration over */
5830  vuint32_t MSKEOFFSET:1; /* mask bit for Error in offset refresh */
5831  vuint32_t MSKEOCTU:1; /* mask bit for EOCTU */
5832  vuint32_t MSKJEOC:1; /* mask bit for JEOC */
5833  vuint32_t MSKJECH:1; /* mask bit for JECH */
5834  vuint32_t MSKEOC:1; /* mask bit for EOC */
5835  vuint32_t MSKECH:1; /* mask bit for ECH */
5836  } B;
5837  } ADC_IMR_32B_tag;
5838 
5839  typedef union { /* CHANNEL INTERRUPT MASK REGISTER 0 */
5840  vuint32_t R;
5841  struct {
5842  vuint32_t CIM31:1; /* Channel 31 mask register */
5843  vuint32_t CIM30:1; /* Channel 30 mask register */
5844  vuint32_t CIM29:1; /* Channel 29 mask register */
5845  vuint32_t CIM28:1; /* Channel 28 mask register */
5846  vuint32_t CIM27:1; /* Channel 27 mask register */
5847  vuint32_t CIM26:1; /* Channel 26 mask register */
5848  vuint32_t CIM25:1; /* Channel 25 mask register */
5849  vuint32_t CIM24:1; /* Channel 24 mask register */
5850  vuint32_t CIM23:1; /* Channel 23 mask register */
5851  vuint32_t CIM22:1; /* Channel 22 mask register */
5852  vuint32_t CIM21:1; /* Channel 21 mask register */
5853  vuint32_t CIM20:1; /* Channel 20 mask register */
5854  vuint32_t CIM19:1; /* Channel 19 mask register */
5855  vuint32_t CIM18:1; /* Channel 18 mask register */
5856  vuint32_t CIM17:1; /* Channel 17 mask register */
5857  vuint32_t CIM16:1; /* Channel 16 mask register */
5858  vuint32_t CIM15:1; /* Channel 15 mask register */
5859  vuint32_t CIM14:1; /* Channel 14 mask register */
5860  vuint32_t CIM13:1; /* Channel 13 mask register */
5861  vuint32_t CIM12:1; /* Channel 12 mask register */
5862  vuint32_t CIM11:1; /* Channel 11 mask register */
5863  vuint32_t CIM10:1; /* Channel 10 mask register */
5864  vuint32_t CIM9:1; /* Channel 9 mask register */
5865  vuint32_t CIM8:1; /* Channel 8 mask register */
5866  vuint32_t CIM7:1; /* Channel 7 mask register */
5867  vuint32_t CIM6:1; /* Channel 6 mask register */
5868  vuint32_t CIM5:1; /* Channel 5 mask register */
5869  vuint32_t CIM4:1; /* Channel 4 mask register */
5870  vuint32_t CIM3:1; /* Channel 3 mask register */
5871  vuint32_t CIM2:1; /* Channel 2 mask register */
5872  vuint32_t CIM1:1; /* Channel 1 mask register */
5873  vuint32_t CIM0:1; /* Channel 0 mask register */
5874  } B;
5875  } ADC_CIMR0_32B_tag;
5876 
5877  typedef union { /* CHANNEL INTERRUPT MASK REGISTER 1 */
5878  vuint32_t R;
5879  struct {
5880  vuint32_t CIM63:1; /* Channel 63 mask register */
5881  vuint32_t CIM62:1; /* Channel 62 mask register */
5882  vuint32_t CIM61:1; /* Channel 61 mask register */
5883  vuint32_t CIM60:1; /* Channel 60 mask register */
5884  vuint32_t CIM59:1; /* Channel 59 mask register */
5885  vuint32_t CIM58:1; /* Channel 58 mask register */
5886  vuint32_t CIM57:1; /* Channel 57 mask register */
5887  vuint32_t CIM56:1; /* Channel 56 mask register */
5888  vuint32_t CIM55:1; /* Channel 55 mask register */
5889  vuint32_t CIM54:1; /* Channel 54 mask register */
5890  vuint32_t CIM53:1; /* Channel 53 mask register */
5891  vuint32_t CIM52:1; /* Channel 52 mask register */
5892  vuint32_t CIM51:1; /* Channel 51 mask register */
5893  vuint32_t CIM50:1; /* Channel 50 mask register */
5894  vuint32_t CIM49:1; /* Channel 49 mask register */
5895  vuint32_t CIM48:1; /* Channel 48 mask register */
5896  vuint32_t CIM47:1; /* Channel 47 mask register */
5897  vuint32_t CIM46:1; /* Channel 46 mask register */
5898  vuint32_t CIM45:1; /* Channel 45 mask register */
5899  vuint32_t CIM44:1; /* Channel 44 mask register */
5900  vuint32_t CIM43:1; /* Channel 43 mask register */
5901  vuint32_t CIM42:1; /* Channel 42 mask register */
5902  vuint32_t CIM41:1; /* Channel 41 mask register */
5903  vuint32_t CIM40:1; /* Channel 40 mask register */
5904  vuint32_t CIM39:1; /* Channel 39 mask register */
5905  vuint32_t CIM38:1; /* Channel 38 mask register */
5906  vuint32_t CIM37:1; /* Channel 37 mask register */
5907  vuint32_t CIM36:1; /* Channel 36 mask register */
5908  vuint32_t CIM35:1; /* Channel 35 mask register */
5909  vuint32_t CIM34:1; /* Channel 34 mask register */
5910  vuint32_t CIM33:1; /* Channel 33 mask register */
5911  vuint32_t CIM32:1; /* Channel 32 mask register */
5912  } B;
5913  } ADC_CIMR1_32B_tag;
5914 
5915  typedef union { /* CHANNEL INTERRUPT MASK REGISTER 2 */
5916  vuint32_t R;
5917  struct {
5918  vuint32_t CIM95:1; /* Channel 95 mask register */
5919  vuint32_t CIM94:1; /* Channel 94 mask register */
5920  vuint32_t CIM93:1; /* Channel 93 mask register */
5921  vuint32_t CIM92:1; /* Channel 92 mask register */
5922  vuint32_t CIM91:1; /* Channel 91 mask register */
5923  vuint32_t CIM90:1; /* Channel 90 mask register */
5924  vuint32_t CIM89:1; /* Channel 89 mask register */
5925  vuint32_t CIM88:1; /* Channel 88 mask register */
5926  vuint32_t CIM87:1; /* Channel 87 mask register */
5927  vuint32_t CIM86:1; /* Channel 86 mask register */
5928  vuint32_t CIM85:1; /* Channel 85 mask register */
5929  vuint32_t CIM84:1; /* Channel 84 mask register */
5930  vuint32_t CIM83:1; /* Channel 83 mask register */
5931  vuint32_t CIM82:1; /* Channel 82 mask register */
5932  vuint32_t CIM81:1; /* Channel 81 mask register */
5933  vuint32_t CIM80:1; /* Channel 80 mask register */
5934  vuint32_t CIM79:1; /* Channel 79 mask register */
5935  vuint32_t CIM78:1; /* Channel 78 mask register */
5936  vuint32_t CIM77:1; /* Channel 77 mask register */
5937  vuint32_t CIM76:1; /* Channel 76 mask register */
5938  vuint32_t CIM75:1; /* Channel 75 mask register */
5939  vuint32_t CIM74:1; /* Channel 74 mask register */
5940  vuint32_t CIM73:1; /* Channel 73 mask register */
5941  vuint32_t CIM72:1; /* Channel 72 mask register */
5942  vuint32_t CIM71:1; /* Channel 71 mask register */
5943  vuint32_t CIM70:1; /* Channel 70 mask register */
5944  vuint32_t CIM69:1; /* Channel 69 mask register */
5945  vuint32_t CIM68:1; /* Channel 68 mask register */
5946  vuint32_t CIM67:1; /* Channel 67 mask register */
5947  vuint32_t CIM66:1; /* Channel 66 mask register */
5948  vuint32_t CIM65:1; /* Channel 65 mask register */
5949  vuint32_t CIM64:1; /* Channel 64 mask register */
5950  } B;
5951  } ADC_CIMR2_32B_tag;
5952 
5953  typedef union { /* Watchdog Threshold interrupt status register */
5954  vuint32_t R;
5955  struct {
5956  vuint32_t:24;
5957  vuint32_t WDG3H:1; /* Interrupt generated on the value being higher than the HTHV 3 */
5958  vuint32_t WDG2H:1; /* Interrupt generated on the value being higher than the HTHV 2 */
5959  vuint32_t WDG1H:1; /* Interrupt generated on the value being higher than the HTHV 1 */
5960  vuint32_t WDG0H:1; /* Interrupt generated on the value being higher than the HTHV 0 */
5961  vuint32_t WDG3L:1; /* Interrupt generated on the value being lower than the LTHV 3 */
5962  vuint32_t WDG2L:1; /* Interrupt generated on the value being lower than the LTHV 2 */
5963  vuint32_t WDG1L:1; /* Interrupt generated on the value being lower than the LTHV 1 */
5964  vuint32_t WDG0L:1; /* Interrupt generated on the value being lower than the LTHV 0 */
5965  } B;
5966  } ADC_WTISR_32B_tag;
5967 
5968  typedef union { /* Watchdog interrupt MASK register */
5969  vuint32_t R;
5970  struct {
5971  vuint32_t:24;
5972  vuint32_t MSKWDG3H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 3 */
5973  vuint32_t MSKWDG2H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 2 */
5974  vuint32_t MSKWDG1H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 1 */
5975  vuint32_t MSKWDG0H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 0 */
5976  vuint32_t MSKWDG3L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 3 */
5977  vuint32_t MSKWDG2L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 2 */
5978  vuint32_t MSKWDG1L:1; /* MAsk enable for Interrupt generated on the value being lower than the LTHV 1 */
5979  vuint32_t MSKWDG0L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 0 */
5980  } B;
5981  } ADC_WTIMR_32B_tag;
5982 
5983  typedef union { /* DMAE register */
5984  vuint32_t R;
5985  struct {
5986  vuint32_t:30;
5987  vuint32_t DCLR:1; /* DMA clear sequence enable */
5988  vuint32_t DMAEN:1; /* DMA global enable */
5989  } B;
5990  } ADC_DMAE_32B_tag;
5991 
5992  typedef union { /* DMA REGISTER 0 */
5993  vuint32_t R;
5994  struct {
5995  vuint32_t DMA31:1; /* Channel 31 DMA Enable */
5996  vuint32_t DMA30:1; /* Channel 30 DMA Enable */
5997  vuint32_t DMA29:1; /* Channel 29 DMA Enable */
5998  vuint32_t DMA28:1; /* Channel 28 DMA Enable */
5999  vuint32_t DMA27:1; /* Channel 27 DMA Enable */
6000  vuint32_t DMA26:1; /* Channel 26 DMA Enable */
6001  vuint32_t DMA25:1; /* Channel 25 DMA Enable */
6002  vuint32_t DMA24:1; /* Channel 24 DMA Enable */
6003  vuint32_t DMA23:1; /* Channel 23 DMA Enable */
6004  vuint32_t DMA22:1; /* Channel 22 DMA Enable */
6005  vuint32_t DMA21:1; /* Channel 21 DMA Enable */
6006  vuint32_t DMA20:1; /* Channel 20 DMA Enable */
6007  vuint32_t DMA19:1; /* Channel 19 DMA Enable */
6008  vuint32_t DMA18:1; /* Channel 18 DMA Enable */
6009  vuint32_t DMA17:1; /* Channel 17 DMA Enable */
6010  vuint32_t DMA16:1; /* Channel 16 DMA Enable */
6011  vuint32_t DMA15:1; /* Channel 15 DMA Enable */
6012  vuint32_t DMA14:1; /* Channel 14 DMA Enable */
6013  vuint32_t DMA13:1; /* Channel 13 DMA Enable */
6014  vuint32_t DMA12:1; /* Channel 12 DMA Enable */
6015  vuint32_t DMA11:1; /* Channel 11 DMA Enable */
6016  vuint32_t DMA10:1; /* Channel 10 DMA Enable */
6017  vuint32_t DMA9:1; /* Channel 9 DMA Enable */
6018  vuint32_t DMA8:1; /* Channel 8 DMA Enable */
6019  vuint32_t DMA7:1; /* Channel 7 DMA Enable */
6020  vuint32_t DMA6:1; /* Channel 6 DMA Enable */
6021  vuint32_t DMA5:1; /* Channel 5 DMA Enable */
6022  vuint32_t DMA4:1; /* Channel 4 DMA Enable */
6023  vuint32_t DMA3:1; /* Channel 3 DMA Enable */
6024  vuint32_t DMA2:1; /* Channel 2 DMA Enable */
6025  vuint32_t DMA1:1; /* Channel 1 DMA Enable */
6026  vuint32_t DMA0:1; /* Channel 0 DMA Enable */
6027  } B;
6028  } ADC_DMAR0_32B_tag;
6029 
6030  typedef union { /* DMA REGISTER 1 */
6031  vuint32_t R;
6032  struct {
6033  vuint32_t DMA63:1; /* Channel 63 DMA Enable */
6034  vuint32_t DMA62:1; /* Channel 62 DMA Enable */
6035  vuint32_t DMA61:1; /* Channel 61 DMA Enable */
6036  vuint32_t DMA60:1; /* Channel 60 DMA Enable */
6037  vuint32_t DMA59:1; /* Channel 59 DMA Enable */
6038  vuint32_t DMA58:1; /* Channel 58 DMA Enable */
6039  vuint32_t DMA57:1; /* Channel 57 DMA Enable */
6040  vuint32_t DMA56:1; /* Channel 56 DMA Enable */
6041  vuint32_t DMA55:1; /* Channel 55 DMA Enable */
6042  vuint32_t DMA54:1; /* Channel 54 DMA Enable */
6043  vuint32_t DMA53:1; /* Channel 53 DMA Enable */
6044  vuint32_t DMA52:1; /* Channel 52 DMA Enable */
6045  vuint32_t DMA51:1; /* Channel 51 DMA Enable */
6046  vuint32_t DMA50:1; /* Channel 50 DMA Enable */
6047  vuint32_t DMA49:1; /* Channel 49 DMA Enable */
6048  vuint32_t DMA48:1; /* Channel 48 DMA Enable */
6049  vuint32_t DMA47:1; /* Channel 47 DMA Enable */
6050  vuint32_t DMA46:1; /* Channel 46 DMA Enable */
6051  vuint32_t DMA45:1; /* Channel 45 DMA Enable */
6052  vuint32_t DMA44:1; /* Channel 44 DMA Enable */
6053  vuint32_t DMA43:1; /* Channel 43 DMA Enable */
6054  vuint32_t DMA42:1; /* Channel 42 DMA Enable */
6055  vuint32_t DMA41:1; /* Channel 41 DMA Enable */
6056  vuint32_t DMA40:1; /* Channel 40 DMA Enable */
6057  vuint32_t DMA39:1; /* Channel 39 DMA Enable */
6058  vuint32_t DMA38:1; /* Channel 38 DMA Enable */
6059  vuint32_t DMA37:1; /* Channel 37 DMA Enable */
6060  vuint32_t DMA36:1; /* Channel 36 DMA Enable */
6061  vuint32_t DMA35:1; /* Channel 35 DMA Enable */
6062  vuint32_t DMA34:1; /* Channel 34 DMA Enable */
6063  vuint32_t DMA33:1; /* Channel 33 DMA Enable */
6064  vuint32_t DMA32:1; /* Channel 32 DMA Enable */
6065  } B;
6066  } ADC_DMAR1_32B_tag;
6067 
6068  typedef union { /* DMA REGISTER 2 */
6069  vuint32_t R;
6070  struct {
6071  vuint32_t DMA95:1; /* Channel 95 DMA Enable */
6072  vuint32_t DMA94:1; /* Channel 94 DMA Enable */
6073  vuint32_t DMA93:1; /* Channel 93 DMA Enable */
6074  vuint32_t DMA92:1; /* Channel 92 DMA Enable */
6075  vuint32_t DMA91:1; /* Channel 91 DMA Enable */
6076  vuint32_t DMA90:1; /* Channel 90 DMA Enable */
6077  vuint32_t DMA89:1; /* Channel 89 DMA Enable */
6078  vuint32_t DMA88:1; /* Channel 88 DMA Enable */
6079  vuint32_t DMA87:1; /* Channel 87 DMA Enable */
6080  vuint32_t DMA86:1; /* Channel 86 DMA Enable */
6081  vuint32_t DMA85:1; /* Channel 85 DMA Enable */
6082  vuint32_t DMA84:1; /* Channel 84 DMA Enable */
6083  vuint32_t DMA83:1; /* Channel 83 DMA Enable */
6084  vuint32_t DMA82:1; /* Channel 82 DMA Enable */
6085  vuint32_t DMA81:1; /* Channel 81 DMA Enable */
6086  vuint32_t DMA80:1; /* Channel 80 DMA Enable */
6087  vuint32_t DMA79:1; /* Channel 79 DMA Enable */
6088  vuint32_t DMA78:1; /* Channel 78 DMA Enable */
6089  vuint32_t DMA77:1; /* Channel 77 DMA Enable */
6090  vuint32_t DMA76:1; /* Channel 76 DMA Enable */
6091  vuint32_t DMA75:1; /* Channel 75 DMA Enable */
6092  vuint32_t DMA74:1; /* Channel 74 DMA Enable */
6093  vuint32_t DMA73:1; /* Channel 73 DMA Enable */
6094  vuint32_t DMA72:1; /* Channel 72 DMA Enable */
6095  vuint32_t DMA71:1; /* Channel 71 DMA Enable */
6096  vuint32_t DMA70:1; /* Channel 70 DMA Enable */
6097  vuint32_t DMA69:1; /* Channel 69 DMA Enable */
6098  vuint32_t DMA68:1; /* Channel 68 DMA Enable */
6099  vuint32_t DMA67:1; /* Channel 67 DMA Enable */
6100  vuint32_t DMA66:1; /* Channel 66 DMA Enable */
6101  vuint32_t DMA65:1; /* Channel 65 DMA Enable */
6102  vuint32_t DMA64:1; /* Channel 64 DMA Enable */
6103  } B;
6104  } ADC_DMAR2_32B_tag;
6105 
6106 
6107  /* Register layout for all registers TRC... */
6108 
6109  typedef union { /* Threshold Control register C */
6110  vuint32_t R;
6111  struct {
6112  vuint32_t:16;
6113  vuint32_t THREN:1; /* Threshold enable */
6114  vuint32_t THRINV:1; /* invert the output pin */
6115  vuint32_t THROP:1; /* output pin register */
6116  vuint32_t:6;
6117  vuint32_t THRCH:7; /* Choose channel for threshold register */
6118  } B;
6119  } ADC_TRC_32B_tag;
6120 
6121 
6122  /* Register layout for all registers THRHLR... */
6123 
6124  typedef union { /* Upper Threshold register */
6125  vuint32_t R;
6126  struct {
6127  vuint32_t:4;
6128  vuint32_t THRH:12; /* high threshold value s */
6129  vuint32_t:4;
6130  vuint32_t THRL:12; /* low threshold value s */
6131  } B;
6132  } ADC_THRHLR_32B_tag;
6133 
6134 
6135  /* Register layout for all registers THRALT... */
6136 
6137  typedef union { /* alternate Upper Threshold register */
6138  vuint32_t R;
6139  struct {
6140  vuint32_t:6;
6141  vuint32_t THRH:10; /* high threshold value s */
6142  vuint32_t:6;
6143  vuint32_t THRL:10; /* low threshold value s */
6144  } B;
6145  } ADC_THRALT_32B_tag;
6146 
6147  typedef union { /* PRESAMPLING CONTROL REGISTER */
6148  vuint32_t R;
6149  struct {
6150  vuint32_t:25;
6151  vuint32_t PREVAL2:2; /* INternal Voltage selection for Presampling */
6152  vuint32_t PREVAL1:2; /* INternal Voltage selection for Presampling */
6153  vuint32_t PREVAL0:2; /* INternal Voltage selection for Presampling */
6154 #ifndef USE_FIELD_ALIASES_ADC
6155  vuint32_t PRECONV:1; /* Presampled value */
6156 #else
6157  vuint32_t PREONCE:1; /* deprecated name - please avoid */
6158 #endif
6159  } B;
6160  } ADC_PSCR_32B_tag;
6161 
6162  typedef union { /* Presampling Register 0 */
6163  vuint32_t R;
6164  struct {
6165  vuint32_t PRES31:1; /* Channel 31 Presampling Enable */
6166  vuint32_t PRES30:1; /* Channel 30 Presampling Enable */
6167  vuint32_t PRES29:1; /* Channel 29 Presampling Enable */
6168  vuint32_t PRES28:1; /* Channel 28 Presampling Enable */
6169  vuint32_t PRES27:1; /* Channel 27 Presampling Enable */
6170  vuint32_t PRES26:1; /* Channel 26 Presampling Enable */
6171  vuint32_t PRES25:1; /* Channel 25 Presampling Enable */
6172  vuint32_t PRES24:1; /* Channel 24 Presampling Enable */
6173  vuint32_t PRES23:1; /* Channel 23 Presampling Enable */
6174  vuint32_t PRES22:1; /* Channel 22 Presampling Enable */
6175  vuint32_t PRES21:1; /* Channel 21 Presampling Enable */
6176  vuint32_t PRES20:1; /* Channel 20 Presampling Enable */
6177  vuint32_t PRES19:1; /* Channel 19 Presampling Enable */
6178  vuint32_t PRES18:1; /* Channel 18 Presampling Enable */
6179  vuint32_t PRES17:1; /* Channel 17 Presampling Enable */
6180  vuint32_t PRES16:1; /* Channel 16 Presampling Enable */
6181  vuint32_t PRES15:1; /* Channel 15 Presampling Enable */
6182  vuint32_t PRES14:1; /* Channel 14 Presampling Enable */
6183  vuint32_t PRES13:1; /* Channel 13 Presampling Enable */
6184  vuint32_t PRES12:1; /* Channel 12 Presampling Enable */
6185  vuint32_t PRES11:1; /* Channel 11 Presampling Enable */
6186  vuint32_t PRES10:1; /* Channel 10 Presampling Enable */
6187  vuint32_t PRES9:1; /* Channel 9 Presampling Enable */
6188  vuint32_t PRES8:1; /* Channel 8 Presampling Enable */
6189  vuint32_t PRES7:1; /* Channel 7 Presampling Enable */
6190  vuint32_t PRES6:1; /* Channel 6 Presampling Enable */
6191  vuint32_t PRES5:1; /* Channel 5 Presampling Enable */
6192  vuint32_t PRES4:1; /* Channel 4 Presampling Enable */
6193  vuint32_t PRES3:1; /* Channel 3 Presampling Enable */
6194  vuint32_t PRES2:1; /* Channel 2 Presampling Enable */
6195  vuint32_t PRES1:1; /* Channel 1presampling Enable */
6196  vuint32_t PRES0:1; /* Channel 0 Presampling Enable */
6197  } B;
6198  } ADC_PSR0_32B_tag;
6199 
6200  typedef union { /* Presampling REGISTER 1 */
6201  vuint32_t R;
6202  struct {
6203  vuint32_t PRES63:1; /* Channel 63 Presampling Enable */
6204  vuint32_t PRES62:1; /* Channel 62 Presampling Enable */
6205  vuint32_t PRES61:1; /* Channel 61 Presampling Enable */
6206  vuint32_t PRES60:1; /* Channel 60 Presampling Enable */
6207  vuint32_t PRES59:1; /* Channel 59 Presampling Enable */
6208  vuint32_t PRES58:1; /* Channel 58 Presampling Enable */
6209  vuint32_t PRES57:1; /* Channel 57 Presampling Enable */
6210  vuint32_t PRES56:1; /* Channel 56 Presampling Enable */
6211  vuint32_t PRES55:1; /* Channel 55 Presampling Enable */
6212  vuint32_t PRES54:1; /* Channel 54 Presampling Enable */
6213  vuint32_t PRES53:1; /* Channel 53 Presampling Enable */
6214  vuint32_t PRES52:1; /* Channel 52 Presampling Enable */
6215  vuint32_t PRES51:1; /* Channel 51 Presampling Enable */
6216  vuint32_t PRES50:1; /* Channel 50 Presampling Enable */
6217  vuint32_t PRES49:1; /* Channel 49 Presampling Enable */
6218  vuint32_t PRES48:1; /* Channel 48 Presampling Enable */
6219  vuint32_t PRES47:1; /* Channel 47 Presampling Enable */
6220  vuint32_t PRES46:1; /* Channel 46 Presampling Enable */
6221  vuint32_t PRES45:1; /* Channel 45 Presampling Enable */
6222  vuint32_t PRES44:1; /* Channel 44 Presampling Enable */
6223  vuint32_t PRES43:1; /* Channel 43 Presampling Enable */
6224  vuint32_t PRES42:1; /* Channel 42 Presampling Enable */
6225  vuint32_t PRES41:1; /* Channel 41 Presampling Enable */
6226  vuint32_t PRES40:1; /* Channel 40 Presampling Enable */
6227  vuint32_t PRES39:1; /* Channel 39 Presampling Enable */
6228  vuint32_t PRES38:1; /* Channel 38 Presampling Enable */
6229  vuint32_t PRES37:1; /* Channel 37 Presampling Enable */
6230  vuint32_t PRES36:1; /* Channel 36 Presampling Enable */
6231  vuint32_t PRES35:1; /* Channel 35 Presampling Enable */
6232  vuint32_t PRES34:1; /* Channel 34 Presampling Enable */
6233  vuint32_t PRES33:1; /* Channel 33 Presampling Enable */
6234  vuint32_t PRES32:1; /* Channel 32 Presampling Enable */
6235  } B;
6236  } ADC_PSR1_32B_tag;
6237 
6238  typedef union { /* Presampling REGISTER 2 */
6239  vuint32_t R;
6240  struct {
6241  vuint32_t PRES95:1; /* Channel 95 Presampling Enable */
6242  vuint32_t PRES94:1; /* Channel 94 Presampling Enable */
6243  vuint32_t PRES93:1; /* Channel 93 Presampling Enable */
6244  vuint32_t PRES92:1; /* Channel 92 Presampling Enable */
6245  vuint32_t PRES91:1; /* Channel 91 Presampling Enable */
6246  vuint32_t PRES90:1; /* Channel 90 Presampling Enable */
6247  vuint32_t PRES89:1; /* Channel 89 Presampling Enable */
6248  vuint32_t PRES88:1; /* Channel 88 Presampling Enable */
6249  vuint32_t PRES87:1; /* Channel 87 Presampling Enable */
6250  vuint32_t PRES86:1; /* Channel 86 Presampling Enable */
6251  vuint32_t PRES85:1; /* Channel 85 Presampling Enable */
6252  vuint32_t PRES84:1; /* Channel 84 Presampling Enable */
6253  vuint32_t PRES83:1; /* Channel 83 Presampling Enable */
6254  vuint32_t PRES82:1; /* Channel 82 Presampling Enable */
6255  vuint32_t PRES81:1; /* Channel 81 Presampling Enable */
6256  vuint32_t PRES80:1; /* Channel 80 Presampling Enable */
6257  vuint32_t PRES79:1; /* Channel 79 Presampling Enable */
6258  vuint32_t PRES78:1; /* Channel 78 Presampling Enable */
6259  vuint32_t PRES77:1; /* Channel 77 Presampling Enable */
6260  vuint32_t PRES76:1; /* Channel 76 Presampling Enable */
6261  vuint32_t PRES75:1; /* Channel 75 Presampling Enable */
6262  vuint32_t PRES74:1; /* Channel 74 Presampling Enable */
6263  vuint32_t PRES73:1; /* Channel 73 Presampling Enable */
6264  vuint32_t PRES72:1; /* Channel 72 Presampling Enable */
6265  vuint32_t PRES71:1; /* Channel 71 Presampling Enable */
6266  vuint32_t PRES70:1; /* Channel 70 Presampling Enable */
6267  vuint32_t PRES69:1; /* Channel 69 Presampling Enable */
6268  vuint32_t PRES68:1; /* Channel 68 Presampling Enable */
6269  vuint32_t PRES67:1; /* Channel 67 Presampling Enable */
6270  vuint32_t PRES66:1; /* Channel 66 Presampling Enable */
6271  vuint32_t PRES65:1; /* Channel 65 Presampling Enable */
6272  vuint32_t PRES64:1; /* Channel 64 Presampling Enable */
6273  } B;
6274  } ADC_PSR2_32B_tag;
6275 
6276 
6277  /* Register layout for all registers CTR... */
6278 
6279  typedef union { /* conversion timing register */
6280  vuint32_t R;
6281  struct {
6282  vuint32_t:16;
6283  vuint32_t INPLATCH:1; /* configuration bits for the LATCHING PHASE duration */
6284  vuint32_t:1;
6285  vuint32_t OFFSHIFT:2; /* configuration for offset shift characteristics */
6286  vuint32_t:1;
6287  vuint32_t INPCMP:2; /* configuration bits for the COMPARISON duration */
6288  vuint32_t:1;
6289 #ifndef USE_FIELD_ALIASES_ADC
6290  vuint32_t INSAMP:8; /* configuration bits for the SAMPLING PHASE duration */
6291 #else
6292  vuint32_t INPSAMP:8;
6293 #endif
6294  } B;
6295  } ADC_CTR_32B_tag;
6296 
6297  typedef union { /* NORMAL CONVERSION MASK REGISTER 0 */
6298  vuint32_t R;
6299  struct {
6300  vuint32_t CH31:1; /* Channel 31 Normal Sampling Enable */
6301  vuint32_t CH30:1; /* Channel 30 Normal Sampling Enable */
6302  vuint32_t CH29:1; /* Channel 29 Normal Sampling Enable */
6303  vuint32_t CH28:1; /* Channel 28 Normal Sampling Enable */
6304  vuint32_t CH27:1; /* Channel 27 Normal Sampling Enable */
6305  vuint32_t CH26:1; /* Channel 26 Normal Sampling Enable */
6306  vuint32_t CH25:1; /* Channel 25 Normal Sampling Enable */
6307  vuint32_t CH24:1; /* Channel 24 Normal Sampling Enable */
6308  vuint32_t CH23:1; /* Channel 23 Normal Sampling Enable */
6309  vuint32_t CH22:1; /* Channel 22 Normal Sampling Enable */
6310  vuint32_t CH21:1; /* Channel 21 Normal Sampling Enable */
6311  vuint32_t CH20:1; /* Channel 20 Normal Sampling Enable */
6312  vuint32_t CH19:1; /* Channel 19 Normal Sampling Enable */
6313  vuint32_t CH18:1; /* Channel 18 Normal Sampling Enable */
6314  vuint32_t CH17:1; /* Channel 17 Normal Sampling Enable */
6315  vuint32_t CH16:1; /* Channel 16 Normal Sampling Enable */
6316  vuint32_t CH15:1; /* Channel 15 Normal Sampling Enable */
6317  vuint32_t CH14:1; /* Channel 14 Normal Sampling Enable */
6318  vuint32_t CH13:1; /* Channel 13 Normal Sampling Enable */
6319  vuint32_t CH12:1; /* Channel 12 Normal Sampling Enable */
6320  vuint32_t CH11:1; /* Channel 11 Normal Sampling Enable */
6321  vuint32_t CH10:1; /* Channel 10 Normal Sampling Enable */
6322  vuint32_t CH9:1; /* Channel 9 Normal Sampling Enable */
6323  vuint32_t CH8:1; /* Channel 8 Normal Sampling Enable */
6324  vuint32_t CH7:1; /* Channel 7 Normal Sampling Enable */
6325  vuint32_t CH6:1; /* Channel 6 Normal Sampling Enable */
6326  vuint32_t CH5:1; /* Channel 5 Normal Sampling Enable */
6327  vuint32_t CH4:1; /* Channel 4 Normal Sampling Enable */
6328  vuint32_t CH3:1; /* Channel 3 Normal Sampling Enable */
6329  vuint32_t CH2:1; /* Channel 2 Normal Sampling Enable */
6330  vuint32_t CH1:1; /* Channel 1 Normal Sampling Enable */
6331  vuint32_t CH0:1; /* Channel 0 Normal Sampling Enable */
6332  } B;
6333  } ADC_NCMR0_32B_tag;
6334 
6335  typedef union { /* NORMAL CONVERSION MASK REGISTER 1 */
6336  vuint32_t R;
6337  struct {
6338  vuint32_t CH63:1; /* Channel 63 Normal Sampling Enable */
6339  vuint32_t CH62:1; /* Channel 62 Normal Sampling Enable */
6340  vuint32_t CH61:1; /* Channel 61 Normal Sampling Enable */
6341  vuint32_t CH60:1; /* Channel 60 Normal Sampling Enable */
6342  vuint32_t CH59:1; /* Channel 59 Normal Sampling Enable */
6343  vuint32_t CH58:1; /* Channel 58 Normal Sampling Enable */
6344  vuint32_t CH57:1; /* Channel 57 Normal Sampling Enable */
6345  vuint32_t CH56:1; /* Channel 56 Normal Sampling Enable */
6346  vuint32_t CH55:1; /* Channel 55 Normal Sampling Enable */
6347  vuint32_t CH54:1; /* Channel 54 Normal Sampling Enable */
6348  vuint32_t CH53:1; /* Channel 53 Normal Sampling Enable */
6349  vuint32_t CH52:1; /* Channel 52 Normal Sampling Enable */
6350  vuint32_t CH51:1; /* Channel 51 Normal Sampling Enable */
6351  vuint32_t CH50:1; /* Channel 50 Normal Sampling Enable */
6352  vuint32_t CH49:1; /* Channel 49 Normal Sampling Enable */
6353  vuint32_t CH48:1; /* Channel 48 Normal Sampling Enable */
6354  vuint32_t CH47:1; /* Channel 47 Normal Sampling Enable */
6355  vuint32_t CH46:1; /* Channel 46 Normal Sampling Enable */
6356  vuint32_t CH45:1; /* Channel 45 Normal Sampling Enable */
6357  vuint32_t CH44:1; /* Channel 44 Normal Sampling Enable */
6358  vuint32_t CH43:1; /* Channel 43 Normal Sampling Enable */
6359  vuint32_t CH42:1; /* Channel 42 Normal Sampling Enable */
6360  vuint32_t CH41:1; /* Channel 41 Normal Sampling Enable */
6361  vuint32_t CH40:1; /* Channel 40 Normal Sampling Enable */
6362  vuint32_t CH39:1; /* Channel 39 Normal Sampling Enable */
6363  vuint32_t CH38:1; /* Channel 38 Normal Sampling Enable */
6364  vuint32_t CH37:1; /* Channel 37 Normal Sampling Enable */
6365  vuint32_t CH36:1; /* Channel 36 Normal Sampling Enable */
6366  vuint32_t CH35:1; /* Channel 35 Normal Sampling Enable */
6367  vuint32_t CH34:1; /* Channel 34 Normal Sampling Enable */
6368  vuint32_t CH33:1; /* Channel 33 Normal Sampling Enable */
6369  vuint32_t CH32:1; /* Channel 32 Normal Sampling Enable */
6370  } B;
6371  } ADC_NCMR1_32B_tag;
6372 
6373  typedef union { /* NORMAL CONVERSION MASK REGISTER 2 */
6374  vuint32_t R;
6375  struct {
6376  vuint32_t CH95:1; /* Channel 95 Normal Sampling Enable */
6377  vuint32_t CH94:1; /* Channel 94 Normal Sampling Enable */
6378  vuint32_t CH93:1; /* Channel 93 Normal Sampling Enable */
6379  vuint32_t CH92:1; /* Channel 92 Normal Sampling Enable */
6380  vuint32_t CH91:1; /* Channel 91 Normal Sampling Enable */
6381  vuint32_t CH90:1; /* Channel 90 Normal Sampling Enable */
6382  vuint32_t CH89:1; /* Channel 89 Normal Sampling Enable */
6383  vuint32_t CH88:1; /* Channel 88 Normal Sampling Enable */
6384  vuint32_t CH87:1; /* Channel 87 Normal Sampling Enable */
6385  vuint32_t CH86:1; /* Channel 86 Normal Sampling Enable */
6386  vuint32_t CH85:1; /* Channel 85 Normal Sampling Enable */
6387  vuint32_t CH84:1; /* Channel 84 Normal Sampling Enable */
6388  vuint32_t CH83:1; /* Channel 83 Normal Sampling Enable */
6389  vuint32_t CH82:1; /* Channel 82 Normal Sampling Enable */
6390  vuint32_t CH81:1; /* Channel 81 Normal Sampling Enable */
6391  vuint32_t CH80:1; /* Channel 80 Normal Sampling Enable */
6392  vuint32_t CH79:1; /* Channel 79 Normal Sampling Enable */
6393  vuint32_t CH78:1; /* Channel 78 Normal Sampling Enable */
6394  vuint32_t CH77:1; /* Channel 77 Normal Sampling Enable */
6395  vuint32_t CH76:1; /* Channel 76 Normal Sampling Enable */
6396  vuint32_t CH75:1; /* Channel 75 Normal Sampling Enable */
6397  vuint32_t CH74:1; /* Channel 74 Normal Sampling Enable */
6398  vuint32_t CH73:1; /* Channel 73 Normal Sampling Enable */
6399  vuint32_t CH72:1; /* Channel 72 Normal Sampling Enable */
6400  vuint32_t CH71:1; /* Channel 71 Normal Sampling Enable */
6401  vuint32_t CH70:1; /* Channel 70 Normal Sampling Enable */
6402  vuint32_t CH69:1; /* Channel 69 Normal Sampling Enable */
6403  vuint32_t CH68:1; /* Channel 68 Normal Sampling Enable */
6404  vuint32_t CH67:1; /* Channel 67 Normal Sampling Enable */
6405  vuint32_t CH66:1; /* Channel 66 Normal Sampling Enable */
6406  vuint32_t CH65:1; /* Channel 65 Normal Sampling Enable */
6407  vuint32_t CH64:1; /* Channel 64 Normal Sampling Enable */
6408  } B;
6409  } ADC_NCMR2_32B_tag;
6410 
6411  typedef union { /* Injected Conversion Mask Register 0 */
6412  vuint32_t R;
6413  struct {
6414  vuint32_t CH31:1; /* Channel 31 Injected Sampling Enable */
6415  vuint32_t CH30:1; /* Channel 30 Injected Sampling Enable */
6416  vuint32_t CH29:1; /* Channel 29 Injected Sampling Enable */
6417  vuint32_t CH28:1; /* Channel 28 Injected Sampling Enable */
6418  vuint32_t CH27:1; /* Channel 27 Injected Sampling Enable */
6419  vuint32_t CH26:1; /* Channel 26 Injected Sampling Enable */
6420  vuint32_t CH25:1; /* Channel 25 Injected Sampling Enable */
6421  vuint32_t CH24:1; /* Channel 24 Injected Sampling Enable */
6422  vuint32_t CH23:1; /* Channel 23 Injected Sampling Enable */
6423  vuint32_t CH22:1; /* Channel 22 Injected Sampling Enable */
6424  vuint32_t CH21:1; /* Channel 21 Injected Sampling Enable */
6425  vuint32_t CH20:1; /* Channel 20 Injected Sampling Enable */
6426  vuint32_t CH19:1; /* Channel 19 Injected Sampling Enable */
6427  vuint32_t CH18:1; /* Channel 18 Injected Sampling Enable */
6428  vuint32_t CH17:1; /* Channel 17 Injected Sampling Enable */
6429  vuint32_t CH16:1; /* Channel 16 Injected Sampling Enable */
6430  vuint32_t CH15:1; /* Channel 15 Injected Sampling Enable */
6431  vuint32_t CH14:1; /* Channel 14 Injected Sampling Enable */
6432  vuint32_t CH13:1; /* Channel 13 Injected Sampling Enable */
6433  vuint32_t CH12:1; /* Channel 12 Injected Sampling Enable */
6434  vuint32_t CH11:1; /* Channel 11 Injected Sampling Enable */
6435  vuint32_t CH10:1; /* Channel 10 Injected Sampling Enable */
6436  vuint32_t CH9:1; /* Channel 9 Injected Sampling Enable */
6437  vuint32_t CH8:1; /* Channel 8 Injected Sampling Enable */
6438  vuint32_t CH7:1; /* Channel 7 Injected Sampling Enable */
6439  vuint32_t CH6:1; /* Channel 6 Injected Sampling Enable */
6440  vuint32_t CH5:1; /* Channel 5 Injected Sampling Enable */
6441  vuint32_t CH4:1; /* Channel 4 Injected Sampling Enable */
6442  vuint32_t CH3:1; /* Channel 3 Injected Sampling Enable */
6443  vuint32_t CH2:1; /* Channel 2 Injected Sampling Enable */
6444  vuint32_t CH1:1; /* Channel 1 injected Sampling Enable */
6445  vuint32_t CH0:1; /* Channel 0 injected Sampling Enable */
6446  } B;
6447  } ADC_JCMR0_32B_tag;
6448 
6449  typedef union { /* INJECTED CONVERSION MASK REGISTER 1 */
6450  vuint32_t R;
6451  struct {
6452  vuint32_t CH63:1; /* Channel 63 Injected Sampling Enable */
6453  vuint32_t CH62:1; /* Channel 62 Injected Sampling Enable */
6454  vuint32_t CH61:1; /* Channel 61 Injected Sampling Enable */
6455  vuint32_t CH60:1; /* Channel 60 Injected Sampling Enable */
6456  vuint32_t CH59:1; /* Channel 59 Injected Sampling Enable */
6457  vuint32_t CH58:1; /* Channel 58 Injected Sampling Enable */
6458  vuint32_t CH57:1; /* Channel 57 Injected Sampling Enable */
6459  vuint32_t CH56:1; /* Channel 56 Injected Sampling Enable */
6460  vuint32_t CH55:1; /* Channel 55 Injected Sampling Enable */
6461  vuint32_t CH54:1; /* Channel 54 Injected Sampling Enable */
6462  vuint32_t CH53:1; /* Channel 53 Injected Sampling Enable */
6463  vuint32_t CH52:1; /* Channel 52 Injected Sampling Enable */
6464  vuint32_t CH51:1; /* Channel 51 Injected Sampling Enable */
6465  vuint32_t CH50:1; /* Channel 50 Injected Sampling Enable */
6466  vuint32_t CH49:1; /* Channel 49 Injected Sampling Enable */
6467  vuint32_t CH48:1; /* Channel 48 Injected Sampling Enable */
6468  vuint32_t CH47:1; /* Channel 47 Injected Sampling Enable */
6469  vuint32_t CH46:1; /* Channel 46 Injected Sampling Enable */
6470  vuint32_t CH45:1; /* Channel 45 Injected Sampling Enable */
6471  vuint32_t CH44:1; /* Channel 44 Injected Sampling Enable */
6472  vuint32_t CH43:1; /* Channel 43 Injected Sampling Enable */
6473  vuint32_t CH42:1; /* Channel 42 Injected Sampling Enable */
6474  vuint32_t CH41:1; /* Channel 41 Injected Sampling Enable */
6475  vuint32_t CH40:1; /* Channel 40 Injected Sampling Enable */
6476  vuint32_t CH39:1; /* Channel 39 Injected Sampling Enable */
6477  vuint32_t CH38:1; /* Channel 38 Injected Sampling Enable */
6478  vuint32_t CH37:1; /* Channel 37 Injected Sampling Enable */
6479  vuint32_t CH36:1; /* Channel 36 Injected Sampling Enable */
6480  vuint32_t CH35:1; /* Channel 35 Injected Sampling Enable */
6481  vuint32_t CH34:1; /* Channel 34 Injected Sampling Enable */
6482  vuint32_t CH33:1; /* Channel 33 Injected Sampling Enable */
6483  vuint32_t CH32:1; /* Channel 32 Injected Sampling Enable */
6484  } B;
6485  } ADC_JCMR1_32B_tag;
6486 
6487  typedef union { /* INJECTED CONVERSION MASK REGISTER 2 */
6488  vuint32_t R;
6489  struct {
6490  vuint32_t CH95:1; /* Channel 95 Injected Sampling Enable */
6491  vuint32_t CH94:1; /* Channel 94 Injected Sampling Enable */
6492  vuint32_t CH93:1; /* Channel 93 Injected Sampling Enable */
6493  vuint32_t CH92:1; /* Channel 92 Injected Sampling Enable */
6494  vuint32_t CH91:1; /* Channel 91 Injected Sampling Enable */
6495  vuint32_t CH90:1; /* Channel 90 Injected Sampling Enable */
6496  vuint32_t CH89:1; /* Channel 89 Injected Sampling Enable */
6497  vuint32_t CH88:1; /* Channel 88 Injected Sampling Enable */
6498  vuint32_t CH87:1; /* Channel 87 Injected Sampling Enable */
6499  vuint32_t CH86:1; /* Channel 86 Injected Sampling Enable */
6500  vuint32_t CH85:1; /* Channel 85 Injected Sampling Enable */
6501  vuint32_t CH84:1; /* Channel 84 Injected Sampling Enable */
6502  vuint32_t CH83:1; /* Channel 83 Injected Sampling Enable */
6503  vuint32_t CH82:1; /* Channel 82 Injected Sampling Enable */
6504  vuint32_t CH81:1; /* Channel 81 Injected Sampling Enable */
6505  vuint32_t CH80:1; /* Channel 80 Injected Sampling Enable */
6506  vuint32_t CH79:1; /* Channel 79 Injected Sampling Enable */
6507  vuint32_t CH78:1; /* Channel 78 Injected Sampling Enable */
6508  vuint32_t CH77:1; /* Channel 77 Injected Sampling Enable */
6509  vuint32_t CH76:1; /* Channel 76 Injected Sampling Enable */
6510  vuint32_t CH75:1; /* Channel 75 Injected Sampling Enable */
6511  vuint32_t CH74:1; /* Channel 74 Injected Sampling Enable */
6512  vuint32_t CH73:1; /* Channel 73 Injected Sampling Enable */
6513  vuint32_t CH72:1; /* Channel 72 Injected Sampling Enable */
6514  vuint32_t CH71:1; /* Channel 71 Injected Sampling Enable */
6515  vuint32_t CH70:1; /* Channel 70 Injected Sampling Enable */
6516  vuint32_t CH69:1; /* Channel 69 Injected Sampling Enable */
6517  vuint32_t CH68:1; /* Channel 68 Injected Sampling Enable */
6518  vuint32_t CH67:1; /* Channel 67 Injected Sampling Enable */
6519  vuint32_t CH66:1; /* Channel 66 Injected Sampling Enable */
6520  vuint32_t CH65:1; /* Channel 65 Injected Sampling Enable */
6521  vuint32_t CH64:1; /* Channel 64 Injected Sampling Enable */
6522  } B;
6523  } ADC_JCMR2_32B_tag;
6524 
6525  typedef union { /* Offset Word Regsiter */
6526  vuint32_t R;
6527  struct {
6528  vuint32_t:15;
6529  vuint32_t OFFSETLOAD:1; /* load_offset */
6530  vuint32_t:8;
6531 #ifndef USE_FIELD_ALIASES_ADC
6532  vuint32_t OFFSET_WORD:8; /* OFFSET word coeff.generated at the end of offset cancellation is lathed int o this register */
6533 #else
6534  vuint32_t OFFSETWORD:8;
6535 #endif
6536  } B;
6537  } ADC_OFFWR_32B_tag;
6538 
6539  typedef union { /* Decode Signal Delay Register */
6540  vuint32_t R;
6541  struct {
6542  vuint32_t:24;
6543  vuint32_t DSD:8; /* take into account the settling time of the external mux */
6544  } B;
6545  } ADC_DSDR_32B_tag;
6546 
6547  typedef union { /* Power Down Dealy Register */
6548  vuint32_t R;
6549  struct {
6550  vuint32_t:24;
6551  vuint32_t PDED:8; /* The delay between the power down bit reset and the starting of conversion */
6552  } B;
6553  } ADC_PDEDR_32B_tag;
6554 
6555 
6556  /* Register layout for all registers CDR... */
6557 
6558  typedef union { /* CHANNEL DATA REGS */
6559  vuint32_t R;
6560  struct {
6561  vuint32_t:12;
6562  vuint32_t VALID:1; /* validity of data */
6563  vuint32_t OVERW:1; /* overwrite data */
6564  vuint32_t RESULT:2; /* reflects mode conversion */
6565  vuint32_t:6;
6566  vuint32_t CDATA:10; /* Channel 0 converted data */
6567  } B;
6568  } ADC_CDR_32B_tag;
6569 
6570  typedef union { /* Upper Threshold register 4 is not contiguous to 3 */
6571  vuint32_t R;
6572  struct {
6573  vuint32_t:4;
6574  vuint32_t THRH:12; /* high threshold value s */
6575  vuint32_t:4;
6576  vuint32_t THRL:12; /* low threshold value s */
6577  } B;
6578  } ADC_THRHLR4_32B_tag;
6579 
6580  typedef union { /* Upper Threshold register 5 */
6581  vuint32_t R;
6582  struct {
6583  vuint32_t:4;
6584  vuint32_t THRH:12; /* high threshold value s */
6585  vuint32_t:4;
6586  vuint32_t THRL:12; /* low threshold value s */
6587  } B;
6588  } ADC_THRHLR5_32B_tag;
6589 
6590  typedef union { /* Upper Threshold register 6 */
6591  vuint32_t R;
6592  struct {
6593  vuint32_t:4;
6594  vuint32_t THRH:12; /* high threshold value s */
6595  vuint32_t:4;
6596  vuint32_t THRL:12; /* low threshold value s */
6597  } B;
6598  } ADC_THRHLR6_32B_tag;
6599 
6600  typedef union { /* Upper Threshold register 7 */
6601  vuint32_t R;
6602  struct {
6603  vuint32_t:4;
6604  vuint32_t THRH:12; /* high threshold value s */
6605  vuint32_t:4;
6606  vuint32_t THRL:12; /* low threshold value s */
6607  } B;
6608  } ADC_THRHLR7_32B_tag;
6609 
6610  typedef union { /* Upper Threshold register 8 */
6611  vuint32_t R;
6612  struct {
6613  vuint32_t:4;
6614  vuint32_t THRH:12; /* high threshold value s */
6615  vuint32_t:4;
6616  vuint32_t THRL:12; /* low threshold value s */
6617  } B;
6618  } ADC_THRHLR8_32B_tag;
6619 
6620  typedef union { /* Upper Threshold register 9 */
6621  vuint32_t R;
6622  struct {
6623  vuint32_t:4;
6624  vuint32_t THRH:12; /* high threshold value s */
6625  vuint32_t:4;
6626  vuint32_t THRL:12; /* low threshold value s */
6627  } B;
6628  } ADC_THRHLR9_32B_tag;
6629 
6630  typedef union { /* Upper Threshold register 10 */
6631  vuint32_t R;
6632  struct {
6633  vuint32_t:4;
6634  vuint32_t THRH:12; /* high threshold value s */
6635  vuint32_t:4;
6636  vuint32_t THRL:12; /* low threshold value s */
6637  } B;
6638  } ADC_THRHLR10_32B_tag;
6639 
6640  typedef union { /* Upper Threshold register 11 */
6641  vuint32_t R;
6642  struct {
6643  vuint32_t:4;
6644  vuint32_t THRH:12; /* high threshold value s */
6645  vuint32_t:4;
6646  vuint32_t THRL:12; /* low threshold value s */
6647  } B;
6648  } ADC_THRHLR11_32B_tag;
6649 
6650  typedef union { /* Upper Threshold register 12 */
6651  vuint32_t R;
6652  struct {
6653  vuint32_t:4;
6654  vuint32_t THRH:12; /* high threshold value s */
6655  vuint32_t:4;
6656  vuint32_t THRL:12; /* low threshold value s */
6657  } B;
6658  } ADC_THRHLR12_32B_tag;
6659 
6660  typedef union { /* Upper Threshold register 13 */
6661  vuint32_t R;
6662  struct {
6663  vuint32_t:4;
6664  vuint32_t THRH:12; /* high threshold value s */
6665  vuint32_t:4;
6666  vuint32_t THRL:12; /* low threshold value s */
6667  } B;
6668  } ADC_THRHLR13_32B_tag;
6669 
6670  typedef union { /* Upper Threshold register 14 */
6671  vuint32_t R;
6672  struct {
6673  vuint32_t:4;
6674  vuint32_t THRH:12; /* high threshold value s */
6675  vuint32_t:4;
6676  vuint32_t THRL:12; /* low threshold value s */
6677  } B;
6678  } ADC_THRHLR14_32B_tag;
6679 
6680  typedef union { /* Upper Threshold register 15 */
6681  vuint32_t R;
6682  struct {
6683  vuint32_t:4;
6684  vuint32_t THRH:12; /* high threshold value s */
6685  vuint32_t:4;
6686  vuint32_t THRL:12; /* low threshold value s */
6687  } B;
6688  } ADC_THRHLR15_32B_tag;
6689 
6690 
6691  /* Register layout for all registers CWSELR... */
6692 
6693  typedef union { /* Channel Watchdog Select register */
6694  vuint32_t R;
6695  struct {
6696  vuint32_t WSEL_CH7:4; /* Channel Watchdog select for channel 7+R*8 */
6697  vuint32_t WSEL_CH6:4; /* Channel Watchdog select for channel 6+R*8 */
6698  vuint32_t WSEL_CH5:4; /* Channel Watchdog select for channel 5+R*8 */
6699  vuint32_t WSEL_CH4:4; /* Channel Watchdog select for channel 4+R*8 */
6700  vuint32_t WSEL_CH3:4; /* Channel Watchdog select for channel 3+R*8 */
6701  vuint32_t WSEL_CH2:4; /* Channel Watchdog select for channel 2+R*8 */
6702  vuint32_t WSEL_CH1:4; /* Channel Watchdog select for channel 1+R*8 */
6703  vuint32_t WSEL_CH0:4; /* Channel Watchdog select for channel 0+R*8 */
6704  } B;
6705  } ADC_CWSELR_32B_tag;
6706 
6707 
6708  /* Register layout for all registers CWENR... */
6709 
6710  typedef union { /* Channel Watchdog Enable Register */
6711  vuint32_t R;
6712  struct {
6713  vuint32_t:16;
6714  vuint32_t CWEN15PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6715  vuint32_t CWEN14PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6716  vuint32_t CWEN13PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6717  vuint32_t CWEN12PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6718  vuint32_t CWEN11PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6719  vuint32_t CWEN10PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6720  vuint32_t CWEN09PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6721  vuint32_t CWEN08PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6722  vuint32_t CWEN07PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6723  vuint32_t CWEN06PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6724  vuint32_t CWEN05PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6725  vuint32_t CWEN04PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6726  vuint32_t CWEN03PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6727  vuint32_t CWEN02PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6728  vuint32_t CWEN01PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6729  vuint32_t CWEN00PRT32:1; /* Channel Watchdog Enable 0+R*32 */
6730  } B;
6731  } ADC_CWENR_32B_tag;
6732 
6733 
6734  /* Register layout for all registers AWORR... */
6735 
6736  typedef union { /* Analog Watchdog Out of Range Register */
6737  vuint32_t R;
6738  struct {
6739  vuint32_t AWOR_CH31:1; /* Channel 31+R*32 converted data out of range */
6740  vuint32_t AWOR_CH30:1; /* Channel 30+R*32 converted data out of range */
6741  vuint32_t AWOR_CH29:1; /* Channel 29+R*32 converted data out of range */
6742  vuint32_t AWOR_CH28:1; /* Channel 28+R*32 converted data out of range */
6743  vuint32_t AWOR_CH27:1; /* Channel 27+R*32 converted data out of range */
6744  vuint32_t AWOR_CH26:1; /* Channel 26+R*32 converted data out of range */
6745  vuint32_t AWOR_CH25:1; /* Channel 25+R*32 converted data out of range */
6746  vuint32_t AWOR_CH24:1; /* Channel 24+R*32 converted data out of range */
6747  vuint32_t AWOR_CH23:1; /* Channel 23+R*32 converted data out of range */
6748  vuint32_t AWOR_CH22:1; /* Channel 22+R*32 converted data out of range */
6749  vuint32_t AWOR_CH21:1; /* Channel 21+R*32 converted data out of range */
6750  vuint32_t AWOR_CH20:1; /* Channel 20+R*32 converted data out of range */
6751  vuint32_t AWOR_CH19:1; /* Channel 19+R*32 converted data out of range */
6752  vuint32_t AWOR_CH18:1; /* Channel 18+R*32 converted data out of range */
6753  vuint32_t AWOR_CH17:1; /* Channel 17+R*32 converted data out of range */
6754  vuint32_t AWOR_CH16:1; /* Channel 16+R*32 converted data out of range */
6755  vuint32_t AWOR_CH15:1; /* Channel 15+R*32 converted data out of range */
6756  vuint32_t AWOR_CH14:1; /* Channel 14+R*32 converted data out of range */
6757  vuint32_t AWOR_CH13:1; /* Channel 13+R*32 converted data out of range */
6758  vuint32_t AWOR_CH12:1; /* Channel 12+R*32 converted data out of range */
6759  vuint32_t AWOR_CH11:1; /* Channel 11+R*32 converted data out of range */
6760  vuint32_t AWOR_CH10:1; /* Channel 10+R*32 converted data out of range */
6761  vuint32_t AWOR_CH9:1; /* Channel 9+R*32 converted data out of range */
6762  vuint32_t AWOR_CH8:1; /* Channel 8+R*32 converted data out of range */
6763  vuint32_t AWOR_CH7:1; /* Channel 7+R*32 converted data out of range */
6764  vuint32_t AWOR_CH6:1; /* Channel 6+R*32 converted data out of range */
6765  vuint32_t AWOR_CH5:1; /* Channel 5+R*32 converted data out of range */
6766  vuint32_t AWOR_CH4:1; /* Channel 4+R*32 converted data out of range */
6767  vuint32_t AWOR_CH3:1; /* Channel 3+R*32 converted data out of range */
6768  vuint32_t AWOR_CH2:1; /* Channel 2+R*32 converted data out of range */
6769  vuint32_t AWOR_CH1:1; /* Channel 1+R*32 converted data out of range */
6770  vuint32_t AWOR_CH0:1; /* Channel 0+R*32 converted data out of range */
6771  } B;
6772  } ADC_AWORR_32B_tag;
6773 
6774  typedef union { /* SELF TEST CONFIGURATION REGISTER 1 */
6775  vuint32_t R;
6776  struct {
6777  vuint32_t INPSAMP_C:8; /* Sampling phase duration for the test conversions - algorithm C */
6778  vuint32_t INPSAMP_RC:8; /* Sampling phase duration for the test conversions - algorithm RC */
6779  vuint32_t INPSAMP_S:8; /* Sampling phase duration for the test conversions - algorithm S */
6780  vuint32_t:5;
6781  vuint32_t ST_INPCMP:2; /* Configuration bit for comparison phase duration for self test channel */
6782  vuint32_t ST_INPLATCH:1; /* Configuration bit for Latching phase duration for self test channel */
6783  } B;
6784  } ADC_STCR1_32B_tag;
6785 
6786  typedef union { /* SELF TEST CONFIGURATION REGISTER 2 */
6787  vuint32_t R;
6788  struct {
6789  vuint32_t:5;
6790  vuint32_t SERR:1; /* Error fault injection bit (write only) */
6791  vuint32_t MSKSTWDTERR:1; /* Interrupt enable (STSR2.WDTERR status bit) */
6792  vuint32_t:1;
6793  vuint32_t MSKST_EOC:1; /* Interrupt enable bit for STSR2.ST_EOC */
6794  vuint32_t:4;
6795  vuint32_t MSKWDG_EOA_C:1; /* Interrupt enable (WDG_EOA_C status bit) */
6796  vuint32_t MSKWDG_EOA_RC:1; /* Interrupt enable (WDG_EOA_RC status bit) */
6797  vuint32_t MSKWDG_EOA_S:1; /* Interrupt enable (WDG_EOA_S status bit) */
6798  vuint32_t MSKERR_C:1; /* Interrupt enable (ERR_C status bit) */
6799  vuint32_t MSKERR_RC:1; /* Interrupt enable (ERR_RC status bit) */
6800  vuint32_t MSKERR_S2:1; /* Interrupt enable (ERR_S2 status bit) */
6801  vuint32_t MSKERR_S1:1; /* Interrupt enable (ERR_S1 status bit) */
6802  vuint32_t MSKERR_S0:1; /* Interrupt enable (ERR_S0 status bit) */
6803  vuint32_t:3;
6804  vuint32_t EN:1; /* Self testing channel enable */
6805  vuint32_t:4;
6806  vuint32_t FMA_C:1; /* Fault mapping for the algorithm C */
6807  vuint32_t FMAR_C:1; /* Fault mapping for the algorithm RC */
6808  vuint32_t FMA_S:1; /* Fault mapping for the algorithm BGAP */
6809  } B;
6810  } ADC_STCR2_32B_tag;
6811 
6812  typedef union { /* SELF TEST CONFIGURATION REGISTER 3 */
6813  vuint32_t R;
6814  struct {
6815  vuint32_t:22;
6816  vuint32_t ALG:2; /* Algorithm scheduling */
6817  vuint32_t:8;
6818  } B;
6819  } ADC_STCR3_32B_tag;
6820 
6821  typedef union { /* SELF TEST BAUD RATE REGISTER */
6822  vuint32_t R;
6823  struct {
6824  vuint32_t:13;
6825  vuint32_t WDT:3; /* Watchdog timer value */
6826  vuint32_t:8;
6827  vuint32_t BR:8; /* Baud rate for the selected algorithm in SCAN mode */
6828  } B;
6829  } ADC_STBRR_32B_tag;
6830 
6831  typedef union { /* SELF TEST STATUS REGISTER 1 */
6832  vuint32_t R;
6833  struct {
6834  vuint32_t:6;
6835  vuint32_t WDTERR:1; /* Watchdog timer error */
6836  vuint32_t OVERWR:1; /* Overwrite error */
6837  vuint32_t ST_EOC:1; /* Self test EOC bit */
6838  vuint32_t:4;
6839  vuint32_t WDG_EOA_C:1; /* Algorithm C completed without error */
6840  vuint32_t WDG_EOA_RC:1; /* Algorithm RC completed without error */
6841  vuint32_t WDG_EOA_S:1; /* Algorithm S completed without error */
6842  vuint32_t ERR_C:1; /* Error on the self testing channel (algorithm C) */
6843  vuint32_t ERR_RC:1; /* Error on the self testing channel (algorithm RC) */
6844  vuint32_t ERR_S2:1; /* Error on the self testing channel (algorithm SUPPLY, step 2) */
6845  vuint32_t ERR_S1:1; /* Error on the self testing channel (algorithm SUPPLY, step 1) */
6846  vuint32_t ERR_S0:1; /* Error on the self testing channel (algorithm SUPPLY, step 0) */
6847  vuint32_t:1;
6848  vuint32_t STEP_C:5; /* Step of algorithm C when ERR_C has occurred */
6849  vuint32_t STEP_RC:5; /* Step of algorithm RC when ERR_RC has occurred */
6850  } B;
6851  } ADC_STSR1_32B_tag;
6852 
6853  typedef union { /* SELF TEST STATUS REGISTER 2 */
6854  vuint32_t R;
6855  struct {
6856  vuint32_t OVFL:1; /* Overflow bit */
6857  vuint32_t:3;
6858  vuint32_t DATA1:12; /* Test channel converted data when ERR_S1 has occurred */
6859  vuint32_t:4;
6860  vuint32_t DATA0:12; /* Test channel converted data when ERR_S1 has occurred */
6861  } B;
6862  } ADC_STSR2_32B_tag;
6863 
6864  typedef union { /* SELF TEST STATUS REGISTER 3 */
6865  vuint32_t R;
6866  struct {
6867  vuint32_t:4;
6868  vuint32_t DATA1:12; /* Test channel converted data when ERR_S0 has occurred */
6869  vuint32_t:4;
6870  vuint32_t DATA0:12; /* Test channel converted data when ERR_S0 has occurred */
6871  } B;
6872  } ADC_STSR3_32B_tag;
6873 
6874  typedef union { /* SELF TEST STATUS REGISTER 4 */
6875  vuint32_t R;
6876  struct {
6877  vuint32_t:4;
6878  vuint32_t DATA1:12; /* Test channel converted data when ERR_C has occurred */
6879  vuint32_t:4;
6880  vuint32_t DATA0:12; /* Test channel converted data when ERR_C has occurred */
6881  } B;
6882  } ADC_STSR4_32B_tag;
6883 
6884  typedef union { /* SELF TEST DATA REGISTER 1 */
6885  vuint32_t R;
6886  struct {
6887  vuint32_t:12;
6888  vuint32_t VALID:1; /* Valid data */
6889  vuint32_t OVERWR:1; /* Overwrite data */
6890  vuint32_t:6;
6891  vuint32_t TCDATA:12; /* Test channel converted data */
6892  } B;
6893  } ADC_STDR1_32B_tag;
6894 
6895  typedef union { /* SELF TEST DATA REGISTER 2 */
6896  vuint32_t R;
6897  struct {
6898  vuint32_t FDATA:12; /* Fractional part of the ratio TEST for algorithm S */
6899  vuint32_t VALID:1; /* Valid data */
6900  vuint32_t OVERWR:1; /* Overwrite data */
6901  vuint32_t:6;
6902  vuint32_t IDATA:12; /* Integer part of the ratio TEST for algorithm S */
6903  } B;
6904  } ADC_STDR2_32B_tag;
6905 
6906  typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 0 */
6907  vuint32_t R;
6908  struct {
6909  vuint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */
6910  vuint32_t WDTE:1; /* WatchDog Timer Enable - algorithm S */
6911  vuint32_t:2;
6912  vuint32_t THRH:12; /* High threshold value for channel 0 */
6913  vuint32_t:4;
6914  vuint32_t THRL:12; /* Low threshold value for channel 0 */
6915  } B;
6916  } ADC_STAW0R_32B_tag;
6917 
6918  typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 1A */
6919  vuint32_t R;
6920  struct {
6921  vuint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */
6922  vuint32_t:3;
6923  vuint32_t THRH:12; /* High threshold value for test channel - algorithm S */
6924  vuint32_t:4;
6925  vuint32_t THRL:12; /* Low threshold value for test channel - algorithm S */
6926  } B;
6927  } ADC_STAW1AR_32B_tag;
6928 
6929  typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 1B */
6930  vuint32_t R;
6931  struct {
6932  vuint32_t:4;
6933  vuint32_t THRH:12; /* High threshold value for test channel - algorithm S */
6934  vuint32_t:4;
6935  vuint32_t THRL:12; /* Low threshold value for test channel - algorithm S */
6936  } B;
6937  } ADC_STAW1BR_32B_tag;
6938 
6939  typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 2 */
6940  vuint32_t R;
6941  struct {
6942  vuint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */
6943  vuint32_t:19;
6944  vuint32_t THRL:12; /* Low threshold value for channel */
6945  } B;
6946  } ADC_STAW2R_32B_tag;
6947 
6948  typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 3 */
6949  vuint32_t R;
6950  struct {
6951  vuint32_t AWDE:1; /* Analog WatchDog Enable - algorithm RC */
6952  vuint32_t WDTE:1; /* WatchDog Timer Enable - algorithm RC */
6953  vuint32_t:2;
6954  vuint32_t THRH:12; /* High threshold value for channel 3 */
6955  vuint32_t:4;
6956  vuint32_t THRL:12; /* Low threshold value for channel 3 */
6957  } B;
6958  } ADC_STAW3R_32B_tag;
6959 
6960  typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 4 */
6961  vuint32_t R;
6962  struct {
6963  vuint32_t AWDE:1; /* Analog WatchDog Enable - algorithm C */
6964  vuint32_t WDTE:1; /* WatchDog Timer Enable - algorithm C */
6965  vuint32_t:2;
6966  vuint32_t THRH:12; /* High threshold value for channel 4 */
6967  vuint32_t:4;
6968  vuint32_t THRL:12; /* Low threshold value for channel 4 */
6969  } B;
6970  } ADC_STAW4R_32B_tag;
6971 
6972  typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 5 */
6973  vuint32_t R;
6974  struct {
6975  vuint32_t:4;
6976  vuint32_t THRH:12; /* High threshold value for algorithm C */
6977  vuint32_t:4;
6978  vuint32_t THRL:12; /* Low threshold value for algorithm C */
6979  } B;
6980  } ADC_STAW5R_32B_tag;
6981 
6982 
6983 
6984  typedef struct ADC_struct_tag { /* start of ADC_tag */
6985  /* module configuration register */
6986  ADC_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */
6987  /* module status register */
6988  ADC_MSR_32B_tag MSR; /* offset: 0x0004 size: 32 bit */
6989  int8_t ADC_reserved_0008[8];
6990  /* Interrupt status register */
6991  ADC_ISR_32B_tag ISR; /* offset: 0x0010 size: 32 bit */
6992  union {
6993  ADC_CEOCFR0_32B_tag CEOCFR[3]; /* offset: 0x0014 (0x0004 x 3) */
6994 
6995  struct {
6996  /* CHANNEL PENDING REGISTER 0 */
6997  ADC_CEOCFR0_32B_tag CEOCFR0; /* offset: 0x0014 size: 32 bit */
6998  /* CHANNEL PENDING REGISTER 1 */
6999  ADC_CEOCFR1_32B_tag CEOCFR1; /* offset: 0x0018 size: 32 bit */
7000  /* CHANNEL PENDING REGISTER 2 */
7001  ADC_CEOCFR2_32B_tag CEOCFR2; /* offset: 0x001C size: 32 bit */
7002  };
7003 
7004  };
7005  /* interrupt mask register */
7006  ADC_IMR_32B_tag IMR; /* offset: 0x0020 size: 32 bit */
7007  union {
7008  ADC_CIMR0_32B_tag CIMR[3]; /* offset: 0x0024 (0x0004 x 3) */
7009 
7010  struct {
7011  /* CHANNEL INTERRUPT MASK REGISTER 0 */
7012  ADC_CIMR0_32B_tag CIMR0; /* offset: 0x0024 size: 32 bit */
7013  /* CHANNEL INTERRUPT MASK REGISTER 1 */
7014  ADC_CIMR1_32B_tag CIMR1; /* offset: 0x0028 size: 32 bit */
7015  /* CHANNEL INTERRUPT MASK REGISTER 2 */
7016  ADC_CIMR2_32B_tag CIMR2; /* offset: 0x002C size: 32 bit */
7017  };
7018 
7019  };
7020  /* Watchdog Threshold interrupt status register */
7021  ADC_WTISR_32B_tag WTISR; /* offset: 0x0030 size: 32 bit */
7022  /* Watchdog interrupt MASK register */
7023  ADC_WTIMR_32B_tag WTIMR; /* offset: 0x0034 size: 32 bit */
7024  int8_t ADC_reserved_0038[8];
7025  /* DMAE register */
7026  ADC_DMAE_32B_tag DMAE; /* offset: 0x0040 size: 32 bit */
7027  union {
7028  ADC_DMAR0_32B_tag DMAR[3]; /* offset: 0x0044 (0x0004 x 3) */
7029 
7030  struct {
7031  /* DMA REGISTER 0 */
7032  ADC_DMAR0_32B_tag DMAR0; /* offset: 0x0044 size: 32 bit */
7033  /* DMA REGISTER 1 */
7034  ADC_DMAR1_32B_tag DMAR1; /* offset: 0x0048 size: 32 bit */
7035  /* DMA REGISTER 2 */
7036  ADC_DMAR2_32B_tag DMAR2; /* offset: 0x004C size: 32 bit */
7037  };
7038 
7039  };
7040  union {
7041  /* Threshold Control register C */
7042  ADC_TRC_32B_tag TRC[4]; /* offset: 0x0050 (0x0004 x 4) */
7043 
7044  struct {
7045  /* Threshold Control register C */
7046  ADC_TRC_32B_tag TRC0; /* offset: 0x0050 size: 32 bit */
7047  ADC_TRC_32B_tag TRC1; /* offset: 0x0054 size: 32 bit */
7048  ADC_TRC_32B_tag TRC2; /* offset: 0x0058 size: 32 bit */
7049  ADC_TRC_32B_tag TRC3; /* offset: 0x005C size: 32 bit */
7050  };
7051 
7052  };
7053  union {
7054  /* Upper Threshold register */
7055  ADC_THRHLR_32B_tag THRHLR[4]; /* offset: 0x0060 (0x0004 x 4) */
7056 
7057  struct {
7058  /* Upper Threshold register */
7059  ADC_THRHLR_32B_tag THRHLR0; /* offset: 0x0060 size: 32 bit */
7060  ADC_THRHLR_32B_tag THRHLR1; /* offset: 0x0064 size: 32 bit */
7061  ADC_THRHLR_32B_tag THRHLR2; /* offset: 0x0068 size: 32 bit */
7062  ADC_THRHLR_32B_tag THRHLR3; /* offset: 0x006C size: 32 bit */
7063  };
7064 
7065  };
7066  union {
7067  /* alternate Upper Threshold register */
7068  ADC_THRALT_32B_tag THRALT[4]; /* offset: 0x0070 (0x0004 x 4) */
7069 
7070  struct {
7071  /* alternate Upper Threshold register */
7072  ADC_THRALT_32B_tag THRALT0; /* offset: 0x0070 size: 32 bit */
7073  ADC_THRALT_32B_tag THRALT1; /* offset: 0x0074 size: 32 bit */
7074  ADC_THRALT_32B_tag THRALT2; /* offset: 0x0078 size: 32 bit */
7075  ADC_THRALT_32B_tag THRALT3; /* offset: 0x007C size: 32 bit */
7076  };
7077 
7078  };
7079  /* PRESAMPLING CONTROL REGISTER */
7080  ADC_PSCR_32B_tag PSCR; /* offset: 0x0080 size: 32 bit */
7081  union {
7082  ADC_PSR0_32B_tag PSR[3]; /* offset: 0x0084 (0x0004 x 3) */
7083 
7084  struct {
7085  /* Presampling Register 0 */
7086  ADC_PSR0_32B_tag PSR0; /* offset: 0x0084 size: 32 bit */
7087  /* Presampling REGISTER 1 */
7088  ADC_PSR1_32B_tag PSR1; /* offset: 0x0088 size: 32 bit */
7089  /* Presampling REGISTER 2 */
7090  ADC_PSR2_32B_tag PSR2; /* offset: 0x008C size: 32 bit */
7091  };
7092 
7093  };
7094  int8_t ADC_reserved_0090_C[4];
7095  union {
7096  /* conversion timing register */
7097  ADC_CTR_32B_tag CTR[3]; /* offset: 0x0094 (0x0004 x 3) */
7098 
7099  struct {
7100  /* conversion timing register */
7101  ADC_CTR_32B_tag CTR0; /* offset: 0x0094 size: 32 bit */
7102  ADC_CTR_32B_tag CTR1; /* offset: 0x0098 size: 32 bit */
7103  ADC_CTR_32B_tag CTR2; /* offset: 0x009C size: 32 bit */
7104  };
7105 
7106  };
7107  int8_t ADC_reserved_00A0_C[4];
7108  union {
7109  ADC_NCMR0_32B_tag NCMR[3]; /* offset: 0x00A4 (0x0004 x 3) */
7110 
7111  struct {
7112  /* NORMAL CONVERSION MASK REGISTER 0 */
7113  ADC_NCMR0_32B_tag NCMR0; /* offset: 0x00A4 size: 32 bit */
7114  /* NORMAL CONVERSION MASK REGISTER 1 */
7115  ADC_NCMR1_32B_tag NCMR1; /* offset: 0x00A8 size: 32 bit */
7116  /* NORMAL CONVERSION MASK REGISTER 2 */
7117  ADC_NCMR2_32B_tag NCMR2; /* offset: 0x00AC size: 32 bit */
7118  };
7119 
7120  };
7121  int8_t ADC_reserved_00B0_C[4];
7122  union {
7123  ADC_JCMR0_32B_tag JCMR[3]; /* offset: 0x00B4 (0x0004 x 3) */
7124 
7125  struct {
7126  /* Injected Conversion Mask Register 0 */
7127  ADC_JCMR0_32B_tag JCMR0; /* offset: 0x00B4 size: 32 bit */
7128  /* INJECTED CONVERSION MASK REGISTER 1 */
7129  ADC_JCMR1_32B_tag JCMR1; /* offset: 0x00B8 size: 32 bit */
7130  /* INJECTED CONVERSION MASK REGISTER 2 */
7131  ADC_JCMR2_32B_tag JCMR2; /* offset: 0x00BC size: 32 bit */
7132  };
7133 
7134  };
7135  /* Offset Word Regsiter */
7136  ADC_OFFWR_32B_tag OFFWR; /* offset: 0x00C0 size: 32 bit */
7137  /* Decode Signal Delay Register */
7138  ADC_DSDR_32B_tag DSDR; /* offset: 0x00C4 size: 32 bit */
7139  /* Power Down Dealy Register */
7140  ADC_PDEDR_32B_tag PDEDR; /* offset: 0x00C8 size: 32 bit */
7141  int8_t ADC_reserved_00CC_C[52];
7142  union {
7143  /* CHANNEL DATA REGS */
7144  ADC_CDR_32B_tag CDR[96]; /* offset: 0x0100 (0x0004 x 96) */
7145 
7146  struct {
7147  /* CHANNEL DATA REGS */
7148  ADC_CDR_32B_tag CDR0; /* offset: 0x0100 size: 32 bit */
7149  ADC_CDR_32B_tag CDR1; /* offset: 0x0104 size: 32 bit */
7150  ADC_CDR_32B_tag CDR2; /* offset: 0x0108 size: 32 bit */
7151  ADC_CDR_32B_tag CDR3; /* offset: 0x010C size: 32 bit */
7152  ADC_CDR_32B_tag CDR4; /* offset: 0x0110 size: 32 bit */
7153  ADC_CDR_32B_tag CDR5; /* offset: 0x0114 size: 32 bit */
7154  ADC_CDR_32B_tag CDR6; /* offset: 0x0118 size: 32 bit */
7155  ADC_CDR_32B_tag CDR7; /* offset: 0x011C size: 32 bit */
7156  ADC_CDR_32B_tag CDR8; /* offset: 0x0120 size: 32 bit */
7157  ADC_CDR_32B_tag CDR9; /* offset: 0x0124 size: 32 bit */
7158  ADC_CDR_32B_tag CDR10; /* offset: 0x0128 size: 32 bit */
7159  ADC_CDR_32B_tag CDR11; /* offset: 0x012C size: 32 bit */
7160  ADC_CDR_32B_tag CDR12; /* offset: 0x0130 size: 32 bit */
7161  ADC_CDR_32B_tag CDR13; /* offset: 0x0134 size: 32 bit */
7162  ADC_CDR_32B_tag CDR14; /* offset: 0x0138 size: 32 bit */
7163  ADC_CDR_32B_tag CDR15; /* offset: 0x013C size: 32 bit */
7164  ADC_CDR_32B_tag CDR16; /* offset: 0x0140 size: 32 bit */
7165  ADC_CDR_32B_tag CDR17; /* offset: 0x0144 size: 32 bit */
7166  ADC_CDR_32B_tag CDR18; /* offset: 0x0148 size: 32 bit */
7167  ADC_CDR_32B_tag CDR19; /* offset: 0x014C size: 32 bit */
7168  ADC_CDR_32B_tag CDR20; /* offset: 0x0150 size: 32 bit */
7169  ADC_CDR_32B_tag CDR21; /* offset: 0x0154 size: 32 bit */
7170  ADC_CDR_32B_tag CDR22; /* offset: 0x0158 size: 32 bit */
7171  ADC_CDR_32B_tag CDR23; /* offset: 0x015C size: 32 bit */
7172  ADC_CDR_32B_tag CDR24; /* offset: 0x0160 size: 32 bit */
7173  ADC_CDR_32B_tag CDR25; /* offset: 0x0164 size: 32 bit */
7174  ADC_CDR_32B_tag CDR26; /* offset: 0x0168 size: 32 bit */
7175  ADC_CDR_32B_tag CDR27; /* offset: 0x016C size: 32 bit */
7176  ADC_CDR_32B_tag CDR28; /* offset: 0x0170 size: 32 bit */
7177  ADC_CDR_32B_tag CDR29; /* offset: 0x0174 size: 32 bit */
7178  ADC_CDR_32B_tag CDR30; /* offset: 0x0178 size: 32 bit */
7179  ADC_CDR_32B_tag CDR31; /* offset: 0x017C size: 32 bit */
7180  ADC_CDR_32B_tag CDR32; /* offset: 0x0180 size: 32 bit */
7181  ADC_CDR_32B_tag CDR33; /* offset: 0x0184 size: 32 bit */
7182  ADC_CDR_32B_tag CDR34; /* offset: 0x0188 size: 32 bit */
7183  ADC_CDR_32B_tag CDR35; /* offset: 0x018C size: 32 bit */
7184  ADC_CDR_32B_tag CDR36; /* offset: 0x0190 size: 32 bit */
7185  ADC_CDR_32B_tag CDR37; /* offset: 0x0194 size: 32 bit */
7186  ADC_CDR_32B_tag CDR38; /* offset: 0x0198 size: 32 bit */
7187  ADC_CDR_32B_tag CDR39; /* offset: 0x019C size: 32 bit */
7188  ADC_CDR_32B_tag CDR40; /* offset: 0x01A0 size: 32 bit */
7189  ADC_CDR_32B_tag CDR41; /* offset: 0x01A4 size: 32 bit */
7190  ADC_CDR_32B_tag CDR42; /* offset: 0x01A8 size: 32 bit */
7191  ADC_CDR_32B_tag CDR43; /* offset: 0x01AC size: 32 bit */
7192  ADC_CDR_32B_tag CDR44; /* offset: 0x01B0 size: 32 bit */
7193  ADC_CDR_32B_tag CDR45; /* offset: 0x01B4 size: 32 bit */
7194  ADC_CDR_32B_tag CDR46; /* offset: 0x01B8 size: 32 bit */
7195  ADC_CDR_32B_tag CDR47; /* offset: 0x01BC size: 32 bit */
7196  ADC_CDR_32B_tag CDR48; /* offset: 0x01C0 size: 32 bit */
7197  ADC_CDR_32B_tag CDR49; /* offset: 0x01C4 size: 32 bit */
7198  ADC_CDR_32B_tag CDR50; /* offset: 0x01C8 size: 32 bit */
7199  ADC_CDR_32B_tag CDR51; /* offset: 0x01CC size: 32 bit */
7200  ADC_CDR_32B_tag CDR52; /* offset: 0x01D0 size: 32 bit */
7201  ADC_CDR_32B_tag CDR53; /* offset: 0x01D4 size: 32 bit */
7202  ADC_CDR_32B_tag CDR54; /* offset: 0x01D8 size: 32 bit */
7203  ADC_CDR_32B_tag CDR55; /* offset: 0x01DC size: 32 bit */
7204  ADC_CDR_32B_tag CDR56; /* offset: 0x01E0 size: 32 bit */
7205  ADC_CDR_32B_tag CDR57; /* offset: 0x01E4 size: 32 bit */
7206  ADC_CDR_32B_tag CDR58; /* offset: 0x01E8 size: 32 bit */
7207  ADC_CDR_32B_tag CDR59; /* offset: 0x01EC size: 32 bit */
7208  ADC_CDR_32B_tag CDR60; /* offset: 0x01F0 size: 32 bit */
7209  ADC_CDR_32B_tag CDR61; /* offset: 0x01F4 size: 32 bit */
7210  ADC_CDR_32B_tag CDR62; /* offset: 0x01F8 size: 32 bit */
7211  ADC_CDR_32B_tag CDR63; /* offset: 0x01FC size: 32 bit */
7212  ADC_CDR_32B_tag CDR64; /* offset: 0x0200 size: 32 bit */
7213  ADC_CDR_32B_tag CDR65; /* offset: 0x0204 size: 32 bit */
7214  ADC_CDR_32B_tag CDR66; /* offset: 0x0208 size: 32 bit */
7215  ADC_CDR_32B_tag CDR67; /* offset: 0x020C size: 32 bit */
7216  ADC_CDR_32B_tag CDR68; /* offset: 0x0210 size: 32 bit */
7217  ADC_CDR_32B_tag CDR69; /* offset: 0x0214 size: 32 bit */
7218  ADC_CDR_32B_tag CDR70; /* offset: 0x0218 size: 32 bit */
7219  ADC_CDR_32B_tag CDR71; /* offset: 0x021C size: 32 bit */
7220  ADC_CDR_32B_tag CDR72; /* offset: 0x0220 size: 32 bit */
7221  ADC_CDR_32B_tag CDR73; /* offset: 0x0224 size: 32 bit */
7222  ADC_CDR_32B_tag CDR74; /* offset: 0x0228 size: 32 bit */
7223  ADC_CDR_32B_tag CDR75; /* offset: 0x022C size: 32 bit */
7224  ADC_CDR_32B_tag CDR76; /* offset: 0x0230 size: 32 bit */
7225  ADC_CDR_32B_tag CDR77; /* offset: 0x0234 size: 32 bit */
7226  ADC_CDR_32B_tag CDR78; /* offset: 0x0238 size: 32 bit */
7227  ADC_CDR_32B_tag CDR79; /* offset: 0x023C size: 32 bit */
7228  ADC_CDR_32B_tag CDR80; /* offset: 0x0240 size: 32 bit */
7229  ADC_CDR_32B_tag CDR81; /* offset: 0x0244 size: 32 bit */
7230  ADC_CDR_32B_tag CDR82; /* offset: 0x0248 size: 32 bit */
7231  ADC_CDR_32B_tag CDR83; /* offset: 0x024C size: 32 bit */
7232  ADC_CDR_32B_tag CDR84; /* offset: 0x0250 size: 32 bit */
7233  ADC_CDR_32B_tag CDR85; /* offset: 0x0254 size: 32 bit */
7234  ADC_CDR_32B_tag CDR86; /* offset: 0x0258 size: 32 bit */
7235  ADC_CDR_32B_tag CDR87; /* offset: 0x025C size: 32 bit */
7236  ADC_CDR_32B_tag CDR88; /* offset: 0x0260 size: 32 bit */
7237  ADC_CDR_32B_tag CDR89; /* offset: 0x0264 size: 32 bit */
7238  ADC_CDR_32B_tag CDR90; /* offset: 0x0268 size: 32 bit */
7239  ADC_CDR_32B_tag CDR91; /* offset: 0x026C size: 32 bit */
7240  ADC_CDR_32B_tag CDR92; /* offset: 0x0270 size: 32 bit */
7241  ADC_CDR_32B_tag CDR93; /* offset: 0x0274 size: 32 bit */
7242  ADC_CDR_32B_tag CDR94; /* offset: 0x0278 size: 32 bit */
7243  ADC_CDR_32B_tag CDR95; /* offset: 0x027C size: 32 bit */
7244  };
7245 
7246  };
7247  /* Upper Threshold register 4 is not contiguous to 3 */
7248  ADC_THRHLR4_32B_tag THRHLR4; /* offset: 0x0280 size: 32 bit */
7249  /* Upper Threshold register 5 */
7250  ADC_THRHLR5_32B_tag THRHLR5; /* offset: 0x0284 size: 32 bit */
7251  /* Upper Threshold register 6 */
7252  ADC_THRHLR6_32B_tag THRHLR6; /* offset: 0x0288 size: 32 bit */
7253  /* Upper Threshold register 7 */
7254  ADC_THRHLR7_32B_tag THRHLR7; /* offset: 0x028C size: 32 bit */
7255  /* Upper Threshold register 8 */
7256  ADC_THRHLR8_32B_tag THRHLR8; /* offset: 0x0290 size: 32 bit */
7257  /* Upper Threshold register 9 */
7258  ADC_THRHLR9_32B_tag THRHLR9; /* offset: 0x0294 size: 32 bit */
7259  /* Upper Threshold register 10 */
7260  ADC_THRHLR10_32B_tag THRHLR10; /* offset: 0x0298 size: 32 bit */
7261  /* Upper Threshold register 11 */
7262  ADC_THRHLR11_32B_tag THRHLR11; /* offset: 0x029C size: 32 bit */
7263  /* Upper Threshold register 12 */
7264  ADC_THRHLR12_32B_tag THRHLR12; /* offset: 0x02A0 size: 32 bit */
7265  /* Upper Threshold register 13 */
7266  ADC_THRHLR13_32B_tag THRHLR13; /* offset: 0x02A4 size: 32 bit */
7267  /* Upper Threshold register 14 */
7268  ADC_THRHLR14_32B_tag THRHLR14; /* offset: 0x02A8 size: 32 bit */
7269  /* Upper Threshold register 15 */
7270  ADC_THRHLR15_32B_tag THRHLR15; /* offset: 0x02AC size: 32 bit */
7271  union {
7272  /* Channel Watchdog Select register */
7273  ADC_CWSELR_32B_tag CWSELR[12]; /* offset: 0x02B0 (0x0004 x 12) */
7274 
7275  struct {
7276  /* Channel Watchdog Select register */
7277  ADC_CWSELR_32B_tag CWSELR0; /* offset: 0x02B0 size: 32 bit */
7278  ADC_CWSELR_32B_tag CWSELR1; /* offset: 0x02B4 size: 32 bit */
7279  ADC_CWSELR_32B_tag CWSELR2; /* offset: 0x02B8 size: 32 bit */
7280  ADC_CWSELR_32B_tag CWSELR3; /* offset: 0x02BC size: 32 bit */
7281  ADC_CWSELR_32B_tag CWSELR4; /* offset: 0x02C0 size: 32 bit */
7282  ADC_CWSELR_32B_tag CWSELR5; /* offset: 0x02C4 size: 32 bit */
7283  ADC_CWSELR_32B_tag CWSELR6; /* offset: 0x02C8 size: 32 bit */
7284  ADC_CWSELR_32B_tag CWSELR7; /* offset: 0x02CC size: 32 bit */
7285  ADC_CWSELR_32B_tag CWSELR8; /* offset: 0x02D0 size: 32 bit */
7286  ADC_CWSELR_32B_tag CWSELR9; /* offset: 0x02D4 size: 32 bit */
7287  ADC_CWSELR_32B_tag CWSELR10; /* offset: 0x02D8 size: 32 bit */
7288  ADC_CWSELR_32B_tag CWSELR11; /* offset: 0x02DC size: 32 bit */
7289  };
7290 
7291  };
7292  union {
7293  /* Channel Watchdog Enable Register */
7294  ADC_CWENR_32B_tag CWENR[3]; /* offset: 0x02E0 (0x0004 x 3) */
7295 
7296  struct {
7297  /* Channel Watchdog Enable Register */
7298  ADC_CWENR_32B_tag CWENR0; /* offset: 0x02E0 size: 32 bit */
7299  ADC_CWENR_32B_tag CWENR1; /* offset: 0x02E4 size: 32 bit */
7300  ADC_CWENR_32B_tag CWENR2; /* offset: 0x02E8 size: 32 bit */
7301  };
7302 
7303  };
7304  int8_t ADC_reserved_02EC_C[4];
7305  union {
7306  /* Analog Watchdog Out of Range Register */
7307  ADC_AWORR_32B_tag AWORR[3]; /* offset: 0x02F0 (0x0004 x 3) */
7308 
7309  struct {
7310  /* Analog Watchdog Out of Range Register */
7311  ADC_AWORR_32B_tag AWORR0; /* offset: 0x02F0 size: 32 bit */
7312  ADC_AWORR_32B_tag AWORR1; /* offset: 0x02F4 size: 32 bit */
7313  ADC_AWORR_32B_tag AWORR2; /* offset: 0x02F8 size: 32 bit */
7314  };
7315 
7316  };
7317  int8_t ADC_reserved_02FC[68];
7318  /* SELF TEST CONFIGURATION REGISTER 1 */
7319  ADC_STCR1_32B_tag STCR1; /* offset: 0x0340 size: 32 bit */
7320  /* SELF TEST CONFIGURATION REGISTER 2 */
7321  ADC_STCR2_32B_tag STCR2; /* offset: 0x0344 size: 32 bit */
7322  /* SELF TEST CONFIGURATION REGISTER 3 */
7323  ADC_STCR3_32B_tag STCR3; /* offset: 0x0348 size: 32 bit */
7324  /* SELF TEST BAUD RATE REGISTER */
7325  ADC_STBRR_32B_tag STBRR; /* offset: 0x034C size: 32 bit */
7326  /* SELF TEST STATUS REGISTER 1 */
7327  ADC_STSR1_32B_tag STSR1; /* offset: 0x0350 size: 32 bit */
7328  /* SELF TEST STATUS REGISTER 2 */
7329  ADC_STSR2_32B_tag STSR2; /* offset: 0x0354 size: 32 bit */
7330  /* SELF TEST STATUS REGISTER 3 */
7331  ADC_STSR3_32B_tag STSR3; /* offset: 0x0358 size: 32 bit */
7332  /* SELF TEST STATUS REGISTER 4 */
7333  ADC_STSR4_32B_tag STSR4; /* offset: 0x035C size: 32 bit */
7334  int8_t ADC_reserved_0360[16];
7335  /* SELF TEST DATA REGISTER 1 */
7336  ADC_STDR1_32B_tag STDR1; /* offset: 0x0370 size: 32 bit */
7337  /* SELF TEST DATA REGISTER 2 */
7338  ADC_STDR2_32B_tag STDR2; /* offset: 0x0374 size: 32 bit */
7339  int8_t ADC_reserved_0378[8];
7340  /* SELF TEST ANALOG WATCHDOG REGISTER 0 */
7341  ADC_STAW0R_32B_tag STAW0R; /* offset: 0x0380 size: 32 bit */
7342  /* SELF TEST ANALOG WATCHDOG REGISTER 1A */
7343  ADC_STAW1AR_32B_tag STAW1AR; /* offset: 0x0384 size: 32 bit */
7344  /* SELF TEST ANALOG WATCHDOG REGISTER 1B */
7345  ADC_STAW1BR_32B_tag STAW1BR; /* offset: 0x0388 size: 32 bit */
7346  /* SELF TEST ANALOG WATCHDOG REGISTER 2 */
7347  ADC_STAW2R_32B_tag STAW2R; /* offset: 0x038C size: 32 bit */
7348  /* SELF TEST ANALOG WATCHDOG REGISTER 3 */
7349  ADC_STAW3R_32B_tag STAW3R; /* offset: 0x0390 size: 32 bit */
7350  /* SELF TEST ANALOG WATCHDOG REGISTER 4 */
7351  ADC_STAW4R_32B_tag STAW4R; /* offset: 0x0394 size: 32 bit */
7352  /* SELF TEST ANALOG WATCHDOG REGISTER 5 */
7353  ADC_STAW5R_32B_tag STAW5R; /* offset: 0x0398 size: 32 bit */
7354  } ADC_tag;
7355 
7356 
7357 #define ADC0 (*(volatile ADC_tag *) 0xFFE00000UL)
7358 #define ADC1 (*(volatile ADC_tag *) 0xFFE04000UL)
7359 
7360 
7361 
7362 /****************************************************************/
7363 /* */
7364 /* Module: CTU */
7365 /* */
7366 /****************************************************************/
7367 
7368  typedef union { /* Trigger Generator Subunit Input Selection register */
7369  vuint32_t R;
7370  struct {
7371  vuint32_t I15_FE:1; /* ext_signal Falling Edge */
7372  vuint32_t I15_RE:1; /* ext_signal Rising Edge */
7373  vuint32_t I14_FE:1; /* eTimer2 Falling Edge Enable */
7374  vuint32_t I14_RE:1; /* eTimer2 Rising Edge Enable */
7375  vuint32_t I13_FE:1; /* eTimer1 Falling Edge Enable */
7376  vuint32_t I13_RE:1; /* eTimer1 Rising Edge Enable */
7377  vuint32_t I12_FE:1; /* RPWM ch3 Falling Edge Enable */
7378  vuint32_t I12_RE:1; /* RPWM ch3 Rising Edge Enable */
7379  vuint32_t I11_FE:1; /* RPWM ch2 Falling Edge Enable */
7380  vuint32_t I11_RE:1; /* RPWM ch2 Rising Edge Enable */
7381  vuint32_t I10_FE:1; /* RPWM ch1 Falling Edge Enable */
7382  vuint32_t I10_RE:1; /* RPWM ch1 Rising Edge Enable */
7383  vuint32_t I9_FE:1; /* RPWM ch0 Falling Edge Enable */
7384  vuint32_t I9_RE:1; /* RPWM ch0 Rising Edge Enable */
7385  vuint32_t I8_FE:1; /* PWM ch3 even trig Falling edge Enable */
7386  vuint32_t I8_RE:1; /* PWM ch3 even trig Rising edge Enable */
7387  vuint32_t I7_FE:1; /* PWM ch2 even trig Falling edge Enable */
7388  vuint32_t I7_RE:1; /* PWM ch2 even trig Rising edge Enable */
7389  vuint32_t I6_FE:1; /* PWM ch1 even trig Falling edge Enable */
7390  vuint32_t I6_RE:1; /* PWM ch1 even trig Rising edge Enable */
7391  vuint32_t I5_FE:1; /* PWM ch0 even trig Falling edge Enable */
7392  vuint32_t I5_RE:1; /* PWM ch0 even trig Rising edge Enable */
7393  vuint32_t I4_FE:1; /* PWM ch3 odd trig Falling edge Enable */
7394  vuint32_t I4_RE:1; /* PWM ch3 odd trig Rising edge Enable */
7395  vuint32_t I3_FE:1; /* PWM ch2 odd trig Falling edge Enable */
7396  vuint32_t I3_RE:1; /* PWM ch2 odd trig Rising edge Enable */
7397  vuint32_t I2_FE:1; /* PWM ch1 odd trig Falling edge Enable */
7398  vuint32_t I2_RE:1; /* PWM ch1 odd trig Rising edge Enable */
7399  vuint32_t I1_FE:1; /* PWM ch0 odd trig Falling edge Enable */
7400  vuint32_t I1_RE:1; /* PWM ch0 odd trig Rising edge Enable */
7401  vuint32_t I0_FE:1; /* PWM Reload Falling Edge Enable */
7402  vuint32_t I0_RE:1; /* PWM Reload Rising Edge Enable */
7403  } B;
7404  } CTU_TGSISR_32B_tag;
7405 
7406  typedef union { /* Trigger Generator Subunit Control Register */
7407  vuint16_t R;
7408  struct {
7409  vuint16_t:7;
7410 #ifndef USE_FIELD_ALIASES_CTU
7411  vuint16_t ET_TM:1; /* Toggle Mode Enable */
7412 #else
7413  vuint16_t ETTM:1; /* deprecated name - please avoid */
7414 #endif
7415  vuint16_t PRES:2; /* TGS Prescaler Selection */
7416 #ifndef USE_FIELD_ALIASES_CTU
7417  vuint16_t MRS_SM:5; /* MRS Selection in Sequential Mode */
7418 #else
7419  vuint16_t MRSSM:5; /* deprecated name - please avoid */
7420 #endif
7421 #ifndef USE_FIELD_ALIASES_CTU
7422  vuint16_t TGS_M:1; /* Trigger Generator Subunit Mode */
7423 #else
7424  vuint16_t TGSM:1; /* deprecated name - please avoid */
7425 #endif
7426  } B;
7427  } CTU_TGSCR_16B_tag;
7428 
7429  typedef union { /* */
7430  vuint16_t R;
7431  } CTU_TCR_16B_tag;
7432 
7433  typedef union { /* TGS Counter Compare Register */
7434  vuint16_t R;
7435 #ifndef USE_FIELD_ALIASES_CTU
7436  struct {
7437  vuint16_t TGSCCV:16; /* deprecated field -- do not use */
7438  } B;
7439 #endif
7440  } CTU_TGSCCR_16B_tag;
7441 
7442  typedef union { /* TGS Counter Reload Register */
7443  vuint16_t R;
7444 #ifndef USE_FIELD_ALIASES_CTU
7445  struct {
7446  vuint16_t TGSCRV:16; /* deprecated field -- do not use */
7447  } B;
7448 #endif
7449  } CTU_TGSCRR_16B_tag;
7450 
7451  typedef union { /* Commands List Control Register 1 */
7452  vuint32_t R;
7453  struct {
7454  vuint32_t:3;
7455  vuint32_t T3INDEX:5; /* Trigger 3 First Command address */
7456  vuint32_t:3;
7457  vuint32_t T2INDEX:5; /* Trigger 2 First Command address */
7458  vuint32_t:3;
7459  vuint32_t T1INDEX:5; /* Trigger 1 First Command address */
7460  vuint32_t:3;
7461  vuint32_t T0INDEX:5; /* Trigger 0 First Command address */
7462  } B;
7463  } CTU_CLCR1_32B_tag;
7464 
7465  typedef union { /* Commands List Control Register 2 */
7466  vuint32_t R;
7467  struct {
7468  vuint32_t:3;
7469  vuint32_t T7INDEX:5; /* Trigger 7 First Command address */
7470  vuint32_t:3;
7471  vuint32_t T6INDEX:5; /* Trigger 6 First Command address */
7472  vuint32_t:3;
7473  vuint32_t T5INDEX:5; /* Trigger 5 First Command address */
7474  vuint32_t:3;
7475  vuint32_t T4INDEX:5; /* Trigger 4 First Command address */
7476  } B;
7477  } CTU_CLCR2_32B_tag;
7478 
7479  typedef union { /* Trigger Handler Control Register 1 */
7480  vuint32_t R;
7481  struct {
7482  vuint32_t:1;
7483  vuint32_t T3_E:1; /* Trigger 3 enable */
7484  vuint32_t T3_ETE:1; /* Trigger 3 Ext Trigger output enable */
7485  vuint32_t T3_T4E:1; /* Trigger 3 Timer4 output enable */
7486  vuint32_t T3_T3E:1; /* Trigger 3 Timer3 output enable */
7487  vuint32_t T3_T2E:1; /* Trigger 3 Timer2 output enable */
7488  vuint32_t T3_T1E:1; /* Trigger 3 Timer1 output enable */
7489  vuint32_t T3_ADCE:1; /* Trigger 3 ADC Command output enable */
7490  vuint32_t:1;
7491  vuint32_t T2_E:1; /* Trigger 2 enable */
7492  vuint32_t T2_ETE:1; /* Trigger 2 Ext Trigger output enable */
7493  vuint32_t T2_T4E:1; /* Trigger 2 Timer4 output enable */
7494  vuint32_t T2_T3E:1; /* Trigger 2 Timer3 output enable */
7495  vuint32_t T2_T2E:1; /* Trigger 2 Timer2 output enable */
7496  vuint32_t T2_T1E:1; /* Trigger 2 Timer1 output enable */
7497  vuint32_t T2_ADCE:1; /* Trigger 2 ADC Command output enable */
7498  vuint32_t:1;
7499  vuint32_t T1_E:1; /* Trigger 1 enable */
7500  vuint32_t T1_ETE:1; /* Trigger 1 Ext Trigger output enable */
7501  vuint32_t T1_T4E:1; /* Trigger 1 Timer4 output enable */
7502  vuint32_t T1_T3E:1; /* Trigger 1 Timer3 output enable */
7503  vuint32_t T1_T2E:1; /* Trigger 1 Timer2 output enable */
7504  vuint32_t T1_T1E:1; /* Trigger 1 Timer1 output enable */
7505  vuint32_t T1_ADCE:1; /* Trigger 1 ADC Command output enable */
7506  vuint32_t:1;
7507  vuint32_t T0_E:1; /* Trigger 0 enable */
7508  vuint32_t T0_ETE:1; /* Trigger 0 Ext Trigger output enable */
7509  vuint32_t T0_T4E:1; /* Trigger 0 Timer4 output enable */
7510  vuint32_t T0_T3E:1; /* Trigger 0 Timer3 output enable */
7511  vuint32_t T0_T2E:1; /* Trigger 0 Timer2 output enable */
7512  vuint32_t T0_T1E:1; /* Trigger 0 Timer1 output enable */
7513  vuint32_t T0_ADCE:1; /* Trigger 0 ADC Command output enable */
7514  } B;
7515  } CTU_THCR1_32B_tag;
7516 
7517  typedef union { /* Trigger Handler Control Register 2 */
7518  vuint32_t R;
7519  struct {
7520  vuint32_t:1;
7521  vuint32_t T7_E:1; /* Trigger 7 enable */
7522  vuint32_t T7_ETE:1; /* Trigger 7 Ext Trigger output enable */
7523  vuint32_t T7_T4E:1; /* Trigger 7 Timer4 output enable */
7524  vuint32_t T7_T3E:1; /* Trigger 7 Timer3 output enable */
7525  vuint32_t T7_T2E:1; /* Trigger 7 Timer2 output enable */
7526  vuint32_t T7_T1E:1; /* Trigger 7 Timer1 output enable */
7527  vuint32_t T7_ADCE:1; /* Trigger 7 ADC Command output enable */
7528  vuint32_t:1;
7529  vuint32_t T6_E:1; /* Trigger 6 enable */
7530  vuint32_t T6_ETE:1; /* Trigger 6 Ext Trigger output enable */
7531  vuint32_t T6_T4E:1; /* Trigger 6 Timer4 output enable */
7532  vuint32_t T6_T3E:1; /* Trigger 6 Timer3 output enable */
7533  vuint32_t T6_T2E:1; /* Trigger 6 Timer2 output enable */
7534  vuint32_t T6_T1E:1; /* Trigger 6 Timer1 output enable */
7535  vuint32_t T6_ADCE:1; /* Trigger 6 ADC Command output enable */
7536  vuint32_t:1;
7537  vuint32_t T5_E:1; /* Trigger 5 enable */
7538  vuint32_t T5_ETE:1; /* Trigger 5 Ext Trigger output enable */
7539  vuint32_t T5_T4E:1; /* Trigger 5 Timer4 output enable */
7540  vuint32_t T5_T3E:1; /* Trigger 5 Timer3 output enable */
7541  vuint32_t T5_T2E:1; /* Trigger 5 Timer2 output enable */
7542  vuint32_t T5_T1E:1; /* Trigger 5 Timer1 output enable */
7543  vuint32_t T5_ADCE:1; /* Trigger 5 ADC Command output enable */
7544  vuint32_t:1;
7545  vuint32_t T4_E:1; /* Trigger 4 enable */
7546  vuint32_t T4_ETE:1; /* Trigger 4 Ext Trigger output enable */
7547  vuint32_t T4_T4E:1; /* Trigger 4 Timer4 output enable */
7548  vuint32_t T4_T3E:1; /* Trigger 4 Timer3 output enable */
7549  vuint32_t T4_T2E:1; /* Trigger 4 Timer2 output enable */
7550  vuint32_t T4_T1E:1; /* Trigger 4 Timer1 output enable */
7551  vuint32_t T4_ADCE:1; /* Trigger 4 ADC Command output enable */
7552  } B;
7553  } CTU_THCR2_32B_tag;
7554 
7555 
7556  /* Register layout for all registers CLR_DCM... */
7557 
7558  typedef union { /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */
7559  vuint16_t R;
7560  struct {
7561  vuint16_t CIR:1; /* Command Interrupt Request */
7562  vuint16_t LC:1; /* Last Command */
7563  vuint16_t CMS:1; /* Conversion Mode Selection */
7564  vuint16_t FIFO:3; /* FIFO for ADC A/B */
7565  vuint16_t:1;
7566  vuint16_t CHB:4; /* ADC unit B channel number */
7567  vuint16_t:1;
7568  vuint16_t CHA:4; /* ADC unit A channel number */
7569  } B;
7570  } CTU_CLR_DCM_16B_tag;
7571 
7572 
7573  /* Register layout for all registers CLR_SCM... */
7574 
7575  typedef union { /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */
7576  vuint16_t R;
7577  struct {
7578  vuint16_t CIR:1; /* Command Interrupt Request */
7579  vuint16_t LC:1; /* Last Command */
7580  vuint16_t CMS:1; /* Conversion Mode Selection */
7581  vuint16_t FIFO:3; /* FIFO for ADC A/B */
7582  vuint16_t:4;
7583  vuint16_t SU:1; /* Selection ADC Unit */
7584  vuint16_t:1;
7585  vuint16_t CH:4; /* ADC unit channel number */
7586  } B;
7587  } CTU_CLR_SCM_16B_tag;
7588 
7589 
7590  /* Register layout for all registers CLR... */
7591 
7592 
7593  typedef union { /* Control Register */
7594  vuint16_t R;
7595  struct {
7596  vuint16_t EMPTY_CLR7:1; /* Empty Clear 7 */
7597  vuint16_t EMPTY_CLR6:1; /* Empty Clear 6 */
7598  vuint16_t EMPTY_CLR5:1; /* Empty Clear 5 */
7599  vuint16_t EMPTY_CLR4:1; /* Empty Clear 4 */
7600  vuint16_t EMPTY_CLR3:1; /* Empty Clear 3 */
7601  vuint16_t EMPTY_CLR2:1; /* Empty Clear 2 */
7602  vuint16_t EMPTY_CLR1:1; /* Empty Clear 1 */
7603  vuint16_t EMPTY_CLR0:1; /* Empty Clear 0 */
7604 #ifndef USE_FIELD_ALIASES_CTU
7605  vuint16_t DMA_EN7:1; /* Enable DMA interface for FIFO 7 */
7606 #else
7607  vuint16_t DMAEN7:1; /* Enable DMA interface for FIFO 7 */
7608 #endif
7609 #ifndef USE_FIELD_ALIASES_CTU
7610  vuint16_t DMA_EN6:1; /* Enable DMA interface for FIFO 6 */
7611 #else
7612  vuint16_t DMAEN6:1; /* Enable DMA interface for FIFO 6 */
7613 #endif
7614 #ifndef USE_FIELD_ALIASES_CTU
7615  vuint16_t DMA_EN5:1; /* Enable DMA interface for FIFO 5 */
7616 #else
7617  vuint16_t DMAEN5:1; /* Enable DMA interface for FIFO 5 */
7618 #endif
7619 #ifndef USE_FIELD_ALIASES_CTU
7620  vuint16_t DMA_EN4:1; /* Enable DMA interface for FIFO 4 */
7621 #else
7622  vuint16_t DMAEN4:1; /* Enable DMA interface for FIFO 4 */
7623 #endif
7624 #ifndef USE_FIELD_ALIASES_CTU
7625  vuint16_t DMA_EN3:1; /* Enable DMA interface for FIFO 3 */
7626 #else
7627  vuint16_t DMAEN3:1; /* Enable DMA interface for FIFO 3 */
7628 #endif
7629 #ifndef USE_FIELD_ALIASES_CTU
7630  vuint16_t DMA_EN2:1; /* Enable DMA interface for FIFO 2 */
7631 #else
7632  vuint16_t DMAEN2:1; /* Enable DMA interface for FIFO 2 */
7633 #endif
7634 #ifndef USE_FIELD_ALIASES_CTU
7635  vuint16_t DMA_EN1:1; /* Enable DMA interface for FIFO 1 */
7636 #else
7637  vuint16_t DMAEN1:1; /* Enable DMA interface for FIFO 1 */
7638 #endif
7639 #ifndef USE_FIELD_ALIASES_CTU
7640  vuint16_t DMA_EN0:1; /* Enable DMA interface for FIFO 0 */
7641 #else
7642  vuint16_t DMAEN0:1; /* Enable DMA interface for FIFO 0 */
7643 #endif
7644  } B;
7645  } CTU_CR_16B_tag;
7646 
7647  typedef union { /* Control Register FIFO */
7648  vuint32_t R;
7649  struct {
7650  vuint32_t FIFO_OVERRUN_EN7:1; /* FIFO 7 OVERRUN Enable Interrupt */
7651  vuint32_t FIFO_OVERFLOW_EN7:1; /* FIFO 7 OVERFLOW Enable Interrupt */
7652  vuint32_t FIFO_EMPTY_EN7:1; /* FIFO 7 EMPTY Enable Interrupt */
7653  vuint32_t FIFO_FULL_EN7:1; /* FIFO 7 FULL Enable Interrupt */
7654  vuint32_t FIFO_OVERRUN_EN6:1; /* FIFO 6 OVERRUN Enable Interrupt */
7655  vuint32_t FIFO_OVERFLOW_EN6:1; /* FIFO 6 OVERFLOW Enable Interrupt */
7656  vuint32_t FIFO_EMPTY_EN6:1; /* FIFO 6 EMPTY Enable Interrupt */
7657  vuint32_t FIFO_FULL_EN6:1; /* FIFO 6 FULL Enable Interrupt */
7658  vuint32_t FIFO_OVERRUN_EN5:1; /* FIFO 5 OVERRUN Enable Interrupt */
7659  vuint32_t FIFO_OVERFLOW_EN5:1; /* FIFO 5 OVERFLOW Enable Interrupt */
7660  vuint32_t FIFO_EMPTY_EN5:1; /* FIFO 5 EMPTY Enable Interrupt */
7661  vuint32_t FIFO_FULL_EN5:1; /* FIFO 5 FULL Enable Interrupt */
7662  vuint32_t FIFO_OVERRUN_EN4:1; /* FIFO 4 OVERRUN Enable Interrupt */
7663  vuint32_t FIFO_OVERFLOW_EN4:1; /* FIFO 4 OVERFLOW Enable Interrupt */
7664  vuint32_t FIFO_EMPTY_EN4:1; /* FIFO 4 EMPTY Enable Interrupt */
7665  vuint32_t FIFO_FULL_EN4:1; /* FIFO 4 FULL Enable Interrupt */
7666  vuint32_t FIFO_OVERRUN_EN3:1; /* FIFO 3 OVERRUN Enable Interrupt */
7667  vuint32_t FIFO_OVERFLOW_EN3:1; /* FIFO 3 OVERFLOW Enable Interrupt */
7668  vuint32_t FIFO_EMPTY_EN3:1; /* FIFO 3 EMPTY Enable Interrupt */
7669  vuint32_t FIFO_FULL_EN3:1; /* FIFO 3 FULL Enable Interrupt */
7670  vuint32_t FIFO_OVERRUN_EN2:1; /* FIFO 2 OVERRUN Enable Interrupt */
7671  vuint32_t FIFO_OVERFLOW_EN2:1; /* FIFO 2 OVERFLOW Enable Interrupt */
7672  vuint32_t FIFO_EMPTY_EN2:1; /* FIFO 2 EMPTY Enable Interrupt */
7673  vuint32_t FIFO_FULL_EN2:1; /* FIFO 2 FULL Enable Interrupt */
7674  vuint32_t FIFO_OVERRUN_EN1:1; /* FIFO 1 OVERRUN Enable Interrupt */
7675  vuint32_t FIFO_OVERFLOW_EN1:1; /* FIFO 1 OVERFLOW Enable Interrupt */
7676  vuint32_t FIFO_EMPTY_EN1:1; /* FIFO 1 EMPTY Enable Interrupt */
7677  vuint32_t FIFO_FULL_EN1:1; /* FIFO 1 FULL Enable Interrupt */
7678  vuint32_t FIFO_OVERRUN_EN0:1; /* FIFO 0 OVERRUN Enable Interrupt */
7679  vuint32_t FIFO_OVERFLOW_EN0:1; /* FIFO 0 OVERFLOW Enable Interrupt */
7680  vuint32_t FIFO_EMPTY_EN0:1; /* FIFO 0 EMPTY Enable Interrupt */
7681  vuint32_t FIFO_FULL_EN0:1; /* FIFO 0 FULL Enable Interrupt */
7682  } B;
7683  } CTU_FCR_32B_tag;
7684 
7685  typedef union { /* Threshold 1 Register */
7686  vuint32_t R;
7687  struct {
7688 #ifndef USE_FIELD_ALIASES_CTU
7689  vuint32_t TRESHOLD3:8; /* Threshlod FIFO 3 */
7690 #else
7691  vuint32_t THRESHOLD3:8; /* Threshlod FIFO 3 */
7692 #endif
7693 #ifndef USE_FIELD_ALIASES_CTU
7694  vuint32_t TRESHOLD2:8; /* Threshlod FIFO 2 */
7695 #else
7696  vuint32_t THRESHOLD2:8; /* Threshlod FIFO 2 */
7697 #endif
7698 #ifndef USE_FIELD_ALIASES_CTU
7699  vuint32_t TRESHOLD1:8; /* Threshlod FIFO 1 */
7700 #else
7701  vuint32_t THRESHOLD1:8; /* Threshlod FIFO 1 */
7702 #endif
7703 #ifndef USE_FIELD_ALIASES_CTU
7704  vuint32_t TRESHOLD0:8; /* Threshlod FIFO 0 */
7705 #else
7706  vuint32_t THRESHOLD0:8; /* Threshlod FIFO 0 */
7707 #endif
7708  } B;
7709  } CTU_TH1_32B_tag;
7710 
7711  typedef union { /* Threshold 2 Register */
7712  vuint32_t R;
7713  struct {
7714 #ifndef USE_FIELD_ALIASES_CTU
7715  vuint32_t TRESHOLD7:8; /* Threshlod FIFO 7 */
7716 #else
7717  vuint32_t THRESHOLD7:8; /* Threshlod FIFO 7 */
7718 #endif
7719 #ifndef USE_FIELD_ALIASES_CTU
7720  vuint32_t TRESHOLD6:8; /* Threshlod FIFO 6 */
7721 #else
7722  vuint32_t THRESHOLD6:8; /* Threshlod FIFO 6 */
7723 #endif
7724 #ifndef USE_FIELD_ALIASES_CTU
7725  vuint32_t TRESHOLD5:8; /* Threshlod FIFO 5 */
7726 #else
7727  vuint32_t THRESHOLD5:8; /* Threshlod FIFO 5 */
7728 #endif
7729 #ifndef USE_FIELD_ALIASES_CTU
7730  vuint32_t TRESHOLD4:8; /* Threshlod FIFO 4 */
7731 #else
7732  vuint32_t THRESHOLD4:8; /* Threshlod FIFO 4 */
7733 #endif
7734  } B;
7735  } CTU_TH2_32B_tag;
7736 
7737  typedef union { /* Status Register */
7738  vuint32_t R;
7739  struct {
7740  vuint32_t FIFO_OVERRUN7:1; /* FIFO 7 OVERRUN Flag */
7741  vuint32_t FIFO_OVERFLOW7:1; /* FIFO 7 OVERFLOW Flag */
7742  vuint32_t FIFO_EMPTY7:1; /* FIFO 7 EMPTY Flag */
7743  vuint32_t FIFO_FULL7:1; /* FIFO 7 FULL Flag */
7744  vuint32_t FIFO_OVERRUN6:1; /* FIFO 6 OVERRUN Flag */
7745  vuint32_t FIFO_OVERFLOW6:1; /* FIFO 6 OVERFLOW Flag */
7746  vuint32_t FIFO_EMPTY6:1; /* FIFO 6 EMPTY Flag */
7747  vuint32_t FIFO_FULL6:1; /* FIFO 6 FULL Flag */
7748  vuint32_t FIFO_OVERRUN5:1; /* FIFO 5 OVERRUN Flag */
7749  vuint32_t FIFO_OVERFLOW5:1; /* FIFO 5 OVERFLOW Flag */
7750  vuint32_t FIFO_EMPTY5:1; /* FIFO 5 EMPTY Flag */
7751  vuint32_t FIFO_FULL5:1; /* FIFO 5 FULL Flag */
7752  vuint32_t FIFO_OVERRUN4:1; /* FIFO 4 OVERRUN Flag */
7753  vuint32_t FIFO_OVERFLOW4:1; /* FIFO 4 OVERFLOW Flag */
7754  vuint32_t FIFO_EMPTY4:1; /* FIFO 4 EMPTY Flag */
7755  vuint32_t FIFO_FULL4:1; /* FIFO 4 FULL Flag */
7756  vuint32_t FIFO_OVERRUN3:1; /* FIFO 3 OVERRUN Flag */
7757  vuint32_t FIFO_OVERFLOW3:1; /* FIFO 3 OVERFLOW Flag */
7758  vuint32_t FIFO_EMPTY3:1; /* FIFO 3 EMPTY Flag */
7759  vuint32_t FIFO_FULL3:1; /* FIFO 3 FULL Flag */
7760  vuint32_t FIFO_OVERRUN2:1; /* FIFO 2 OVERRUN Flag */
7761  vuint32_t FIFO_OVERFLOW2:1; /* FIFO 2 OVERFLOW Flag */
7762  vuint32_t FIFO_EMPTY2:1; /* FIFO 2 EMPTY Flag */
7763  vuint32_t FIFO_FULL2:1; /* FIFO 2 FULL Flag */
7764  vuint32_t FIFO_OVERRUN1:1; /* FIFO 1 OVERRUN Flag */
7765  vuint32_t FIFO_OVERFLOW1:1; /* FIFO 1 OVERFLOW Flag */
7766  vuint32_t FIFO_EMPTY1:1; /* FIFO 1 EMPTY Flag */
7767  vuint32_t FIFO_FULL1:1; /* FIFO 1 FULL Flag */
7768  vuint32_t FIFO_OVERRUN0:1; /* FIFO 0 OVERRUN Flag */
7769  vuint32_t FIFO_OVERFLOW0:1; /* FIFO 0 OVERFLOW Flag */
7770  vuint32_t FIFO_EMPTY0:1; /* FIFO 0 EMPTY Flag */
7771  vuint32_t FIFO_FULL0:1; /* FIFO 0 FULL Flag */
7772  } B;
7773  } CTU_STS_32B_tag;
7774 
7775 
7776  /* Register layout for all registers FR... */
7777 
7778  typedef union { /* FIFO Right Aligned register */
7779  vuint32_t R;
7780  struct {
7781  vuint32_t:11;
7782  vuint32_t ADC:1; /* ADC Unit */
7783  vuint32_t N_CH:4; /* Number Channel */
7784  vuint32_t:4;
7785  vuint32_t DATA:12; /* Data Fifo */
7786  } B;
7787  } CTU_FR_32B_tag;
7788 
7789 
7790  /* Register layout for all registers FL... */
7791 
7792  typedef union { /* FIFO Left Aligned register */
7793  vuint32_t R;
7794  struct {
7795  vuint32_t:11;
7796  vuint32_t ADC:1; /* ADC Unit */
7797  vuint32_t N_CH:4; /* Number Channel */
7798  vuint32_t:1;
7799  vuint32_t DATA:12; /* Data Fifo */
7800  vuint32_t:3;
7801  } B;
7802  } CTU_FL_32B_tag;
7803 
7804  typedef union { /* CTU Error Flag Register */
7805  vuint16_t R;
7806  struct {
7807  vuint16_t:3;
7808  vuint16_t CS:1; /* Counter Status */
7809  vuint16_t ET_OE:1; /* ExtTrigger Generation Overrun */
7810  vuint16_t ERR_CMP:1; /* Set if counter reaches TGSCCR register */
7811  vuint16_t T4_OE:1; /* Timer4 Generation Overrun */
7812  vuint16_t T3_OE:1; /* Timer3 Generation Overrun */
7813  vuint16_t T2_OE:1; /* Timer2 Generation Overrun */
7814  vuint16_t T1_OE:1; /* Timer1 Generation Overrun */
7815 #ifndef USE_FIELD_ALIASES_CTU
7816  vuint16_t ADC_OE:1; /* ADC Command Generation Overrun */
7817 #else
7818  vuint16_t ADCOE:1; /* ADC Command Generation Overrun */
7819 #endif
7820 #ifndef USE_FIELD_ALIASES_CTU
7821  vuint16_t TGS_OSM:1; /* TGS Overrun */
7822 #else
7823  vuint16_t TGSOSM:1; /* TGS Overrun */
7824 #endif
7825 #ifndef USE_FIELD_ALIASES_CTU
7826  vuint16_t MRS_O:1; /* MRS Overrun */
7827 #else
7828  vuint16_t MRSO:1; /* TGS Overrun */
7829 #endif
7830  vuint16_t ICE:1; /* Invalid Command Error */
7831 #ifndef USE_FIELD_ALIASES_CTU
7832  vuint16_t SM_TO:1; /* Trigger Overrun */
7833 #else
7834  vuint16_t SMTO:1; /* Trigger Overrun */
7835 #endif
7836 #ifndef USE_FIELD_ALIASES_CTU
7837  vuint16_t MRS_RE:1; /* MRS Reload Error */
7838 #else
7839  vuint16_t MRSRE:1; /* MRS Reload Error */
7840 #endif
7841  } B;
7842  } CTU_CTUEFR_16B_tag;
7843 
7844  typedef union { /* CTU Interrupt Flag Register */
7845  vuint16_t R;
7846  struct {
7847  vuint16_t:4;
7848  vuint16_t S_E_B:1; /* Slice time OK */
7849  vuint16_t S_E_A:1; /* Slice time OK */
7850 #ifndef USE_FIELD_ALIASES_CTU
7851  vuint16_t ADC_I:1; /* ADC Command Interrupt Flag */
7852 #else
7853  vuint16_t ADC:1;
7854 #endif
7855 #ifndef USE_FIELD_ALIASES_CTU
7856  vuint16_t T7_I:1; /* Trigger 7 Interrupt Flag */
7857 #else
7858  vuint16_t T7:1;
7859 #endif
7860 #ifndef USE_FIELD_ALIASES_CTU
7861  vuint16_t T6_I:1; /* Trigger 6 Interrupt Flag */
7862 #else
7863  vuint16_t T6:1;
7864 #endif
7865 #ifndef USE_FIELD_ALIASES_CTU
7866  vuint16_t T5_I:1; /* Trigger 5 Interrupt Flag */
7867 #else
7868  vuint16_t T5:1;
7869 #endif
7870 #ifndef USE_FIELD_ALIASES_CTU
7871  vuint16_t T4_I:1; /* Trigger 4 Interrupt Flag */
7872 #else
7873  vuint16_t T4:1;
7874 #endif
7875 #ifndef USE_FIELD_ALIASES_CTU
7876  vuint16_t T3_I:1; /* Trigger 3 Interrupt Flag */
7877 #else
7878  vuint16_t T3:1;
7879 #endif
7880 #ifndef USE_FIELD_ALIASES_CTU
7881  vuint16_t T2_I:1; /* Trigger 2 Interrupt Flag */
7882 #else
7883  vuint16_t T2:1;
7884 #endif
7885 #ifndef USE_FIELD_ALIASES_CTU
7886  vuint16_t T1_I:1; /* Trigger 1 Interrupt Flag */
7887 #else
7888  vuint16_t T1:1;
7889 #endif
7890 #ifndef USE_FIELD_ALIASES_CTU
7891  vuint16_t T0_I:1; /* Trigger 0 Interrupt Flag */
7892 #else
7893  vuint16_t T0:1;
7894 #endif
7895 #ifndef USE_FIELD_ALIASES_CTU
7896  vuint16_t MRS_I:1; /* MRS Interrupt Flag */
7897 #else
7898  vuint16_t MRS:1;
7899 #endif
7900  } B;
7901  } CTU_CTUIFR_16B_tag;
7902 
7903  typedef union { /* CTU Interrupt/DMA Register */
7904  vuint16_t R;
7905  struct {
7906 #ifndef USE_FIELD_ALIASES_CTU
7907  vuint16_t T7_I:1; /* Trigger 7 Interrupt Enable */
7908 #else
7909  vuint16_t T7IE:1;
7910 #endif
7911 #ifndef USE_FIELD_ALIASES_CTU
7912  vuint16_t T6_I:1; /* Trigger 6 Interrupt Enable */
7913 #else
7914  vuint16_t T6IE:1;
7915 #endif
7916 #ifndef USE_FIELD_ALIASES_CTU
7917  vuint16_t T5_I:1; /* Trigger 5 Interrupt Enable */
7918 #else
7919  vuint16_t T5IE:1;
7920 #endif
7921 #ifndef USE_FIELD_ALIASES_CTU
7922  vuint16_t T4_I:1; /* Trigger 4 Interrupt Enable */
7923 #else
7924  vuint16_t T4IE:1;
7925 #endif
7926 #ifndef USE_FIELD_ALIASES_CTU
7927  vuint16_t T3_I:1; /* Trigger 3 Interrupt Enable */
7928 #else
7929  vuint16_t T3IE:1;
7930 #endif
7931 #ifndef USE_FIELD_ALIASES_CTU
7932  vuint16_t T2_I:1; /* Trigger 2 Interrupt Enable */
7933 #else
7934  vuint16_t T2IE:1;
7935 #endif
7936 #ifndef USE_FIELD_ALIASES_CTU
7937  vuint16_t T1_I:1; /* Trigger 1 Interrupt Enable */
7938 #else
7939  vuint16_t T1IE:1;
7940 #endif
7941 #ifndef USE_FIELD_ALIASES_CTU
7942  vuint16_t T0_I:1; /* Trigger 0 Interrupt Enable */
7943 #else
7944  vuint16_t T0IE:1;
7945 #endif
7946  vuint16_t:2;
7947  vuint16_t SAF_CNT_B_EN:1; /* Conversion time counter enabled */
7948  vuint16_t SAF_CNT_A_EN:1; /* Conversion time counter enabled */
7949  vuint16_t DMA_DE:1; /* DMA and gre bit */
7950 #ifndef USE_FIELD_ALIASES_CTU
7951  vuint16_t MRS_DMAE:1; /* DMA Transfer Enable */
7952 #else
7953  vuint16_t MRSDMAE:1;
7954 #endif
7955 #ifndef USE_FIELD_ALIASES_CTU
7956  vuint16_t MRS_IE:1; /* MRS Interrupt Enable */
7957 #else
7958  vuint16_t MRSIE:1;
7959 #endif
7960  vuint16_t IEE:1; /* Interrupt Error Enable */
7961  } B;
7962  } CTU_CTUIR_16B_tag;
7963 
7964  typedef union { /* Control On-Time Register */
7965  vuint16_t R;
7966  struct {
7967  vuint16_t:8;
7968 #ifndef USE_FIELD_ALIASES_CTU
7969  vuint16_t COTR_COTR:8; /* Control On-Time Register and Guard Time */
7970 #else
7971  vuint16_t COTR:8;
7972 #endif
7973  } B;
7974  } CTU_COTR_16B_tag;
7975 
7976  typedef union { /* CTU Control Register */
7977  vuint16_t R;
7978  struct {
7979 #ifndef USE_FIELD_ALIASES_CTU
7980  vuint16_t T7_SG:1; /* Trigger 7 Software Generated */
7981 #else
7982  vuint16_t T7SG:1;
7983 #endif
7984 #ifndef USE_FIELD_ALIASES_CTU
7985  vuint16_t T6_SG:1; /* Trigger 6 Software Generated */
7986 #else
7987  vuint16_t T6SG:1;
7988 #endif
7989 #ifndef USE_FIELD_ALIASES_CTU
7990  vuint16_t T5_SG:1; /* Trigger 5 Software Generated */
7991 #else
7992  vuint16_t T5SG:1;
7993 #endif
7994 #ifndef USE_FIELD_ALIASES_CTU
7995  vuint16_t T4_SG:1; /* Trigger 4 Software Generated */
7996 #else
7997  vuint16_t T4SG:1;
7998 #endif
7999 #ifndef USE_FIELD_ALIASES_CTU
8000  vuint16_t T3_SG:1; /* Trigger 3 Software Generated */
8001 #else
8002  vuint16_t T3SG:1;
8003 #endif
8004 #ifndef USE_FIELD_ALIASES_CTU
8005  vuint16_t T2_SG:1; /* Trigger 2 Software Generated */
8006 #else
8007  vuint16_t T2SG:1;
8008 #endif
8009 #ifndef USE_FIELD_ALIASES_CTU
8010  vuint16_t T1_SG:1; /* Trigger 1 Software Generated */
8011 #else
8012  vuint16_t T1SG:1;
8013 #endif
8014 #ifndef USE_FIELD_ALIASES_CTU
8015  vuint16_t T0_SG:1; /* Trigger 0 Software Generated */
8016 #else
8017  vuint16_t T0SG:1;
8018 #endif
8019 #ifndef USE_FIELD_ALIASES_CTU
8020  vuint16_t CTU_ADC_RESET:1; /* CTU ADC State Machine Reset */
8021 #else
8022  vuint16_t CTUADCRESET:1;
8023 #endif
8024 #ifndef USE_FIELD_ALIASES_CTU
8025  vuint16_t CTU_ODIS:1; /* CTU Output Disable */
8026 #else
8027  vuint16_t CTUODIS:1;
8028 #endif
8029 #ifndef USE_FIELD_ALIASES_CTU
8030  vuint16_t FILTER_EN:1; /* Synchronize Filter Register value */
8031 #else
8032  vuint16_t FILTERENABLE:1;
8033 #endif
8034  vuint16_t CGRE:1; /* Clear GRE */
8035  vuint16_t FGRE:1; /* GRE Flag */
8036 #ifndef USE_FIELD_ALIASES_CTU
8037  vuint16_t MRS_SG:1; /* MRS Software Generated */
8038 #else
8039  vuint16_t MRSSG:1;
8040 #endif
8041  vuint16_t GRE:1; /* General Reload Enable */
8042 #ifndef USE_FIELD_ALIASES_CTU
8043  vuint16_t TGSISR_RE:1; /* TGSISR Reload Enable */
8044 #else
8045  vuint16_t TGSISRRE:1;
8046 #endif
8047  } B;
8048  } CTU_CTUCR_16B_tag;
8049 
8050  typedef union { /* CTU Digital Filter Register */
8051  vuint16_t R;
8052  struct {
8053  vuint16_t:8;
8054 #ifndef USE_FIELD_ALIASES_CTU
8055  vuint16_t FILTER_VALUE:8; /* Filter Value */
8056 #else
8057  vuint16_t FILTERVALUE:8; /* deprecated name - please avoid */
8058 #endif
8059  } B;
8060  } CTU_FILTER_16B_tag;
8061 
8062  typedef union { /* CTU Expected A Value Register */
8063  vuint16_t R;
8064  struct {
8065  vuint16_t EXPECTED_A_VALUE:16; /* Expected A Value */
8066  } B;
8067  } CTU_EXPECTED_A_16B_tag;
8068 
8069  typedef union { /* CTU Expected B Value Register */
8070  vuint16_t R;
8071  struct {
8072  vuint16_t EXPECTED_B_VALUE:16; /* Expected B Value */
8073  } B;
8074  } CTU_EXPECTED_B_16B_tag;
8075 
8076  typedef union { /* CTU Counter Range Register */
8077  vuint16_t R;
8078  struct {
8079  vuint16_t:8;
8080  vuint16_t CNT_RANGE_VALUE:8; /* Counter Range Value */
8081  } B;
8082  } CTU_CNT_RANGE_16B_tag;
8083 
8084 
8085  /* Register layout for generated register(s) FRA... */
8086 
8087  typedef union { /* */
8088  vuint32_t R;
8089  } CTU_FRA_32B_tag;
8090 
8091 
8092  /* Register layout for generated register(s) FLA... */
8093 
8094  typedef union { /* */
8095  vuint32_t R;
8096  } CTU_FLA_32B_tag;
8097 
8098 
8099 
8100  typedef struct CTU_struct_tag { /* start of CTU_tag */
8101  /* Trigger Generator Subunit Input Selection register */
8102  CTU_TGSISR_32B_tag TGSISR; /* offset: 0x0000 size: 32 bit */
8103  /* Trigger Generator Subunit Control Register */
8104  CTU_TGSCR_16B_tag TGSCR; /* offset: 0x0004 size: 16 bit */
8105  union {
8106  CTU_TCR_16B_tag TCR[8]; /* offset: 0x0006 (0x0002 x 8) */
8107 
8108  struct {
8109  CTU_TCR_16B_tag T0CR; /* offset: 0x0006 size: 16 bit */
8110  CTU_TCR_16B_tag T1CR; /* offset: 0x0008 size: 16 bit */
8111  CTU_TCR_16B_tag T2CR; /* offset: 0x000A size: 16 bit */
8112  CTU_TCR_16B_tag T3CR; /* offset: 0x000C size: 16 bit */
8113  CTU_TCR_16B_tag T4CR; /* offset: 0x000E size: 16 bit */
8114  CTU_TCR_16B_tag T5CR; /* offset: 0x0010 size: 16 bit */
8115  CTU_TCR_16B_tag T6CR; /* offset: 0x0012 size: 16 bit */
8116  CTU_TCR_16B_tag T7CR; /* offset: 0x0014 size: 16 bit */
8117  };
8118 
8119  };
8120  /* TGS Counter Compare Register */
8121  CTU_TGSCCR_16B_tag TGSCCR; /* offset: 0x0016 size: 16 bit */
8122  /* TGS Counter Reload Register */
8123  CTU_TGSCRR_16B_tag TGSCRR; /* offset: 0x0018 size: 16 bit */
8124  int8_t CTU_reserved_001A[2];
8125  /* Commands List Control Register 1 */
8126  CTU_CLCR1_32B_tag CLCR1; /* offset: 0x001C size: 32 bit */
8127  /* Commands List Control Register 2 */
8128  CTU_CLCR2_32B_tag CLCR2; /* offset: 0x0020 size: 32 bit */
8129  /* Trigger Handler Control Register 1 */
8130  CTU_THCR1_32B_tag THCR1; /* offset: 0x0024 size: 32 bit */
8131  /* Trigger Handler Control Register 2 */
8132  CTU_THCR2_32B_tag THCR2; /* offset: 0x0028 size: 32 bit */
8133  union {
8134  /* Command List Register. View: BIT13, BIT9 */
8135  CTU_CLR_SCM_16B_tag CLR[24]; /* offset: 0x002C (0x0002 x 24) */ /* deprecated name - please avoid */
8136 
8137  /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */
8138  CTU_CLR_SCM_16B_tag CLR_SCM[24]; /* offset: 0x002C (0x0002 x 24) */
8139 
8140  /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */
8141  CTU_CLR_DCM_16B_tag CLR_DCM[24]; /* offset: 0x002C (0x0002 x 24) */
8142 
8143  struct {
8144  /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */
8145  CTU_CLR_SCM_16B_tag CLR_SCM1; /* offset: 0x002C size: 16 bit */
8146  CTU_CLR_SCM_16B_tag CLR_SCM2; /* offset: 0x002E size: 16 bit */
8147  CTU_CLR_SCM_16B_tag CLR_SCM3; /* offset: 0x0030 size: 16 bit */
8148  CTU_CLR_SCM_16B_tag CLR_SCM4; /* offset: 0x0032 size: 16 bit */
8149  CTU_CLR_SCM_16B_tag CLR_SCM5; /* offset: 0x0034 size: 16 bit */
8150  CTU_CLR_SCM_16B_tag CLR_SCM6; /* offset: 0x0036 size: 16 bit */
8151  CTU_CLR_SCM_16B_tag CLR_SCM7; /* offset: 0x0038 size: 16 bit */
8152  CTU_CLR_SCM_16B_tag CLR_SCM8; /* offset: 0x003A size: 16 bit */
8153  CTU_CLR_SCM_16B_tag CLR_SCM9; /* offset: 0x003C size: 16 bit */
8154  CTU_CLR_SCM_16B_tag CLR_SCM10; /* offset: 0x003E size: 16 bit */
8155  CTU_CLR_SCM_16B_tag CLR_SCM11; /* offset: 0x0040 size: 16 bit */
8156  CTU_CLR_SCM_16B_tag CLR_SCM12; /* offset: 0x0042 size: 16 bit */
8157  CTU_CLR_SCM_16B_tag CLR_SCM13; /* offset: 0x0044 size: 16 bit */
8158  CTU_CLR_SCM_16B_tag CLR_SCM14; /* offset: 0x0046 size: 16 bit */
8159  CTU_CLR_SCM_16B_tag CLR_SCM15; /* offset: 0x0048 size: 16 bit */
8160  CTU_CLR_SCM_16B_tag CLR_SCM16; /* offset: 0x004A size: 16 bit */
8161  CTU_CLR_SCM_16B_tag CLR_SCM17; /* offset: 0x004C size: 16 bit */
8162  CTU_CLR_SCM_16B_tag CLR_SCM18; /* offset: 0x004E size: 16 bit */
8163  CTU_CLR_SCM_16B_tag CLR_SCM19; /* offset: 0x0050 size: 16 bit */
8164  CTU_CLR_SCM_16B_tag CLR_SCM20; /* offset: 0x0052 size: 16 bit */
8165  CTU_CLR_SCM_16B_tag CLR_SCM21; /* offset: 0x0054 size: 16 bit */
8166  CTU_CLR_SCM_16B_tag CLR_SCM22; /* offset: 0x0056 size: 16 bit */
8167  CTU_CLR_SCM_16B_tag CLR_SCM23; /* offset: 0x0058 size: 16 bit */
8168  CTU_CLR_SCM_16B_tag CLR_SCM24; /* offset: 0x005A size: 16 bit */
8169  };
8170 
8171  struct {
8172  /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */
8173  CTU_CLR_DCM_16B_tag CLR_DCM1; /* offset: 0x002C size: 16 bit */
8174  CTU_CLR_DCM_16B_tag CLR_DCM2; /* offset: 0x002E size: 16 bit */
8175  CTU_CLR_DCM_16B_tag CLR_DCM3; /* offset: 0x0030 size: 16 bit */
8176  CTU_CLR_DCM_16B_tag CLR_DCM4; /* offset: 0x0032 size: 16 bit */
8177  CTU_CLR_DCM_16B_tag CLR_DCM5; /* offset: 0x0034 size: 16 bit */
8178  CTU_CLR_DCM_16B_tag CLR_DCM6; /* offset: 0x0036 size: 16 bit */
8179  CTU_CLR_DCM_16B_tag CLR_DCM7; /* offset: 0x0038 size: 16 bit */
8180  CTU_CLR_DCM_16B_tag CLR_DCM8; /* offset: 0x003A size: 16 bit */
8181  CTU_CLR_DCM_16B_tag CLR_DCM9; /* offset: 0x003C size: 16 bit */
8182  CTU_CLR_DCM_16B_tag CLR_DCM10; /* offset: 0x003E size: 16 bit */
8183  CTU_CLR_DCM_16B_tag CLR_DCM11; /* offset: 0x0040 size: 16 bit */
8184  CTU_CLR_DCM_16B_tag CLR_DCM12; /* offset: 0x0042 size: 16 bit */
8185  CTU_CLR_DCM_16B_tag CLR_DCM13; /* offset: 0x0044 size: 16 bit */
8186  CTU_CLR_DCM_16B_tag CLR_DCM14; /* offset: 0x0046 size: 16 bit */
8187  CTU_CLR_DCM_16B_tag CLR_DCM15; /* offset: 0x0048 size: 16 bit */
8188  CTU_CLR_DCM_16B_tag CLR_DCM16; /* offset: 0x004A size: 16 bit */
8189  CTU_CLR_DCM_16B_tag CLR_DCM17; /* offset: 0x004C size: 16 bit */
8190  CTU_CLR_DCM_16B_tag CLR_DCM18; /* offset: 0x004E size: 16 bit */
8191  CTU_CLR_DCM_16B_tag CLR_DCM19; /* offset: 0x0050 size: 16 bit */
8192  CTU_CLR_DCM_16B_tag CLR_DCM20; /* offset: 0x0052 size: 16 bit */
8193  CTU_CLR_DCM_16B_tag CLR_DCM21; /* offset: 0x0054 size: 16 bit */
8194  CTU_CLR_DCM_16B_tag CLR_DCM22; /* offset: 0x0056 size: 16 bit */
8195  CTU_CLR_DCM_16B_tag CLR_DCM23; /* offset: 0x0058 size: 16 bit */
8196  CTU_CLR_DCM_16B_tag CLR_DCM24; /* offset: 0x005A size: 16 bit */
8197  };
8198 
8199  };
8200  int8_t CTU_reserved_005C[16];
8201  /* Control Register */
8202  CTU_CR_16B_tag CR; /* offset: 0x006C size: 16 bit */
8203  int8_t CTU_reserved_006E[2];
8204  /* Control Register FIFO */
8205  CTU_FCR_32B_tag FCR; /* offset: 0x0070 size: 32 bit */
8206  /* Threshold 1 Register */
8207  CTU_TH1_32B_tag TH1; /* offset: 0x0074 size: 32 bit */
8208  /* Threshold 2 Register */
8209  CTU_TH2_32B_tag TH2; /* offset: 0x0078 size: 32 bit */
8210  union {
8211  /* Status Register */
8212  CTU_STS_32B_tag STS; /* offset: 0x007C size: 32 bit */
8213 
8214  CTU_STS_32B_tag STATUS; /* deprecated - please avoid */
8215 
8216  };
8217  union {
8218  CTU_FRA_32B_tag FRA[8]; /* offset: 0x0080 (0x0004 x 8) */
8219 
8220  /* FIFO Right Aligned register */
8221  CTU_FR_32B_tag FR[8]; /* offset: 0x0080 (0x0004 x 8) */
8222 
8223  struct {
8224  /* FIFO Right Aligned register */
8225  CTU_FR_32B_tag FR0; /* offset: 0x0080 size: 32 bit */
8226  CTU_FR_32B_tag FR1; /* offset: 0x0084 size: 32 bit */
8227  CTU_FR_32B_tag FR2; /* offset: 0x0088 size: 32 bit */
8228  CTU_FR_32B_tag FR3; /* offset: 0x008C size: 32 bit */
8229  CTU_FR_32B_tag FR4; /* offset: 0x0090 size: 32 bit */
8230  CTU_FR_32B_tag FR5; /* offset: 0x0094 size: 32 bit */
8231  CTU_FR_32B_tag FR6; /* offset: 0x0098 size: 32 bit */
8232  CTU_FR_32B_tag FR7; /* offset: 0x009C size: 32 bit */
8233  };
8234 
8235  };
8236  union {
8237  CTU_FLA_32B_tag FLA[8]; /* offset: 0x00A0 (0x0004 x 8) */
8238 
8239  /* FIFO Left Aligned register */
8240  CTU_FL_32B_tag FL[8]; /* offset: 0x00A0 (0x0004 x 8) */
8241 
8242  struct {
8243  /* FIFO Left Aligned register */
8244  CTU_FL_32B_tag FL0; /* offset: 0x00A0 size: 32 bit */
8245  CTU_FL_32B_tag FL1; /* offset: 0x00A4 size: 32 bit */
8246  CTU_FL_32B_tag FL2; /* offset: 0x00A8 size: 32 bit */
8247  CTU_FL_32B_tag FL3; /* offset: 0x00AC size: 32 bit */
8248  CTU_FL_32B_tag FL4; /* offset: 0x00B0 size: 32 bit */
8249  CTU_FL_32B_tag FL5; /* offset: 0x00B4 size: 32 bit */
8250  CTU_FL_32B_tag FL6; /* offset: 0x00B8 size: 32 bit */
8251  CTU_FL_32B_tag FL7; /* offset: 0x00BC size: 32 bit */
8252  };
8253 
8254  };
8255  /* CTU Error Flag Register */
8256  CTU_CTUEFR_16B_tag CTUEFR; /* offset: 0x00C0 size: 16 bit */
8257  /* CTU Interrupt Flag Register */
8258  CTU_CTUIFR_16B_tag CTUIFR; /* offset: 0x00C2 size: 16 bit */
8259  /* CTU Interrupt/DMA Register */
8260  CTU_CTUIR_16B_tag CTUIR; /* offset: 0x00C4 size: 16 bit */
8261  /* Control On-Time Register */
8262  CTU_COTR_16B_tag COTR; /* offset: 0x00C6 size: 16 bit */
8263  /* CTU Control Register */
8264  CTU_CTUCR_16B_tag CTUCR; /* offset: 0x00C8 size: 16 bit */
8265  union {
8266  /* CTU Digital Filter Register */
8267  CTU_FILTER_16B_tag FILTER; /* offset: 0x00CA size: 16 bit */
8268 
8269  CTU_FILTER_16B_tag CTUFILTER; /* deprecated - please avoid */
8270 
8271  };
8272  /* CTU Expected A Value Register */
8273  CTU_EXPECTED_A_16B_tag EXPECTED_A; /* offset: 0x00CC size: 16 bit */
8274 
8275  /* CTU Expected B Value Register */
8276  CTU_EXPECTED_B_16B_tag EXPECTED_B; /* offset: 0x00CE size: 16 bit */
8277  /* CTU Counter Range Register */
8278  CTU_CNT_RANGE_16B_tag CNT_RANGE; /* offset: 0x00D0 size: 16 bit */
8279  } CTU_tag;
8280 
8281 
8282 #define CTU (*(volatile CTU_tag *) 0xFFE0C000UL)
8283 
8284 
8285 
8286 /****************************************************************/
8287 /* */
8288 /* Module: mcTIMER */
8289 /* */
8290 /****************************************************************/
8291 
8292 
8293  /* Register layout for all registers COMP1... */
8294 
8295  typedef union { /* Compare Register 1 */
8296  vuint16_t R;
8297  struct {
8298  vuint16_t COMP1:16; /* deprecated definition -- do not use */
8299  } B;
8300  } mcTIMER_COMP1_16B_tag;
8301 
8302 
8303  /* Register layout for all registers COMP2... */
8304 
8305  typedef union { /* Compare Register 2 */
8306  vuint16_t R;
8307  struct {
8308  vuint16_t COMP2:16; /* deprecated definition -- do not use */
8309  } B;
8310  } mcTIMER_COMP2_16B_tag;
8311 
8312 
8313  /* Register layout for all registers CAPT1... */
8314 
8315  typedef union { /* Capture Register 1 */
8316  vuint16_t R;
8317  struct {
8318  vuint16_t CAPT1:16; /* deprecated definition -- do not use */
8319  } B;
8320  } mcTIMER_CAPT1_16B_tag;
8321 
8322 
8323  /* Register layout for all registers CAPT2... */
8324 
8325  typedef union { /* Capture Register 2 */
8326  vuint16_t R;
8327  struct {
8328  vuint16_t CAPT2:16; /* deprecated definition -- do not use */
8329  } B;
8330  } mcTIMER_CAPT2_16B_tag;
8331 
8332 
8333  /* Register layout for all registers LOAD... */
8334 
8335  typedef union { /* Load Register */
8336  vuint16_t R;
8337  struct {
8338  vuint16_t LOAD:16; /* deprecated definition -- do not use */
8339  } B;
8340  } mcTIMER_LOAD_16B_tag;
8341 
8342 
8343  /* Register layout for all registers HOLD... */
8344 
8345  typedef union { /* Hold Register */
8346  vuint16_t R;
8347  struct {
8348  vuint16_t HOLD:16; /* deprecated definition -- do not use */
8349  } B;
8350  } mcTIMER_HOLD_16B_tag;
8351 
8352 
8353  /* Register layout for all registers CNTR... */
8354 
8355  typedef union { /* Counter Register */
8356  vuint16_t R;
8357  struct {
8358  vuint16_t CNTR:16; /* deprecated definition -- do not use */
8359  } B;
8360  } mcTIMER_CNTR_16B_tag;
8361 
8362 
8363  /* Register layout for all registers CTRL1... */
8364 
8365  typedef union { /* Control Register */
8366  vuint16_t R;
8367  struct {
8368  vuint16_t CNTMODE:3; /* Count Mode */
8369  vuint16_t PRISRC:5; /* Primary Count Source */
8370  vuint16_t ONCE:1; /* Count Once */
8371  vuint16_t LENGTH:1; /* Count Length */
8372  vuint16_t DIR:1; /* Count Direction */
8373  vuint16_t SECSRC:5; /* Secondary Count Source */
8374  } B;
8375  } mcTIMER_CTRL1_16B_tag;
8376 
8377 
8378  /* Register layout for all registers CTRL2... */
8379 
8380  typedef union { /* Control Register 2 */
8381  vuint16_t R;
8382  struct {
8383  vuint16_t OEN:1; /* Output Enable */
8384  vuint16_t RDNT:1; /* Redundant Channel Enable */
8385  vuint16_t INPUT:1; /* External Input Signal */
8386  vuint16_t VAL:1; /* Forced OFLAG Value */
8387  vuint16_t FORCE:1; /* Force the OFLAG output */
8388  vuint16_t COFRC:1; /* Co-channel OFLAG Force */
8389  vuint16_t COINIT:2; /* Co-channel Initialization */
8390  vuint16_t SIPS:1; /* Secondary Source Input Polarity Select */
8391  vuint16_t PIPS:1; /* Primary Source Input Polarity Select */
8392  vuint16_t OPS:1; /* Output Polarity Select */
8393  vuint16_t MSTR:1; /* Master Mode */
8394  vuint16_t OUTMODE:4; /* Output Mode */
8395  } B;
8396  } mcTIMER_CTRL2_16B_tag;
8397 
8398 
8399  /* Register layout for all registers CTRL3... */
8400 
8401  typedef union { /* Control Register 3 */
8402  vuint16_t R;
8403  struct {
8404  vuint16_t STPEN:1; /* Stop Action Enable */
8405  vuint16_t ROC:2; /* Reload On Capture */
8406  vuint16_t FMODE:1; /* Fault Safing Mode */
8407  vuint16_t FDIS:4; /* Fault Disable Mask */
8408  vuint16_t C2FCNT:3; /* CAPT2 FIFO Word Count */
8409  vuint16_t C1FCNT:3; /* CAPT1 FIFO Word Count */
8410  vuint16_t DBGEN:2; /* Debug Actions Enable */
8411  } B;
8412  } mcTIMER_CTRL3_16B_tag;
8413 
8414 
8415  /* Register layout for all registers STS... */
8416 
8417  typedef union { /* Status Register */
8418  vuint16_t R;
8419  struct {
8420  vuint16_t:6;
8421  vuint16_t WDF:1; /* Watchdog Time-out Flag */
8422  vuint16_t RCF:1; /* Redundant Channel Flag */
8423  vuint16_t ICF2:1; /* Input Capture 2 Flag */
8424  vuint16_t ICF1:1; /* Input Capture 1 Flag */
8425  vuint16_t IEHF:1; /* Input Edge High Flag */
8426  vuint16_t IELF:1; /* Input Edge Low Flag */
8427  vuint16_t TOF:1; /* Timer Overflow Flag */
8428  vuint16_t TCF2:1; /* Timer Compare 2 Flag */
8429  vuint16_t TCF1:1; /* Timer Compare 1 Flag */
8430  vuint16_t TCF:1; /* Timer Compare Flag */
8431  } B;
8432  } mcTIMER_STS_16B_tag;
8433 
8434 
8435  /* Register layout for all registers INTDMA... */
8436 
8437  typedef union { /* Interrupt and DMA Enable Register */
8438  vuint16_t R;
8439  struct {
8440  vuint16_t ICF2DE:1; /* Input Capture 2 Flag DMA Enable */
8441  vuint16_t ICF1DE:1; /* Input Capture 1 Flag DMA Enable */
8442  vuint16_t CMPLD2DE:1; /* Comparator Load Register 2 Flag DMA Enable */
8443  vuint16_t CMPLD1DE:1; /* Comparator Load Register 1 Flag DMA Enable */
8444  vuint16_t:2;
8445  vuint16_t WDFIE:1; /* Watchdog Flag Interrupt Enable */
8446  vuint16_t RCFIE:1; /* Redundant Channel Flag Interrupt Enable */
8447  vuint16_t ICF2IE:1; /* Input Capture 2 Flag Interrupt Enable */
8448  vuint16_t ICF1IE:1; /* Input Capture 1 Flag Interrupt Enable */
8449  vuint16_t IEHFIE:1; /* Input Edge High Flag Interrupt Enable */
8450  vuint16_t IELFIE:1; /* Input Edge Low Flag Interrupt Enable */
8451  vuint16_t TOFIE:1; /* Timer Overflow Flag Interrupt Enable */
8452  vuint16_t TCF2IE:1; /* Timer Compare 2 Flag Interrupt Enable */
8453  vuint16_t TCF1IE:1; /* Timer Compare 1 Flag Interrupt Enable */
8454  vuint16_t TCFIE:1; /* Timer Compare Flag Interrupt Enable */
8455  } B;
8456  } mcTIMER_INTDMA_16B_tag;
8457 
8458 
8459  /* Register layout for all registers CMPLD1... */
8460 
8461  typedef union { /* Comparator Load Register 1 */
8462  vuint16_t R;
8463  struct {
8464  vuint16_t CMPLD1:16; /* deprecated definition -- do not use */
8465  } B;
8466  } mcTIMER_CMPLD1_16B_tag;
8467 
8468 
8469  /* Register layout for all registers CMPLD2... */
8470 
8471  typedef union { /* Comparator Load Register 2 */
8472  vuint16_t R;
8473  struct {
8474  vuint16_t CMPLD2:16; /* deprecated definition -- do not use */
8475  } B;
8476  } mcTIMER_CMPLD2_16B_tag;
8477 
8478 
8479  /* Register layout for all registers CCCTRL... */
8480 
8481  typedef union { /* Compare and Capture Control Register */
8482  vuint16_t R;
8483  struct {
8484  vuint16_t CLC2:3; /* Compare Load Control 2 */
8485  vuint16_t CLC1:3; /* Compare Load Control 1 */
8486  vuint16_t CMPMODE:2; /* Compare Mode */
8487  vuint16_t CPT2MODE:2; /* Capture 2 Mode Control */
8488  vuint16_t CPT1MODE:2; /* Capture 1 Mode Control */
8489  vuint16_t CFWM:2; /* Capture FIFO Water Mark */
8490  vuint16_t ONESHOT:1; /* One Shot Capture Mode */
8491  vuint16_t ARM:1; /* Arm Capture */
8492  } B;
8493  } mcTIMER_CCCTRL_16B_tag;
8494 
8495 
8496  /* Register layout for all registers FILT... */
8497 
8498  typedef union { /* Input Filter Register */
8499  vuint16_t R;
8500  struct {
8501  vuint16_t:5;
8502 #ifndef USE_FIELD_ALIASES_mcTIMER
8503  vuint16_t FILT_CNT:3; /* Input Filter Sample Count */
8504 #else
8505  vuint16_t FILTCNT:3; /* deprecated name - please avoid */
8506 #endif
8507 #ifndef USE_FIELD_ALIASES_mcTIMER
8508  vuint16_t FILT_PER:8; /* Input Filter Sample Period */
8509 #else
8510  vuint16_t FILTPER:8; /* deprecated name - please avoid */
8511 #endif
8512  } B;
8513  } mcTIMER_FILT_16B_tag;
8514 
8515  typedef union { /* Watchdog Time-out Register */
8516  vuint16_t R;
8517  struct {
8518  vuint16_t WDTOL:16; /* deprecated definition -- do not use */
8519  } B;
8520  } mcTIMER_WDTOL_16B_tag;
8521 
8522  typedef union { /* Watchdog Time-out Register */
8523  vuint16_t R;
8524  struct {
8525  vuint16_t WDTOH:16; /* deprecated definition -- do not use */
8526  } B;
8527  } mcTIMER_WDTOH_16B_tag;
8528 
8529  typedef union { /* Fault Control Register */
8530  vuint16_t R;
8531  struct {
8532  vuint16_t:3;
8533  vuint16_t FTEST:1; /* Fault Test */
8534  vuint16_t FIE:4; /* Fault Interrupt Enable */
8535  vuint16_t:4;
8536  vuint16_t FLVL:4; /* Fault Active Logic Level */
8537  } B;
8538  } mcTIMER_FCTRL_16B_tag;
8539 
8540  typedef union { /* Fault Status Register */
8541  vuint16_t R;
8542  struct {
8543  vuint16_t:4;
8544  vuint16_t FFPIN:4; /* Filtered Fault Pin */
8545  vuint16_t:4;
8546  vuint16_t FFLAG:4; /* Fault Flag */
8547  } B;
8548  } mcTIMER_FSTS_16B_tag;
8549 
8550  typedef union { /* Fault Filter Registers */
8551  vuint16_t R;
8552  struct {
8553  vuint16_t:5;
8554 #ifndef USE_FIELD_ALIASES_mcTIMER
8555  vuint16_t FFPIN:3; /* Fault Filter Sample Count */
8556 #else
8557  vuint16_t FFILTCNT:3; /* deprecated name - please avoid */
8558 #endif
8559 #ifndef USE_FIELD_ALIASES_mcTIMER
8560  vuint16_t FFILT_PER:8; /* Fault Filter Sample Period */
8561 #else
8562  vuint16_t FFILTPER:8; /* deprecated name - please avoid */
8563 #endif
8564  } B;
8565  } mcTIMER_FFILT_16B_tag;
8566 
8567  typedef union { /* Channel Enable Registers */
8568  vuint16_t R;
8569  struct {
8570  vuint16_t:8;
8571  vuint16_t ENBL:8; /* Timer Channel Enable */
8572  } B;
8573  } mcTIMER_ENBL_16B_tag;
8574 
8575  typedef union { /* DMA Request 0 Select Registers */
8576  vuint16_t R;
8577  struct {
8578  vuint16_t:11;
8579  vuint16_t DREQ0V:5; /* DMA Request Select */
8580  } B;
8581  } mcTIMER_DREQ0_16B_tag;
8582 
8583  typedef union { /* DMA Request 1 Select Registers */
8584  vuint16_t R;
8585  struct {
8586  vuint16_t:11;
8587  vuint16_t DREQ1V:5; /* DMA Request Select */
8588  } B;
8589  } mcTIMER_DREQ1_16B_tag;
8590 
8591  typedef union { /* DMA Request 2 Select Registers */
8592  vuint16_t R;
8593  struct {
8594  vuint16_t:11;
8595  vuint16_t DREQ2V:5; /* DMA Request Select */
8596  } B;
8597  } mcTIMER_DREQ2_16B_tag;
8598 
8599  typedef union { /* DMA Request 3 Select Registers */
8600  vuint16_t R;
8601  struct {
8602  vuint16_t:11;
8603  vuint16_t DREQ3V:5; /* DMA Request Select */
8604  } B;
8605  } mcTIMER_DREQ3_16B_tag;
8606 
8607 
8608  /* Register layout for generated register(s) DREQ... */
8609 
8610  typedef union { /* */
8611  vuint16_t R;
8612  } mcTIMER_DREQ_16B_tag;
8613 
8614 
8615  typedef struct mcTIMER_CHANNEL_struct_tag {
8616 
8617  /* Compare Register 1 */
8618  mcTIMER_COMP1_16B_tag COMP1; /* relative offset: 0x0000 */
8619  /* Compare Register 2 */
8620  mcTIMER_COMP2_16B_tag COMP2; /* relative offset: 0x0002 */
8621  /* Capture Register 1 */
8622  mcTIMER_CAPT1_16B_tag CAPT1; /* relative offset: 0x0004 */
8623  /* Capture Register 2 */
8624  mcTIMER_CAPT2_16B_tag CAPT2; /* relative offset: 0x0006 */
8625  /* Load Register */
8626  mcTIMER_LOAD_16B_tag LOAD; /* relative offset: 0x0008 */
8627  /* Hold Register */
8628  mcTIMER_HOLD_16B_tag HOLD; /* relative offset: 0x000A */
8629  /* Counter Register */
8630  mcTIMER_CNTR_16B_tag CNTR; /* relative offset: 0x000C */
8631  union {
8632  /* Control Register */
8633  mcTIMER_CTRL1_16B_tag CTRL1; /* relative offset: 0x000E */
8634  mcTIMER_CTRL1_16B_tag CTRL; /* deprecated - please avoid */
8635  };
8636  /* Control Register 2 */
8637  mcTIMER_CTRL2_16B_tag CTRL2; /* relative offset: 0x0010 */
8638  /* Control Register 3 */
8639  mcTIMER_CTRL3_16B_tag CTRL3; /* relative offset: 0x0012 */
8640  /* Status Register */
8641  mcTIMER_STS_16B_tag STS; /* relative offset: 0x0014 */
8642  /* Interrupt and DMA Enable Register */
8643  mcTIMER_INTDMA_16B_tag INTDMA; /* relative offset: 0x0016 */
8644  /* Comparator Load Register 1 */
8645  mcTIMER_CMPLD1_16B_tag CMPLD1; /* relative offset: 0x0018 */
8646  /* Comparator Load Register 2 */
8647  mcTIMER_CMPLD2_16B_tag CMPLD2; /* relative offset: 0x001A */
8648  /* Compare and Capture Control Register */
8649  mcTIMER_CCCTRL_16B_tag CCCTRL; /* relative offset: 0x001C */
8650  /* Input Filter Register */
8651  mcTIMER_FILT_16B_tag FILT; /* relative offset: 0x001E */
8652 
8653  } mcTIMER_CHANNEL_tag;
8654 
8655 
8656  typedef struct mcTIMER_struct_tag { /* start of mcTIMER_tag */
8657  union {
8658  /* Register set CHANNEL */
8659  mcTIMER_CHANNEL_tag CHANNEL[6]; /* offset: 0x0000 (0x0020 x 6) */
8660 
8661  struct {
8662  /* Compare Register 1 */
8663  mcTIMER_COMP1_16B_tag COMP10; /* offset: 0x0000 size: 16 bit */
8664  /* Compare Register 2 */
8665  mcTIMER_COMP2_16B_tag COMP20; /* offset: 0x0002 size: 16 bit */
8666  /* Capture Register 1 */
8667  mcTIMER_CAPT1_16B_tag CAPT10; /* offset: 0x0004 size: 16 bit */
8668  /* Capture Register 2 */
8669  mcTIMER_CAPT2_16B_tag CAPT20; /* offset: 0x0006 size: 16 bit */
8670  /* Load Register */
8671  mcTIMER_LOAD_16B_tag LOAD0; /* offset: 0x0008 size: 16 bit */
8672  /* Hold Register */
8673  mcTIMER_HOLD_16B_tag HOLD0; /* offset: 0x000A size: 16 bit */
8674  /* Counter Register */
8675  mcTIMER_CNTR_16B_tag CNTR0; /* offset: 0x000C size: 16 bit */
8676  /* Control Register */
8677  mcTIMER_CTRL1_16B_tag CTRL10; /* offset: 0x000E size: 16 bit */
8678  /* Control Register 2 */
8679  mcTIMER_CTRL2_16B_tag CTRL20; /* offset: 0x0010 size: 16 bit */
8680  /* Control Register 3 */
8681  mcTIMER_CTRL3_16B_tag CTRL30; /* offset: 0x0012 size: 16 bit */
8682  /* Status Register */
8683  mcTIMER_STS_16B_tag STS0; /* offset: 0x0014 size: 16 bit */
8684  /* Interrupt and DMA Enable Register */
8685  mcTIMER_INTDMA_16B_tag INTDMA0; /* offset: 0x0016 size: 16 bit */
8686  /* Comparator Load Register 1 */
8687  mcTIMER_CMPLD1_16B_tag CMPLD10; /* offset: 0x0018 size: 16 bit */
8688  /* Comparator Load Register 2 */
8689  mcTIMER_CMPLD2_16B_tag CMPLD20; /* offset: 0x001A size: 16 bit */
8690  /* Compare and Capture Control Register */
8691  mcTIMER_CCCTRL_16B_tag CCCTRL0; /* offset: 0x001C size: 16 bit */
8692  /* Input Filter Register */
8693  mcTIMER_FILT_16B_tag FILT0; /* offset: 0x001E size: 16 bit */
8694  /* Compare Register 1 */
8695  mcTIMER_COMP1_16B_tag COMP11; /* offset: 0x0020 size: 16 bit */
8696  /* Compare Register 2 */
8697  mcTIMER_COMP2_16B_tag COMP21; /* offset: 0x0022 size: 16 bit */
8698  /* Capture Register 1 */
8699  mcTIMER_CAPT1_16B_tag CAPT11; /* offset: 0x0024 size: 16 bit */
8700  /* Capture Register 2 */
8701  mcTIMER_CAPT2_16B_tag CAPT21; /* offset: 0x0026 size: 16 bit */
8702  /* Load Register */
8703  mcTIMER_LOAD_16B_tag LOAD1; /* offset: 0x0028 size: 16 bit */
8704  /* Hold Register */
8705  mcTIMER_HOLD_16B_tag HOLD1; /* offset: 0x002A size: 16 bit */
8706  /* Counter Register */
8707  mcTIMER_CNTR_16B_tag CNTR1; /* offset: 0x002C size: 16 bit */
8708  /* Control Register */
8709  mcTIMER_CTRL1_16B_tag CTRL11; /* offset: 0x002E size: 16 bit */
8710  /* Control Register 2 */
8711  mcTIMER_CTRL2_16B_tag CTRL21; /* offset: 0x0030 size: 16 bit */
8712  /* Control Register 3 */
8713  mcTIMER_CTRL3_16B_tag CTRL31; /* offset: 0x0032 size: 16 bit */
8714  /* Status Register */
8715  mcTIMER_STS_16B_tag STS1; /* offset: 0x0034 size: 16 bit */
8716  /* Interrupt and DMA Enable Register */
8717  mcTIMER_INTDMA_16B_tag INTDMA1; /* offset: 0x0036 size: 16 bit */
8718  /* Comparator Load Register 1 */
8719  mcTIMER_CMPLD1_16B_tag CMPLD11; /* offset: 0x0038 size: 16 bit */
8720  /* Comparator Load Register 2 */
8721  mcTIMER_CMPLD2_16B_tag CMPLD21; /* offset: 0x003A size: 16 bit */
8722  /* Compare and Capture Control Register */
8723  mcTIMER_CCCTRL_16B_tag CCCTRL1; /* offset: 0x003C size: 16 bit */
8724  /* Input Filter Register */
8725  mcTIMER_FILT_16B_tag FILT1; /* offset: 0x003E size: 16 bit */
8726  /* Compare Register 1 */
8727  mcTIMER_COMP1_16B_tag COMP12; /* offset: 0x0040 size: 16 bit */
8728  /* Compare Register 2 */
8729  mcTIMER_COMP2_16B_tag COMP22; /* offset: 0x0042 size: 16 bit */
8730  /* Capture Register 1 */
8731  mcTIMER_CAPT1_16B_tag CAPT12; /* offset: 0x0044 size: 16 bit */
8732  /* Capture Register 2 */
8733  mcTIMER_CAPT2_16B_tag CAPT22; /* offset: 0x0046 size: 16 bit */
8734  /* Load Register */
8735  mcTIMER_LOAD_16B_tag LOAD2; /* offset: 0x0048 size: 16 bit */
8736  /* Hold Register */
8737  mcTIMER_HOLD_16B_tag HOLD2; /* offset: 0x004A size: 16 bit */
8738  /* Counter Register */
8739  mcTIMER_CNTR_16B_tag CNTR2; /* offset: 0x004C size: 16 bit */
8740  /* Control Register */
8741  mcTIMER_CTRL1_16B_tag CTRL12; /* offset: 0x004E size: 16 bit */
8742  /* Control Register 2 */
8743  mcTIMER_CTRL2_16B_tag CTRL22; /* offset: 0x0050 size: 16 bit */
8744  /* Control Register 3 */
8745  mcTIMER_CTRL3_16B_tag CTRL32; /* offset: 0x0052 size: 16 bit */
8746  /* Status Register */
8747  mcTIMER_STS_16B_tag STS2; /* offset: 0x0054 size: 16 bit */
8748  /* Interrupt and DMA Enable Register */
8749  mcTIMER_INTDMA_16B_tag INTDMA2; /* offset: 0x0056 size: 16 bit */
8750  /* Comparator Load Register 1 */
8751  mcTIMER_CMPLD1_16B_tag CMPLD12; /* offset: 0x0058 size: 16 bit */
8752  /* Comparator Load Register 2 */
8753  mcTIMER_CMPLD2_16B_tag CMPLD22; /* offset: 0x005A size: 16 bit */
8754  /* Compare and Capture Control Register */
8755  mcTIMER_CCCTRL_16B_tag CCCTRL2; /* offset: 0x005C size: 16 bit */
8756  /* Input Filter Register */
8757  mcTIMER_FILT_16B_tag FILT2; /* offset: 0x005E size: 16 bit */
8758  /* Compare Register 1 */
8759  mcTIMER_COMP1_16B_tag COMP13; /* offset: 0x0060 size: 16 bit */
8760  /* Compare Register 2 */
8761  mcTIMER_COMP2_16B_tag COMP23; /* offset: 0x0062 size: 16 bit */
8762  /* Capture Register 1 */
8763  mcTIMER_CAPT1_16B_tag CAPT13; /* offset: 0x0064 size: 16 bit */
8764  /* Capture Register 2 */
8765  mcTIMER_CAPT2_16B_tag CAPT23; /* offset: 0x0066 size: 16 bit */
8766  /* Load Register */
8767  mcTIMER_LOAD_16B_tag LOAD3; /* offset: 0x0068 size: 16 bit */
8768  /* Hold Register */
8769  mcTIMER_HOLD_16B_tag HOLD3; /* offset: 0x006A size: 16 bit */
8770  /* Counter Register */
8771  mcTIMER_CNTR_16B_tag CNTR3; /* offset: 0x006C size: 16 bit */
8772  /* Control Register */
8773  mcTIMER_CTRL1_16B_tag CTRL13; /* offset: 0x006E size: 16 bit */
8774  /* Control Register 2 */
8775  mcTIMER_CTRL2_16B_tag CTRL23; /* offset: 0x0070 size: 16 bit */
8776  /* Control Register 3 */
8777  mcTIMER_CTRL3_16B_tag CTRL33; /* offset: 0x0072 size: 16 bit */
8778  /* Status Register */
8779  mcTIMER_STS_16B_tag STS3; /* offset: 0x0074 size: 16 bit */
8780  /* Interrupt and DMA Enable Register */
8781  mcTIMER_INTDMA_16B_tag INTDMA3; /* offset: 0x0076 size: 16 bit */
8782  /* Comparator Load Register 1 */
8783  mcTIMER_CMPLD1_16B_tag CMPLD13; /* offset: 0x0078 size: 16 bit */
8784  /* Comparator Load Register 2 */
8785  mcTIMER_CMPLD2_16B_tag CMPLD23; /* offset: 0x007A size: 16 bit */
8786  /* Compare and Capture Control Register */
8787  mcTIMER_CCCTRL_16B_tag CCCTRL3; /* offset: 0x007C size: 16 bit */
8788  /* Input Filter Register */
8789  mcTIMER_FILT_16B_tag FILT3; /* offset: 0x007E size: 16 bit */
8790  /* Compare Register 1 */
8791  mcTIMER_COMP1_16B_tag COMP14; /* offset: 0x0080 size: 16 bit */
8792  /* Compare Register 2 */
8793  mcTIMER_COMP2_16B_tag COMP24; /* offset: 0x0082 size: 16 bit */
8794  /* Capture Register 1 */
8795  mcTIMER_CAPT1_16B_tag CAPT14; /* offset: 0x0084 size: 16 bit */
8796  /* Capture Register 2 */
8797  mcTIMER_CAPT2_16B_tag CAPT24; /* offset: 0x0086 size: 16 bit */
8798  /* Load Register */
8799  mcTIMER_LOAD_16B_tag LOAD4; /* offset: 0x0088 size: 16 bit */
8800  /* Hold Register */
8801  mcTIMER_HOLD_16B_tag HOLD4; /* offset: 0x008A size: 16 bit */
8802  /* Counter Register */
8803  mcTIMER_CNTR_16B_tag CNTR4; /* offset: 0x008C size: 16 bit */
8804  /* Control Register */
8805  mcTIMER_CTRL1_16B_tag CTRL14; /* offset: 0x008E size: 16 bit */
8806  /* Control Register 2 */
8807  mcTIMER_CTRL2_16B_tag CTRL24; /* offset: 0x0090 size: 16 bit */
8808  /* Control Register 3 */
8809  mcTIMER_CTRL3_16B_tag CTRL34; /* offset: 0x0092 size: 16 bit */
8810  /* Status Register */
8811  mcTIMER_STS_16B_tag STS4; /* offset: 0x0094 size: 16 bit */
8812  /* Interrupt and DMA Enable Register */
8813  mcTIMER_INTDMA_16B_tag INTDMA4; /* offset: 0x0096 size: 16 bit */
8814  /* Comparator Load Register 1 */
8815  mcTIMER_CMPLD1_16B_tag CMPLD14; /* offset: 0x0098 size: 16 bit */
8816  /* Comparator Load Register 2 */
8817  mcTIMER_CMPLD2_16B_tag CMPLD24; /* offset: 0x009A size: 16 bit */
8818  /* Compare and Capture Control Register */
8819  mcTIMER_CCCTRL_16B_tag CCCTRL4; /* offset: 0x009C size: 16 bit */
8820  /* Input Filter Register */
8821  mcTIMER_FILT_16B_tag FILT4; /* offset: 0x009E size: 16 bit */
8822  /* Compare Register 1 */
8823  mcTIMER_COMP1_16B_tag COMP15; /* offset: 0x00A0 size: 16 bit */
8824  /* Compare Register 2 */
8825  mcTIMER_COMP2_16B_tag COMP25; /* offset: 0x00A2 size: 16 bit */
8826  /* Capture Register 1 */
8827  mcTIMER_CAPT1_16B_tag CAPT15; /* offset: 0x00A4 size: 16 bit */
8828  /* Capture Register 2 */
8829  mcTIMER_CAPT2_16B_tag CAPT25; /* offset: 0x00A6 size: 16 bit */
8830  /* Load Register */
8831  mcTIMER_LOAD_16B_tag LOAD5; /* offset: 0x00A8 size: 16 bit */
8832  /* Hold Register */
8833  mcTIMER_HOLD_16B_tag HOLD5; /* offset: 0x00AA size: 16 bit */
8834  /* Counter Register */
8835  mcTIMER_CNTR_16B_tag CNTR5; /* offset: 0x00AC size: 16 bit */
8836  /* Control Register */
8837  mcTIMER_CTRL1_16B_tag CTRL15; /* offset: 0x00AE size: 16 bit */
8838  /* Control Register 2 */
8839  mcTIMER_CTRL2_16B_tag CTRL25; /* offset: 0x00B0 size: 16 bit */
8840  /* Control Register 3 */
8841  mcTIMER_CTRL3_16B_tag CTRL35; /* offset: 0x00B2 size: 16 bit */
8842  /* Status Register */
8843  mcTIMER_STS_16B_tag STS5; /* offset: 0x00B4 size: 16 bit */
8844  /* Interrupt and DMA Enable Register */
8845  mcTIMER_INTDMA_16B_tag INTDMA5; /* offset: 0x00B6 size: 16 bit */
8846  /* Comparator Load Register 1 */
8847  mcTIMER_CMPLD1_16B_tag CMPLD15; /* offset: 0x00B8 size: 16 bit */
8848  /* Comparator Load Register 2 */
8849  mcTIMER_CMPLD2_16B_tag CMPLD25; /* offset: 0x00BA size: 16 bit */
8850  /* Compare and Capture Control Register */
8851  mcTIMER_CCCTRL_16B_tag CCCTRL5; /* offset: 0x00BC size: 16 bit */
8852  /* Input Filter Register */
8853  mcTIMER_FILT_16B_tag FILT5; /* offset: 0x00BE size: 16 bit */
8854  };
8855 
8856  };
8857  int8_t mcTIMER_reserved_00C0[64];
8858  /* Watchdog Time-out Register */
8859  mcTIMER_WDTOL_16B_tag WDTOL; /* offset: 0x0100 size: 16 bit */
8860  /* Watchdog Time-out Register */
8861  mcTIMER_WDTOH_16B_tag WDTOH; /* offset: 0x0102 size: 16 bit */
8862  /* Fault Control Register */
8863  mcTIMER_FCTRL_16B_tag FCTRL; /* offset: 0x0104 size: 16 bit */
8864  /* Fault Status Register */
8865  mcTIMER_FSTS_16B_tag FSTS; /* offset: 0x0106 size: 16 bit */
8866  /* Fault Filter Registers */
8867  mcTIMER_FFILT_16B_tag FFILT; /* offset: 0x0108 size: 16 bit */
8868  int8_t mcTIMER_reserved_010A[2];
8869  /* Channel Enable Registers */
8870  mcTIMER_ENBL_16B_tag ENBL; /* offset: 0x010C size: 16 bit */
8871  int8_t mcTIMER_reserved_010E_C[2];
8872  union {
8873  mcTIMER_DREQ_16B_tag DREQ[4]; /* offset: 0x0110 (0x0002 x 4) */
8874 
8875  struct {
8876  /* DMA Request 0 Select Registers */
8877  mcTIMER_DREQ0_16B_tag DREQ0; /* offset: 0x0110 size: 16 bit */
8878  /* DMA Request 1 Select Registers */
8879  mcTIMER_DREQ1_16B_tag DREQ1; /* offset: 0x0112 size: 16 bit */
8880  /* DMA Request 2 Select Registers */
8881  mcTIMER_DREQ2_16B_tag DREQ2; /* offset: 0x0114 size: 16 bit */
8882  /* DMA Request 3 Select Registers */
8883  mcTIMER_DREQ3_16B_tag DREQ3; /* offset: 0x0116 size: 16 bit */
8884  };
8885 
8886  };
8887  } mcTIMER_tag;
8888 
8889 
8890 #define mcTIMER0 (*(volatile mcTIMER_tag *) 0xFFE18000UL)
8891 #define mcTIMER1 (*(volatile mcTIMER_tag *) 0xFFE1C000UL)
8892 #define mcTIMER2 (*(volatile mcTIMER_tag *) 0xFFE20000UL)
8893 
8894 
8895 
8896 /****************************************************************/
8897 /* */
8898 /* Module: mcPWM */
8899 /* */
8900 /****************************************************************/
8901 
8902 
8903  /* Register layout for all registers CNT... */
8904 
8905  typedef union { /* Counter Register */
8906  vuint16_t R;
8907  } mcPWM_CNT_16B_tag;
8908 
8909 
8910  /* Register layout for all registers INIT... */
8911 
8912  typedef union { /* Initial Counter Register */
8913  vuint16_t R;
8914  } mcPWM_INIT_16B_tag;
8915 
8916 
8917  /* Register layout for all registers CTRL2... */
8918 
8919  typedef union { /* Control 2 Register */
8920  vuint16_t R;
8921  struct {
8922  vuint16_t DBGEN:1; /* Debug Enable */
8923  vuint16_t WAITEN:1; /* Wait Enable */
8924  vuint16_t INDEP:1; /* Independent or Complementary Pair Operation */
8925 #ifndef USE_FIELD_ALIASES_mcPWM
8926  vuint16_t PWM23_INIT:1; /* PWM23 Initial Value */
8927 #else
8928  vuint16_t PWMA_INIT:1; /* deprecated name - please avoid */
8929 #endif
8930 #ifndef USE_FIELD_ALIASES_mcPWM
8931  vuint16_t PWM45_INIT:1; /* PWM23 Initial Value */
8932 #else
8933  vuint16_t PWMB_INIT:1; /* deprecated name - please avoid */
8934 #endif
8935  vuint16_t PWMX_INIT:1; /* PWMX Initial Value */
8936  vuint16_t INIT_SEL:2; /* Initialization Control Select */
8937  vuint16_t FRCEN:1; /* Force Initialization enable */
8938  vuint16_t FORCE:1; /* Force Initialization */
8939  vuint16_t FORCE_SEL:3; /* Force Source Select */
8940  vuint16_t RELOAD_SEL:1; /* Reload Source Select */
8941  vuint16_t CLK_SEL:2; /* Clock Source Select */
8942  } B;
8943  } mcPWM_CTRL2_16B_tag;
8944 
8945 
8946  /* Register layout for all registers CTRL1... */
8947 
8948  typedef union { /* Control Register */
8949  vuint16_t R;
8950  struct {
8951  vuint16_t LDFQ:4; /* Load Frequency */
8952  vuint16_t HALF:1; /* Half Cycle Reload */
8953  vuint16_t FULL:1; /* Full Cycle Reload */
8954  vuint16_t DT:2; /* Deadtime */
8955  vuint16_t:1;
8956  vuint16_t PRSC:3; /* Prescaler */
8957  vuint16_t:1;
8958  vuint16_t LDMOD:1; /* Load Mode Select */
8959  vuint16_t:1;
8960 #ifndef USE_FIELD_ALIASES_mcPWM
8961  vuint16_t DBL_EN:1; /* Double Switching Enable */
8962 #else
8963  vuint16_t DBLEN:1; /* deprecated name - please avoid */
8964 #endif
8965  } B;
8966  } mcPWM_CTRL1_16B_tag;
8967 
8968 
8969  /* Register layout for all registers VAL_0... */
8970 
8971  typedef union { /* Value Register 0 */
8972  vuint16_t R;
8973  } mcPWM_VAL_0_16B_tag;
8974 
8975 
8976  /* Register layout for all registers VAL_1... */
8977 
8978  typedef union { /* Value Register 1 */
8979  vuint16_t R;
8980  } mcPWM_VAL_1_16B_tag;
8981 
8982 
8983  /* Register layout for all registers VAL_2... */
8984 
8985  typedef union { /* Value Register 2 */
8986  vuint16_t R;
8987  } mcPWM_VAL_2_16B_tag;
8988 
8989 
8990  /* Register layout for all registers VAL_3... */
8991 
8992  typedef union { /* Value Register 3 */
8993  vuint16_t R;
8994  } mcPWM_VAL_3_16B_tag;
8995 
8996 
8997  /* Register layout for all registers VAL_4... */
8998 
8999  typedef union { /* Value Register 4 */
9000  vuint16_t R;
9001  } mcPWM_VAL_4_16B_tag;
9002 
9003 
9004  /* Register layout for all registers VAL_5... */
9005 
9006  typedef union { /* Value Register 5 */
9007  vuint16_t R;
9008  } mcPWM_VAL_5_16B_tag;
9009 
9010 
9011  /* Register layout for all registers FRACA... */
9012 
9013  typedef union { /* Fractional Delay Register A */
9014  vuint16_t R;
9015  struct {
9016  vuint16_t FRACA_EN:1; /* Fractional Delay Enable */
9017  vuint16_t:10;
9018  vuint16_t FRACA_DLY:5; /* Fractional Delay Value */
9019  } B;
9020  } mcPWM_FRACA_16B_tag;
9021 
9022 
9023  /* Register layout for all registers FRACB... */
9024 
9025  typedef union { /* Fractional Delay Register B */
9026  vuint16_t R;
9027  struct {
9028  vuint16_t FRACA_EN:1; /* Fractional Delay Enable */
9029  vuint16_t:10;
9030  vuint16_t FRACA_DLY:5; /* Fractional Delay Value */
9031  } B;
9032  } mcPWM_FRACB_16B_tag;
9033 
9034 
9035  /* Register layout for all registers OCTRL... */
9036 
9037  typedef union { /* Output Control Register */
9038  vuint16_t R;
9039  struct {
9040  vuint16_t PWMA_IN:1; /* PWMA Input */
9041  vuint16_t PWMB_IN:1; /* PWMB Input */
9042  vuint16_t PWMX_IN:1; /* PWMX Input */
9043  vuint16_t:2;
9044  vuint16_t POLA:1; /* PWMA Output Polarity */
9045  vuint16_t POLB:1; /* PWMB Output Polarity */
9046  vuint16_t POLX:1; /* PWMX Output Polarity */
9047  vuint16_t:2;
9048  vuint16_t PWMAFS:2; /* PWMA Fault State */
9049  vuint16_t PWMBFS:2; /* PWMB Fault State */
9050  vuint16_t PWMXFS:2; /* PWMX Fault State */
9051  } B;
9052  } mcPWM_OCTRL_16B_tag;
9053 
9054 
9055  /* Register layout for all registers STS... */
9056 
9057  typedef union { /* Status Register */
9058  vuint16_t R;
9059  struct {
9060  vuint16_t:1;
9061  vuint16_t RUF:1; /* Registers Updated Flag */
9062  vuint16_t REF:1; /* Reload Error Flag */
9063  vuint16_t RF:1; /* Reload Flag */
9064  vuint16_t CFA1:1; /* Capture Flag A1 */
9065  vuint16_t CFA0:1; /* Capture Flag A0 */
9066  vuint16_t CFB1:1; /* Capture Flag B1 */
9067  vuint16_t CFB0:1; /* Capture Flag B0 */
9068  vuint16_t CFX1:1; /* Capture Flag X1 */
9069  vuint16_t CFX0:1; /* Capture Flag X0 */
9070  vuint16_t CMPF:6; /* Compare Flags */
9071  } B;
9072  } mcPWM_STS_16B_tag;
9073 
9074 
9075  /* Register layout for all registers INTEN... */
9076 
9077  typedef union { /* Interrupt Enable Registers */
9078  vuint16_t R;
9079  struct {
9080  vuint16_t:2;
9081  vuint16_t REIE:1; /* Reload Error Interrupt Enable */
9082  vuint16_t RIE:1; /* Reload Interrupt Enable */
9083  vuint16_t CA1IE:1; /* Capture A1 Interrupt Enable */
9084  vuint16_t CA0IE:1; /* Capture A0 Interrupt Enable */
9085  vuint16_t CB1IE:1; /* Capture B1 Interrupt Enable */
9086  vuint16_t CB0IE:1; /* Capture B0 Interrupt Enable */
9087  vuint16_t CX1IE:1; /* Capture X1 Interrupt Enable */
9088  vuint16_t CX0IE:1; /* Capture X0 Interrupt Enable */
9089  vuint16_t CMPIE:6; /* Compare Interrupt Enables */
9090  } B;
9091  } mcPWM_INTEN_16B_tag;
9092 
9093 
9094  /* Register layout for all registers DMAEN... */
9095 
9096  typedef union { /* DMA Enable Registers */
9097  vuint16_t R;
9098  struct {
9099  vuint16_t:6;
9100  vuint16_t VALDE:1; /* Value Register DMA Enable */
9101  vuint16_t FAND:1; /* FIFO Watermark AND Control */
9102  vuint16_t CAPTDE:2; /* Capture DMA Enable Source Select */
9103  vuint16_t CA1DE:1; /* Capture A1 FIFO DMA Enable */
9104  vuint16_t CA0DE:1; /* Capture A0 FIFO DMA Enable */
9105  vuint16_t CB1DE:1; /* Capture B1 FIFO DMA Enable */
9106  vuint16_t CB0DE:1; /* Capture B0 FIFO DMA Enable */
9107  vuint16_t CX1DE:1; /* Capture X1 FIFO DMA Enable */
9108  vuint16_t CX0DE:1; /* Capture X0 FIFO DMA Enable */
9109  } B;
9110  } mcPWM_DMAEN_16B_tag;
9111 
9112 
9113  /* Register layout for all registers TCTRL... */
9114 
9115  typedef union { /* Output Trigger Control Registers */
9116  vuint16_t R;
9117  struct {
9118  vuint16_t:10;
9119  vuint16_t OUT_TRIG_EN:6; /* Output Trigger Enables */
9120  } B;
9121  } mcPWM_TCTRL_16B_tag;
9122 
9123 
9124  /* Register layout for all registers DISMAP... */
9125 
9126  typedef union { /* Fault Disable Mapping Registers */
9127  vuint16_t R;
9128  struct {
9129  vuint16_t:4;
9130  vuint16_t DISX:4; /* PWMX Fault Disable Mask */
9131  vuint16_t DISB:4; /* PWMB Fault Disable Mask */
9132  vuint16_t DISA:4; /* PWMA Fault Disable Mask */
9133  } B;
9134  } mcPWM_DISMAP_16B_tag;
9135 
9136 
9137  /* Register layout for all registers DTCNT0... */
9138 
9139  typedef union { /* Deadtime Count Register 0 */
9140  vuint16_t R;
9141  struct {
9142  vuint16_t:5;
9143  vuint16_t DTCNT0:11; /* Deadtime Count Register 0 */
9144  } B;
9145  } mcPWM_DTCNT0_16B_tag;
9146 
9147 
9148  /* Register layout for all registers DTCNT1... */
9149 
9150  typedef union { /* Deadtime Count Register 1 */
9151  vuint16_t R;
9152  struct {
9153  vuint16_t:5;
9154  vuint16_t DTCNT1:11; /* Deadtime Count Register 1 */
9155  } B;
9156  } mcPWM_DTCNT1_16B_tag;
9157 
9158 
9159  /* Register layout for all registers CAPTCTRLA... */
9160 
9161  typedef union { /* Capture Control A Register */
9162  vuint16_t R;
9163  struct {
9164  vuint16_t CA1CNT:3; /* Capture A1 FIFO Word Count */
9165  vuint16_t CA0CNT:3; /* Capture A0 FIFO Word Count */
9166  vuint16_t CFAWM:2; /* Capture A FIFOs Water Mark */
9167  vuint16_t EDGCNTAEN:1; /* Edge Counter A Enable */
9168  vuint16_t INPSELA:1; /* Input Select A */
9169  vuint16_t EDGA1:2; /* Edge A 1 */
9170  vuint16_t EDGA0:2; /* Edge A 0 */
9171  vuint16_t ONESHOTA:1; /* One Shot Mode A */
9172  vuint16_t ARMA:1; /* Arm A */
9173  } B;
9174  } mcPWM_CAPTCTRLA_16B_tag;
9175 
9176 
9177  /* Register layout for all registers CAPTCMPA... */
9178 
9179  typedef union { /* Capture Compare A Register */
9180  vuint16_t R;
9181  struct {
9182  vuint16_t EDGCNTA:8; /* Edge Counter A */
9183  vuint16_t EDGCMPA:8; /* Edge Compare A */
9184  } B;
9185  } mcPWM_CAPTCMPA_16B_tag;
9186 
9187 
9188  /* Register layout for all registers CAPTCTRLB... */
9189 
9190  typedef union { /* Capture Control B Register */
9191  vuint16_t R;
9192  struct {
9193  vuint16_t CB1CNT:3; /* Capture B1 FIFO Word Count */
9194  vuint16_t CB0CNT:3; /* Capture B0 FIFO Word Count */
9195  vuint16_t CFBWM:2; /* Capture B FIFOs Water Mark */
9196  vuint16_t EDGCNTBEN:1; /* Edge Counter B Enable */
9197  vuint16_t INPSELB:1; /* Input Select B */
9198  vuint16_t EDGB1:2; /* Edge B 1 */
9199  vuint16_t EDGB0:2; /* Edge B 0 */
9200  vuint16_t ONESHOTB:1; /* One Shot Mode B */
9201  vuint16_t ARMB:1; /* Arm B */
9202  } B;
9203  } mcPWM_CAPTCTRLB_16B_tag;
9204 
9205 
9206  /* Register layout for all registers CAPTCMPB... */
9207 
9208  typedef union { /* Capture Compare B Register */
9209  vuint16_t R;
9210  struct {
9211  vuint16_t EDGCNTB:8; /* Edge Counter B */
9212  vuint16_t EDGCMPB:8; /* Edge Compare B */
9213  } B;
9214  } mcPWM_CAPTCMPB_16B_tag;
9215 
9216 
9217  /* Register layout for all registers CAPTCTRLX... */
9218 
9219  typedef union { /* Capture Control X Register */
9220  vuint16_t R;
9221  struct {
9222  vuint16_t CX1CNT:3; /* Capture X1 FIFO Word Count */
9223  vuint16_t CX0CNT:3; /* Capture X0 FIFO Word Count */
9224  vuint16_t CFXWM:2; /* Capture X FIFOs Water Mark */
9225 #ifndef USE_FIELD_ALIASES_mcPWM
9226  vuint16_t EDGCNTXEN:1; /* Edge Counter X Enable */
9227 #else
9228  vuint16_t EDGCNTX_EN:1; /* deprecated name - please avoid */
9229 #endif
9230 #ifndef USE_FIELD_ALIASES_mcPWM
9231  vuint16_t INPSELX:1; /* Input Select X */
9232 #else
9233  vuint16_t INP_SELX:1; /* deprecated name - please avoid */
9234 #endif
9235  vuint16_t EDGX1:2; /* Edge X 1 */
9236  vuint16_t EDGX0:2; /* Edge X 0 */
9237  vuint16_t ONESHOTX:1; /* One Shot Mode X */
9238  vuint16_t ARMX:1; /* Arm X */
9239  } B;
9240  } mcPWM_CAPTCTRLX_16B_tag;
9241 
9242 
9243  /* Register layout for all registers CAPTCMPX... */
9244 
9245  typedef union { /* Capture Compare X Register */
9246  vuint16_t R;
9247  struct {
9248  vuint16_t EDGCNTX:8; /* Edge Counter X */
9249  vuint16_t EDGCMPX:8; /* Edge Compare X */
9250  } B;
9251  } mcPWM_CAPTCMPX_16B_tag;
9252 
9253 
9254  /* Register layout for all registers CVAL0... */
9255 
9256  typedef union { /* Capture Value 0 Register */
9257  vuint16_t R;
9258  struct {
9259  vuint16_t CAPTVAL0:16; /* Captured value from submodule counter */
9260  } B;
9261  } mcPWM_CVAL0_16B_tag;
9262 
9263 
9264  /* Register layout for all registers CVAL0CYC... */
9265 
9266  typedef union { /* Capture Value 0 Cycle Register */
9267  vuint16_t R;
9268  struct {
9269  vuint16_t:12;
9270  vuint16_t CVAL0CYC:4; /* Capture Value 0 Cycle */
9271  } B;
9272  } mcPWM_CVAL0CYC_16B_tag;
9273 
9274 
9275  /* Register layout for all registers CVAL1... */
9276 
9277  typedef union { /* Capture Value 1 Register */
9278  vuint16_t R;
9279  struct {
9280  vuint16_t CAPTVAL1:16; /* Captured value from submodule counter */
9281  } B;
9282  } mcPWM_CVAL1_16B_tag;
9283 
9284 
9285  /* Register layout for all registers CVAL1CYC... */
9286 
9287  typedef union { /* Capture Value 1 Cycle Register */
9288  vuint16_t R;
9289  struct {
9290  vuint16_t:12;
9291  vuint16_t CVAL1CYC:4; /* Capture Value 1 Cycle */
9292  } B;
9293  } mcPWM_CVAL1CYC_16B_tag;
9294 
9295 
9296  /* Register layout for all registers CVAL2... */
9297 
9298  typedef union { /* Capture Value 2 Register */
9299  vuint16_t R;
9300  struct {
9301  vuint16_t CAPTVAL2:16; /* Captured value from submodule counter */
9302  } B;
9303  } mcPWM_CVAL2_16B_tag;
9304 
9305 
9306  /* Register layout for all registers CVAL2CYC... */
9307 
9308  typedef union { /* Capture Value 2 Cycle Register */
9309  vuint16_t R;
9310  struct {
9311  vuint16_t:12;
9312  vuint16_t CVAL2CYC:4; /* Capture Value 2 Cycle */
9313  } B;
9314  } mcPWM_CVAL2CYC_16B_tag;
9315 
9316 
9317  /* Register layout for all registers CVAL3... */
9318 
9319  typedef union { /* Capture Value 3 Register */
9320  vuint16_t R;
9321  struct {
9322  vuint16_t CAPTVAL3:16; /* Captured value from submodule counter */
9323  } B;
9324  } mcPWM_CVAL3_16B_tag;
9325 
9326 
9327  /* Register layout for all registers CVAL3CYC... */
9328 
9329  typedef union { /* Capture Value 3 Cycle Register */
9330  vuint16_t R;
9331  struct {
9332  vuint16_t:12;
9333  vuint16_t CVAL3CYC:4; /* Capture Value 3 Cycle */
9334  } B;
9335  } mcPWM_CVAL3CYC_16B_tag;
9336 
9337 
9338  /* Register layout for all registers CVAL4... */
9339 
9340  typedef union { /* Capture Value 4 Register */
9341  vuint16_t R;
9342  struct {
9343  vuint16_t CAPTVAL4:16; /* Captured value from submodule counter */
9344  } B;
9345  } mcPWM_CVAL4_16B_tag;
9346 
9347 
9348  /* Register layout for all registers CVAL4CYC... */
9349 
9350  typedef union { /* Capture Value 4 Cycle Register */
9351  vuint16_t R;
9352  struct {
9353  vuint16_t:12;
9354  vuint16_t CVAL4CYC:4; /* Capture Value 4 Cycle */
9355  } B;
9356  } mcPWM_CVAL4CYC_16B_tag;
9357 
9358 
9359  /* Register layout for all registers CVAL5... */
9360 
9361  typedef union { /* Capture Value 5 Register */
9362  vuint16_t R;
9363  struct {
9364  vuint16_t CAPTVAL5:16; /* Captured value from submodule counter */
9365  } B;
9366  } mcPWM_CVAL5_16B_tag;
9367 
9368 
9369  /* Register layout for all registers CVAL5CYC... */
9370 
9371  typedef union { /* Capture Value 5 Cycle Register */
9372  vuint16_t R;
9373  struct {
9374  vuint16_t:12;
9375  vuint16_t CVAL5CYC:4; /* Capture Value 5 Cycle */
9376  } B;
9377  } mcPWM_CVAL5CYC_16B_tag;
9378 
9379  typedef union { /* Output Enable Register */
9380  vuint16_t R;
9381  struct {
9382  vuint16_t:4;
9383  vuint16_t PWMA_EN:4; /* PWMA Output Enables */
9384  vuint16_t PWMB_EN:4; /* PWMB Output Enables */
9385  vuint16_t PWMX_EN:4; /* PWMX Output Enables */
9386  } B;
9387  } mcPWM_OUTEN_16B_tag;
9388 
9389  typedef union { /* Mask Register */
9390  vuint16_t R;
9391  struct {
9392  vuint16_t:4;
9393  vuint16_t MASKA:4; /* PWMA Masks */
9394  vuint16_t MASKB:4; /* PWMB Masks */
9395  vuint16_t MASKX:4; /* PWMX Masks */
9396  } B;
9397  } mcPWM_MASK_16B_tag;
9398 
9399  typedef union { /* Software Controlled Output Register */
9400  vuint16_t R;
9401  struct {
9402  vuint16_t:8;
9403 #ifndef USE_FIELD_ALIASES_mcPWM
9404  vuint16_t OUT23_3:1; /* Software Controlled Output 23_3 */
9405 #else
9406  vuint16_t OUTA_3:1; /* deprecated name - please avoid */
9407 #endif
9408 #ifndef USE_FIELD_ALIASES_mcPWM
9409  vuint16_t OUT45_3:1; /* Software Controlled Output 45_3 */
9410 #else
9411  vuint16_t OUTB_3:1; /* deprecated name - please avoid */
9412 #endif
9413 #ifndef USE_FIELD_ALIASES_mcPWM
9414  vuint16_t OUT23_2:1; /* Software Controlled Output 23_2 */
9415 #else
9416  vuint16_t OUTA_2:1; /* deprecated name - please avoid */
9417 #endif
9418 #ifndef USE_FIELD_ALIASES_mcPWM
9419  vuint16_t OUT45_2:1; /* Software Controlled Output 45_2 */
9420 #else
9421  vuint16_t OUTB_2:1; /* deprecated name - please avoid */
9422 #endif
9423 #ifndef USE_FIELD_ALIASES_mcPWM
9424  vuint16_t OUT23_1:1; /* Software Controlled Output 23_1 */
9425 #else
9426  vuint16_t OUTA_1:1; /* deprecated name - please avoid */
9427 #endif
9428 #ifndef USE_FIELD_ALIASES_mcPWM
9429  vuint16_t OUT45_1:1; /* Software Controlled Output 45_1 */
9430 #else
9431  vuint16_t OUTB_1:1; /* deprecated name - please avoid */
9432 #endif
9433 #ifndef USE_FIELD_ALIASES_mcPWM
9434  vuint16_t OUT23_0:1; /* Software Controlled Output 23_0 */
9435 #else
9436  vuint16_t OUTA_0:1; /* deprecated name - please avoid */
9437 #endif
9438 #ifndef USE_FIELD_ALIASES_mcPWM
9439  vuint16_t OUT45_0:1; /* Software Controlled Output 45_0 */
9440 #else
9441  vuint16_t OUTB_0:1; /* deprecated name - please avoid */
9442 #endif
9443  } B;
9444  } mcPWM_SWCOUT_16B_tag;
9445 
9446  typedef union { /* Deadtime Source Select Register */
9447  vuint16_t R;
9448  struct {
9449 #ifndef USE_FIELD_ALIASES_mcPWM
9450  vuint16_t SEL23_3:2; /* PWM23_3 Control Select */
9451 #else
9452  vuint16_t SELA_3:2; /* deprecated name - please avoid */
9453 #endif
9454 #ifndef USE_FIELD_ALIASES_mcPWM
9455  vuint16_t SEL45_3:2; /* PWM45_3 Control Select */
9456 #else
9457  vuint16_t SELB_3:2; /* deprecated name - please avoid */
9458 #endif
9459 #ifndef USE_FIELD_ALIASES_mcPWM
9460  vuint16_t SEL23_2:2; /* PWM23_2 Control Select */
9461 #else
9462  vuint16_t SELA_2:2; /* deprecated name - please avoid */
9463 #endif
9464 #ifndef USE_FIELD_ALIASES_mcPWM
9465  vuint16_t SEL45_2:2; /* PWM45_2 Control Select */
9466 #else
9467  vuint16_t SELB_2:2; /* deprecated name - please avoid */
9468 #endif
9469 #ifndef USE_FIELD_ALIASES_mcPWM
9470  vuint16_t SEL23_1:2; /* PWM23_1 Control Select */
9471 #else
9472  vuint16_t SELA_1:2; /* deprecated name - please avoid */
9473 #endif
9474 #ifndef USE_FIELD_ALIASES_mcPWM
9475  vuint16_t SEL45_1:2; /* PWM45_1 Control Select */
9476 #else
9477  vuint16_t SELB_1:2; /* deprecated name - please avoid */
9478 #endif
9479 #ifndef USE_FIELD_ALIASES_mcPWM
9480  vuint16_t SEL23_0:2; /* PWM23_0 Control Select */
9481 #else
9482  vuint16_t SELA_0:2; /* deprecated name - please avoid */
9483 #endif
9484 #ifndef USE_FIELD_ALIASES_mcPWM
9485  vuint16_t SEL45_0:2; /* PWM45_0 Control Select */
9486 #else
9487  vuint16_t SELB_0:2; /* deprecated name - please avoid */
9488 #endif
9489  } B;
9490  } mcPWM_DTSRCSEL_16B_tag;
9491 
9492  typedef union { /* Master Control Register */
9493  vuint16_t R;
9494  struct {
9495  vuint16_t IPOL:4; /* Current Polarity */
9496  vuint16_t RUN:4; /* Run */
9497 #ifndef USE_FIELD_ALIASES_mcPWM
9498  vuint16_t CLOK:4; /* Clear Load Okay */
9499 #else
9500  vuint16_t CLDOK:4; /* deprecated name - please avoid */
9501 #endif
9502  vuint16_t LDOK:4; /* Load Okay */
9503  } B;
9504  } mcPWM_MCTRL_16B_tag;
9505 
9506  typedef union { /* Fault Control Register */
9507  vuint16_t R;
9508  struct {
9509  vuint16_t FLVL:4; /* Fault Level */
9510  vuint16_t FAUTO:4; /* Automatic Fault Clearing */
9511  vuint16_t FSAFE:4; /* Fault Safety Mode */
9512  vuint16_t FIE:4; /* Fault Interrupt Enables */
9513  } B;
9514  } mcPWM_FCTRL_16B_tag;
9515 
9516  typedef union { /* Fault Status Register */
9517  vuint16_t R;
9518  struct {
9519  vuint16_t:3;
9520  vuint16_t FTEST:1; /* Fault Test */
9521  vuint16_t FFPIN:4; /* Filtered Fault Pins */
9522  vuint16_t:4;
9523  vuint16_t FFLAG:4; /* Fault Flags */
9524  } B;
9525  } mcPWM_FSTS_16B_tag;
9526 
9527  typedef union { /* Fault Filter Register */
9528  vuint16_t R;
9529  struct {
9530  vuint16_t:5;
9531  vuint16_t FILT_CNT:3; /* Fault Filter Count */
9532  vuint16_t FILT_PER:8; /* Fault Filter Period */
9533  } B;
9534  } mcPWM_FFILT_16B_tag;
9535 
9536 
9537  /* Register layout for generated register(s) VAL... */
9538 
9539  typedef union { /* */
9540  vuint16_t R;
9541  } mcPWM_VAL_16B_tag;
9542 
9543 
9544  typedef struct mcPWM_SUBMOD_struct_tag {
9545 
9546  /* Counter Register */
9547  mcPWM_CNT_16B_tag CNT; /* relative offset: 0x0000 */
9548  /* Initial Counter Register */
9549  mcPWM_INIT_16B_tag INIT; /* relative offset: 0x0002 */
9550  /* Control 2 Register */
9551  mcPWM_CTRL2_16B_tag CTRL2; /* relative offset: 0x0004 */
9552  union {
9553  /* Control Register */
9554  mcPWM_CTRL1_16B_tag CTRL1; /* relative offset: 0x0006 */
9555  mcPWM_CTRL1_16B_tag CTRL; /* deprecated - please avoid */
9556  };
9557  /* Value Register 0 */
9558 
9559  union {
9560 
9561  struct {
9562 
9563  mcPWM_VAL_0_16B_tag VAL_0; /* relative offset: 0x0008 */
9564  /* Value Register 1 */
9565  mcPWM_VAL_1_16B_tag VAL_1; /* relative offset: 0x000A */
9566  /* Value Register 2 */
9567  mcPWM_VAL_2_16B_tag VAL_2; /* relative offset: 0x000C */
9568  /* Value Register 3 */
9569  mcPWM_VAL_3_16B_tag VAL_3; /* relative offset: 0x000E */
9570  /* Value Register 4 */
9571  mcPWM_VAL_4_16B_tag VAL_4; /* relative offset: 0x0010 */
9572  /* Value Register 5 */
9573  mcPWM_VAL_5_16B_tag VAL_5; /* relative offset: 0x0012 */
9574 
9575  };
9576 
9577  mcPWM_VAL_0_16B_tag VAL[6]; /* offset: 0x0008 size: 16 bit */
9578 
9579  };
9580  /* Fractional Delay Register A */
9581  mcPWM_FRACA_16B_tag FRACA; /* relative offset: 0x0014 */
9582  /* Fractional Delay Register B */
9583  mcPWM_FRACB_16B_tag FRACB; /* relative offset: 0x0016 */
9584  /* Output Control Register */
9585  mcPWM_OCTRL_16B_tag OCTRL; /* relative offset: 0x0018 */
9586  /* Status Register */
9587  mcPWM_STS_16B_tag STS; /* relative offset: 0x001A */
9588  /* Interrupt Enable Registers */
9589  mcPWM_INTEN_16B_tag INTEN; /* relative offset: 0x001C */
9590  /* DMA Enable Registers */
9591  mcPWM_DMAEN_16B_tag DMAEN; /* relative offset: 0x001E */
9592  /* Output Trigger Control Registers */
9593  mcPWM_TCTRL_16B_tag TCTRL; /* relative offset: 0x0020 */
9594  /* Fault Disable Mapping Registers */
9595  mcPWM_DISMAP_16B_tag DISMAP; /* relative offset: 0x0022 */
9596  /* Deadtime Count Register 0 */
9597  mcPWM_DTCNT0_16B_tag DTCNT0; /* relative offset: 0x0024 */
9598  /* Deadtime Count Register 1 */
9599  mcPWM_DTCNT1_16B_tag DTCNT1; /* relative offset: 0x0026 */
9600  /* Capture Control A Register */
9601  mcPWM_CAPTCTRLA_16B_tag CAPTCTRLA; /* relative offset: 0x0028 */
9602  union {
9603  /* Capture Compare A Register */
9604  mcPWM_CAPTCMPA_16B_tag CAPTCMPA; /* relative offset: 0x002A */
9605  mcPWM_CAPTCMPA_16B_tag CAPTCOMPA; /* deprecated - please avoid */
9606  };
9607  /* Capture Control B Register */
9608  mcPWM_CAPTCTRLB_16B_tag CAPTCTRLB; /* relative offset: 0x002C */
9609  union {
9610  /* Capture Compare B Register */
9611  mcPWM_CAPTCMPB_16B_tag CAPTCMPB; /* relative offset: 0x002E */
9612  mcPWM_CAPTCMPB_16B_tag CAPTCOMPB; /* deprecated - please avoid */
9613  };
9614  /* Capture Control X Register */
9615  mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX; /* relative offset: 0x0030 */
9616  union {
9617  /* Capture Compare X Register */
9618  mcPWM_CAPTCMPX_16B_tag CAPTCMPX; /* relative offset: 0x0032 */
9619  mcPWM_CAPTCMPX_16B_tag CAPTCOMPX; /* deprecated - please avoid */
9620  };
9621  /* Capture Value 0 Register */
9622  mcPWM_CVAL0_16B_tag CVAL0; /* relative offset: 0x0034 */
9623  union {
9624  /* Capture Value 0 Cycle Register */
9625  mcPWM_CVAL0CYC_16B_tag CVAL0CYC; /* relative offset: 0x0036 */
9626  mcPWM_CVAL0CYC_16B_tag CVAL0C; /* deprecated - please avoid */
9627  };
9628  /* Capture Value 1 Register */
9629  mcPWM_CVAL1_16B_tag CVAL1; /* relative offset: 0x0038 */
9630  union {
9631  /* Capture Value 1 Cycle Register */
9632  mcPWM_CVAL1CYC_16B_tag CVAL1CYC; /* relative offset: 0x003A */
9633  mcPWM_CVAL1CYC_16B_tag CVAL1C; /* deprecated - please avoid */
9634  };
9635  /* Capture Value 2 Register */
9636  mcPWM_CVAL2_16B_tag CVAL2; /* relative offset: 0x003C */
9637  union {
9638  /* Capture Value 2 Cycle Register */
9639  mcPWM_CVAL2CYC_16B_tag CVAL2CYC; /* relative offset: 0x003E */
9640  mcPWM_CVAL2CYC_16B_tag CVAL2C; /* deprecated - please avoid */
9641  };
9642  /* Capture Value 3 Register */
9643  mcPWM_CVAL3_16B_tag CVAL3; /* relative offset: 0x0040 */
9644  union {
9645  /* Capture Value 3 Cycle Register */
9646  mcPWM_CVAL3CYC_16B_tag CVAL3CYC; /* relative offset: 0x0042 */
9647  mcPWM_CVAL3CYC_16B_tag CVAL3C; /* deprecated - please avoid */
9648  };
9649  /* Capture Value 4 Register */
9650  mcPWM_CVAL4_16B_tag CVAL4; /* relative offset: 0x0044 */
9651  union {
9652  /* Capture Value 4 Cycle Register */
9653  mcPWM_CVAL4CYC_16B_tag CVAL4CYC; /* relative offset: 0x0046 */
9654  mcPWM_CVAL4CYC_16B_tag CVAL4C; /* deprecated - please avoid */
9655  };
9656  /* Capture Value 5 Register */
9657  mcPWM_CVAL5_16B_tag CVAL5; /* relative offset: 0x0048 */
9658  union {
9659  /* Capture Value 5 Cycle Register */
9660  mcPWM_CVAL5CYC_16B_tag CVAL5CYC; /* relative offset: 0x004A */
9661  mcPWM_CVAL5CYC_16B_tag CVAL5C; /* deprecated - please avoid */
9662  };
9663  int8_t mcPWM_SUBMOD_reserved_004C[4];
9664 
9665  } mcPWM_SUBMOD_tag;
9666 
9667 
9668  typedef struct mcPWM_struct_tag { /* start of mcPWM_tag */
9669  union {
9670  /* Register set SUBMOD */
9671  mcPWM_SUBMOD_tag SUBMOD[4]; /* offset: 0x0000 (0x0050 x 4) */
9672 
9673  struct {
9674  /* Counter Register */
9675  mcPWM_CNT_16B_tag CNT0; /* offset: 0x0000 size: 16 bit */
9676  /* Initial Counter Register */
9677  mcPWM_INIT_16B_tag INIT0; /* offset: 0x0002 size: 16 bit */
9678  /* Control 2 Register */
9679  mcPWM_CTRL2_16B_tag CTRL20; /* offset: 0x0004 size: 16 bit */
9680  /* Control Register */
9681  mcPWM_CTRL1_16B_tag CTRL10; /* offset: 0x0006 size: 16 bit */
9682  /* Value Register 0 */
9683  mcPWM_VAL_0_16B_tag VAL_00; /* offset: 0x0008 size: 16 bit */
9684  /* Value Register 1 */
9685  mcPWM_VAL_1_16B_tag VAL_10; /* offset: 0x000A size: 16 bit */
9686  /* Value Register 2 */
9687  mcPWM_VAL_2_16B_tag VAL_20; /* offset: 0x000C size: 16 bit */
9688  /* Value Register 3 */
9689  mcPWM_VAL_3_16B_tag VAL_30; /* offset: 0x000E size: 16 bit */
9690  /* Value Register 4 */
9691  mcPWM_VAL_4_16B_tag VAL_40; /* offset: 0x0010 size: 16 bit */
9692  /* Value Register 5 */
9693  mcPWM_VAL_5_16B_tag VAL_50; /* offset: 0x0012 size: 16 bit */
9694  /* Fractional Delay Register A */
9695  mcPWM_FRACA_16B_tag FRACA0; /* offset: 0x0014 size: 16 bit */
9696  /* Fractional Delay Register B */
9697  mcPWM_FRACB_16B_tag FRACB0; /* offset: 0x0016 size: 16 bit */
9698  /* Output Control Register */
9699  mcPWM_OCTRL_16B_tag OCTRL0; /* offset: 0x0018 size: 16 bit */
9700  /* Status Register */
9701  mcPWM_STS_16B_tag STS0; /* offset: 0x001A size: 16 bit */
9702  /* Interrupt Enable Registers */
9703  mcPWM_INTEN_16B_tag INTEN0; /* offset: 0x001C size: 16 bit */
9704  /* DMA Enable Registers */
9705  mcPWM_DMAEN_16B_tag DMAEN0; /* offset: 0x001E size: 16 bit */
9706  /* Output Trigger Control Registers */
9707  mcPWM_TCTRL_16B_tag TCTRL0; /* offset: 0x0020 size: 16 bit */
9708  /* Fault Disable Mapping Registers */
9709  mcPWM_DISMAP_16B_tag DISMAP0; /* offset: 0x0022 size: 16 bit */
9710  /* Deadtime Count Register 0 */
9711  mcPWM_DTCNT0_16B_tag DTCNT00; /* offset: 0x0024 size: 16 bit */
9712  /* Deadtime Count Register 1 */
9713  mcPWM_DTCNT1_16B_tag DTCNT10; /* offset: 0x0026 size: 16 bit */
9714  /* Capture Control A Register */
9715  mcPWM_CAPTCTRLA_16B_tag CAPTCTRLA0; /* offset: 0x0028 size: 16 bit */
9716  /* Capture Compare A Register */
9717  mcPWM_CAPTCMPA_16B_tag CAPTCMPA0; /* offset: 0x002A size: 16 bit */
9718  /* Capture Control B Register */
9719  mcPWM_CAPTCTRLB_16B_tag CAPTCTRLB0; /* offset: 0x002C size: 16 bit */
9720  /* Capture Compare B Register */
9721  mcPWM_CAPTCMPB_16B_tag CAPTCMPB0; /* offset: 0x002E size: 16 bit */
9722  /* Capture Control X Register */
9723  mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX0; /* offset: 0x0030 size: 16 bit */
9724  /* Capture Compare X Register */
9725  mcPWM_CAPTCMPX_16B_tag CAPTCMPX0; /* offset: 0x0032 size: 16 bit */
9726  /* Capture Value 0 Register */
9727  mcPWM_CVAL0_16B_tag CVAL00; /* offset: 0x0034 size: 16 bit */
9728  /* Capture Value 0 Cycle Register */
9729  mcPWM_CVAL0CYC_16B_tag CVAL0CYC0; /* offset: 0x0036 size: 16 bit */
9730  /* Capture Value 1 Register */
9731  mcPWM_CVAL1_16B_tag CVAL10; /* offset: 0x0038 size: 16 bit */
9732  /* Capture Value 1 Cycle Register */
9733  mcPWM_CVAL1CYC_16B_tag CVAL1CYC0; /* offset: 0x003A size: 16 bit */
9734  /* Capture Value 2 Register */
9735  mcPWM_CVAL2_16B_tag CVAL20; /* offset: 0x003C size: 16 bit */
9736  /* Capture Value 2 Cycle Register */
9737  mcPWM_CVAL2CYC_16B_tag CVAL2CYC0; /* offset: 0x003E size: 16 bit */
9738  /* Capture Value 3 Register */
9739  mcPWM_CVAL3_16B_tag CVAL30; /* offset: 0x0040 size: 16 bit */
9740  /* Capture Value 3 Cycle Register */
9741  mcPWM_CVAL3CYC_16B_tag CVAL3CYC0; /* offset: 0x0042 size: 16 bit */
9742  /* Capture Value 4 Register */
9743  mcPWM_CVAL4_16B_tag CVAL40; /* offset: 0x0044 size: 16 bit */
9744  /* Capture Value 4 Cycle Register */
9745  mcPWM_CVAL4CYC_16B_tag CVAL4CYC0; /* offset: 0x0046 size: 16 bit */
9746  /* Capture Value 5 Register */
9747  mcPWM_CVAL5_16B_tag CVAL50; /* offset: 0x0048 size: 16 bit */
9748  /* Capture Value 5 Cycle Register */
9749  mcPWM_CVAL5CYC_16B_tag CVAL5CYC0; /* offset: 0x004A size: 16 bit */
9750  int8_t mcPWM_reserved_004C_I2[4];
9751  /* Counter Register */
9752  mcPWM_CNT_16B_tag CNT1; /* offset: 0x0050 size: 16 bit */
9753  /* Initial Counter Register */
9754  mcPWM_INIT_16B_tag INIT1; /* offset: 0x0052 size: 16 bit */
9755  /* Control 2 Register */
9756  mcPWM_CTRL2_16B_tag CTRL21; /* offset: 0x0054 size: 16 bit */
9757  /* Control Register */
9758  mcPWM_CTRL1_16B_tag CTRL11; /* offset: 0x0056 size: 16 bit */
9759  /* Value Register 0 */
9760  mcPWM_VAL_0_16B_tag VAL_01; /* offset: 0x0058 size: 16 bit */
9761  /* Value Register 1 */
9762  mcPWM_VAL_1_16B_tag VAL_11; /* offset: 0x005A size: 16 bit */
9763  /* Value Register 2 */
9764  mcPWM_VAL_2_16B_tag VAL_21; /* offset: 0x005C size: 16 bit */
9765  /* Value Register 3 */
9766  mcPWM_VAL_3_16B_tag VAL_31; /* offset: 0x005E size: 16 bit */
9767  /* Value Register 4 */
9768  mcPWM_VAL_4_16B_tag VAL_41; /* offset: 0x0060 size: 16 bit */
9769  /* Value Register 5 */
9770  mcPWM_VAL_5_16B_tag VAL_51; /* offset: 0x0062 size: 16 bit */
9771  /* Fractional Delay Register A */
9772  mcPWM_FRACA_16B_tag FRACA1; /* offset: 0x0064 size: 16 bit */
9773  /* Fractional Delay Register B */
9774  mcPWM_FRACB_16B_tag FRACB1; /* offset: 0x0066 size: 16 bit */
9775  /* Output Control Register */
9776  mcPWM_OCTRL_16B_tag OCTRL1; /* offset: 0x0068 size: 16 bit */
9777  /* Status Register */
9778  mcPWM_STS_16B_tag STS1; /* offset: 0x006A size: 16 bit */
9779  /* Interrupt Enable Registers */
9780  mcPWM_INTEN_16B_tag INTEN1; /* offset: 0x006C size: 16 bit */
9781  /* DMA Enable Registers */
9782  mcPWM_DMAEN_16B_tag DMAEN1; /* offset: 0x006E size: 16 bit */
9783  /* Output Trigger Control Registers */
9784  mcPWM_TCTRL_16B_tag TCTRL1; /* offset: 0x0070 size: 16 bit */
9785  /* Fault Disable Mapping Registers */
9786  mcPWM_DISMAP_16B_tag DISMAP1; /* offset: 0x0072 size: 16 bit */
9787  /* Deadtime Count Register 0 */
9788  mcPWM_DTCNT0_16B_tag DTCNT01; /* offset: 0x0074 size: 16 bit */
9789  /* Deadtime Count Register 1 */
9790  mcPWM_DTCNT1_16B_tag DTCNT11; /* offset: 0x0076 size: 16 bit */
9791  /* Capture Control A Register */
9792  mcPWM_CAPTCTRLA_16B_tag CAPTCTRLA1; /* offset: 0x0078 size: 16 bit */
9793  /* Capture Compare A Register */
9794  mcPWM_CAPTCMPA_16B_tag CAPTCMPA1; /* offset: 0x007A size: 16 bit */
9795  /* Capture Control B Register */
9796  mcPWM_CAPTCTRLB_16B_tag CAPTCTRLB1; /* offset: 0x007C size: 16 bit */
9797  /* Capture Compare B Register */
9798  mcPWM_CAPTCMPB_16B_tag CAPTCMPB1; /* offset: 0x007E size: 16 bit */
9799  /* Capture Control X Register */
9800  mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX1; /* offset: 0x0080 size: 16 bit */
9801  /* Capture Compare X Register */
9802  mcPWM_CAPTCMPX_16B_tag CAPTCMPX1; /* offset: 0x0082 size: 16 bit */
9803  /* Capture Value 0 Register */
9804  mcPWM_CVAL0_16B_tag CVAL01; /* offset: 0x0084 size: 16 bit */
9805  /* Capture Value 0 Cycle Register */
9806  mcPWM_CVAL0CYC_16B_tag CVAL0CYC1; /* offset: 0x0086 size: 16 bit */
9807  /* Capture Value 1 Register */
9808  mcPWM_CVAL1_16B_tag CVAL11; /* offset: 0x0088 size: 16 bit */
9809  /* Capture Value 1 Cycle Register */
9810  mcPWM_CVAL1CYC_16B_tag CVAL1CYC1; /* offset: 0x008A size: 16 bit */
9811  /* Capture Value 2 Register */
9812  mcPWM_CVAL2_16B_tag CVAL21; /* offset: 0x008C size: 16 bit */
9813  /* Capture Value 2 Cycle Register */
9814  mcPWM_CVAL2CYC_16B_tag CVAL2CYC1; /* offset: 0x008E size: 16 bit */
9815  /* Capture Value 3 Register */
9816  mcPWM_CVAL3_16B_tag CVAL31; /* offset: 0x0090 size: 16 bit */
9817  /* Capture Value 3 Cycle Register */
9818  mcPWM_CVAL3CYC_16B_tag CVAL3CYC1; /* offset: 0x0092 size: 16 bit */
9819  /* Capture Value 4 Register */
9820  mcPWM_CVAL4_16B_tag CVAL41; /* offset: 0x0094 size: 16 bit */
9821  /* Capture Value 4 Cycle Register */
9822  mcPWM_CVAL4CYC_16B_tag CVAL4CYC1; /* offset: 0x0096 size: 16 bit */
9823  /* Capture Value 5 Register */
9824  mcPWM_CVAL5_16B_tag CVAL51; /* offset: 0x0098 size: 16 bit */
9825  /* Capture Value 5 Cycle Register */
9826  mcPWM_CVAL5CYC_16B_tag CVAL5CYC1; /* offset: 0x009A size: 16 bit */
9827  int8_t mcPWM_reserved_009C_I2[4];
9828  /* Counter Register */
9829  mcPWM_CNT_16B_tag CNT2; /* offset: 0x00A0 size: 16 bit */
9830  /* Initial Counter Register */
9831  mcPWM_INIT_16B_tag INIT2; /* offset: 0x00A2 size: 16 bit */
9832  /* Control 2 Register */
9833  mcPWM_CTRL2_16B_tag CTRL22; /* offset: 0x00A4 size: 16 bit */
9834  /* Control Register */
9835  mcPWM_CTRL1_16B_tag CTRL12; /* offset: 0x00A6 size: 16 bit */
9836  /* Value Register 0 */
9837  mcPWM_VAL_0_16B_tag VAL_02; /* offset: 0x00A8 size: 16 bit */
9838  /* Value Register 1 */
9839  mcPWM_VAL_1_16B_tag VAL_12; /* offset: 0x00AA size: 16 bit */
9840  /* Value Register 2 */
9841  mcPWM_VAL_2_16B_tag VAL_22; /* offset: 0x00AC size: 16 bit */
9842  /* Value Register 3 */
9843  mcPWM_VAL_3_16B_tag VAL_32; /* offset: 0x00AE size: 16 bit */
9844  /* Value Register 4 */
9845  mcPWM_VAL_4_16B_tag VAL_42; /* offset: 0x00B0 size: 16 bit */
9846  /* Value Register 5 */
9847  mcPWM_VAL_5_16B_tag VAL_52; /* offset: 0x00B2 size: 16 bit */
9848  /* Fractional Delay Register A */
9849  mcPWM_FRACA_16B_tag FRACA2; /* offset: 0x00B4 size: 16 bit */
9850  /* Fractional Delay Register B */
9851  mcPWM_FRACB_16B_tag FRACB2; /* offset: 0x00B6 size: 16 bit */
9852  /* Output Control Register */
9853  mcPWM_OCTRL_16B_tag OCTRL2; /* offset: 0x00B8 size: 16 bit */
9854  /* Status Register */
9855  mcPWM_STS_16B_tag STS2; /* offset: 0x00BA size: 16 bit */
9856  /* Interrupt Enable Registers */
9857  mcPWM_INTEN_16B_tag INTEN2; /* offset: 0x00BC size: 16 bit */
9858  /* DMA Enable Registers */
9859  mcPWM_DMAEN_16B_tag DMAEN2; /* offset: 0x00BE size: 16 bit */
9860  /* Output Trigger Control Registers */
9861  mcPWM_TCTRL_16B_tag TCTRL2; /* offset: 0x00C0 size: 16 bit */
9862  /* Fault Disable Mapping Registers */
9863  mcPWM_DISMAP_16B_tag DISMAP2; /* offset: 0x00C2 size: 16 bit */
9864  /* Deadtime Count Register 0 */
9865  mcPWM_DTCNT0_16B_tag DTCNT02; /* offset: 0x00C4 size: 16 bit */
9866  /* Deadtime Count Register 1 */
9867  mcPWM_DTCNT1_16B_tag DTCNT12; /* offset: 0x00C6 size: 16 bit */
9868  /* Capture Control A Register */
9869  mcPWM_CAPTCTRLA_16B_tag CAPTCTRLA2; /* offset: 0x00C8 size: 16 bit */
9870  /* Capture Compare A Register */
9871  mcPWM_CAPTCMPA_16B_tag CAPTCMPA2; /* offset: 0x00CA size: 16 bit */
9872  /* Capture Control B Register */
9873  mcPWM_CAPTCTRLB_16B_tag CAPTCTRLB2; /* offset: 0x00CC size: 16 bit */
9874  /* Capture Compare B Register */
9875  mcPWM_CAPTCMPB_16B_tag CAPTCMPB2; /* offset: 0x00CE size: 16 bit */
9876  /* Capture Control X Register */
9877  mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX2; /* offset: 0x00D0 size: 16 bit */
9878  /* Capture Compare X Register */
9879  mcPWM_CAPTCMPX_16B_tag CAPTCMPX2; /* offset: 0x00D2 size: 16 bit */
9880  /* Capture Value 0 Register */
9881  mcPWM_CVAL0_16B_tag CVAL02; /* offset: 0x00D4 size: 16 bit */
9882  /* Capture Value 0 Cycle Register */
9883  mcPWM_CVAL0CYC_16B_tag CVAL0CYC2; /* offset: 0x00D6 size: 16 bit */
9884  /* Capture Value 1 Register */
9885  mcPWM_CVAL1_16B_tag CVAL12; /* offset: 0x00D8 size: 16 bit */
9886  /* Capture Value 1 Cycle Register */
9887  mcPWM_CVAL1CYC_16B_tag CVAL1CYC2; /* offset: 0x00DA size: 16 bit */
9888  /* Capture Value 2 Register */
9889  mcPWM_CVAL2_16B_tag CVAL22; /* offset: 0x00DC size: 16 bit */
9890  /* Capture Value 2 Cycle Register */
9891  mcPWM_CVAL2CYC_16B_tag CVAL2CYC2; /* offset: 0x00DE size: 16 bit */
9892  /* Capture Value 3 Register */
9893  mcPWM_CVAL3_16B_tag CVAL32; /* offset: 0x00E0 size: 16 bit */
9894  /* Capture Value 3 Cycle Register */
9895  mcPWM_CVAL3CYC_16B_tag CVAL3CYC2; /* offset: 0x00E2 size: 16 bit */
9896  /* Capture Value 4 Register */
9897  mcPWM_CVAL4_16B_tag CVAL42; /* offset: 0x00E4 size: 16 bit */
9898  /* Capture Value 4 Cycle Register */
9899  mcPWM_CVAL4CYC_16B_tag CVAL4CYC2; /* offset: 0x00E6 size: 16 bit */
9900  /* Capture Value 5 Register */
9901  mcPWM_CVAL5_16B_tag CVAL52; /* offset: 0x00E8 size: 16 bit */
9902  /* Capture Value 5 Cycle Register */
9903  mcPWM_CVAL5CYC_16B_tag CVAL5CYC2; /* offset: 0x00EA size: 16 bit */
9904  int8_t mcPWM_reserved_00EC_I2[4];
9905  /* Counter Register */
9906  mcPWM_CNT_16B_tag CNT3; /* offset: 0x00F0 size: 16 bit */
9907  /* Initial Counter Register */
9908  mcPWM_INIT_16B_tag INIT3; /* offset: 0x00F2 size: 16 bit */
9909  /* Control 2 Register */
9910  mcPWM_CTRL2_16B_tag CTRL23; /* offset: 0x00F4 size: 16 bit */
9911  /* Control Register */
9912  mcPWM_CTRL1_16B_tag CTRL13; /* offset: 0x00F6 size: 16 bit */
9913  /* Value Register 0 */
9914  mcPWM_VAL_0_16B_tag VAL_03; /* offset: 0x00F8 size: 16 bit */
9915  /* Value Register 1 */
9916  mcPWM_VAL_1_16B_tag VAL_13; /* offset: 0x00FA size: 16 bit */
9917  /* Value Register 2 */
9918  mcPWM_VAL_2_16B_tag VAL_23; /* offset: 0x00FC size: 16 bit */
9919  /* Value Register 3 */
9920  mcPWM_VAL_3_16B_tag VAL_33; /* offset: 0x00FE size: 16 bit */
9921  /* Value Register 4 */
9922  mcPWM_VAL_4_16B_tag VAL_43; /* offset: 0x0100 size: 16 bit */
9923  /* Value Register 5 */
9924  mcPWM_VAL_5_16B_tag VAL_53; /* offset: 0x0102 size: 16 bit */
9925  /* Fractional Delay Register A */
9926  mcPWM_FRACA_16B_tag FRACA3; /* offset: 0x0104 size: 16 bit */
9927  /* Fractional Delay Register B */
9928  mcPWM_FRACB_16B_tag FRACB3; /* offset: 0x0106 size: 16 bit */
9929  /* Output Control Register */
9930  mcPWM_OCTRL_16B_tag OCTRL3; /* offset: 0x0108 size: 16 bit */
9931  /* Status Register */
9932  mcPWM_STS_16B_tag STS3; /* offset: 0x010A size: 16 bit */
9933  /* Interrupt Enable Registers */
9934  mcPWM_INTEN_16B_tag INTEN3; /* offset: 0x010C size: 16 bit */
9935  /* DMA Enable Registers */
9936  mcPWM_DMAEN_16B_tag DMAEN3; /* offset: 0x010E size: 16 bit */
9937  /* Output Trigger Control Registers */
9938  mcPWM_TCTRL_16B_tag TCTRL3; /* offset: 0x0110 size: 16 bit */
9939  /* Fault Disable Mapping Registers */
9940  mcPWM_DISMAP_16B_tag DISMAP3; /* offset: 0x0112 size: 16 bit */
9941  /* Deadtime Count Register 0 */
9942  mcPWM_DTCNT0_16B_tag DTCNT03; /* offset: 0x0114 size: 16 bit */
9943  /* Deadtime Count Register 1 */
9944  mcPWM_DTCNT1_16B_tag DTCNT13; /* offset: 0x0116 size: 16 bit */
9945  /* Capture Control A Register */
9946  mcPWM_CAPTCTRLA_16B_tag CAPTCTRLA3; /* offset: 0x0118 size: 16 bit */
9947  /* Capture Compare A Register */
9948  mcPWM_CAPTCMPA_16B_tag CAPTCMPA3; /* offset: 0x011A size: 16 bit */
9949  /* Capture Control B Register */
9950  mcPWM_CAPTCTRLB_16B_tag CAPTCTRLB3; /* offset: 0x011C size: 16 bit */
9951  /* Capture Compare B Register */
9952  mcPWM_CAPTCMPB_16B_tag CAPTCMPB3; /* offset: 0x011E size: 16 bit */
9953  /* Capture Control X Register */
9954  mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX3; /* offset: 0x0120 size: 16 bit */
9955  /* Capture Compare X Register */
9956  mcPWM_CAPTCMPX_16B_tag CAPTCMPX3; /* offset: 0x0122 size: 16 bit */
9957  /* Capture Value 0 Register */
9958  mcPWM_CVAL0_16B_tag CVAL03; /* offset: 0x0124 size: 16 bit */
9959  /* Capture Value 0 Cycle Register */
9960  mcPWM_CVAL0CYC_16B_tag CVAL0CYC3; /* offset: 0x0126 size: 16 bit */
9961  /* Capture Value 1 Register */
9962  mcPWM_CVAL1_16B_tag CVAL13; /* offset: 0x0128 size: 16 bit */
9963  /* Capture Value 1 Cycle Register */
9964  mcPWM_CVAL1CYC_16B_tag CVAL1CYC3; /* offset: 0x012A size: 16 bit */
9965  /* Capture Value 2 Register */
9966  mcPWM_CVAL2_16B_tag CVAL23; /* offset: 0x012C size: 16 bit */
9967  /* Capture Value 2 Cycle Register */
9968  mcPWM_CVAL2CYC_16B_tag CVAL2CYC3; /* offset: 0x012E size: 16 bit */
9969  /* Capture Value 3 Register */
9970  mcPWM_CVAL3_16B_tag CVAL33; /* offset: 0x0130 size: 16 bit */
9971  /* Capture Value 3 Cycle Register */
9972  mcPWM_CVAL3CYC_16B_tag CVAL3CYC3; /* offset: 0x0132 size: 16 bit */
9973  /* Capture Value 4 Register */
9974  mcPWM_CVAL4_16B_tag CVAL43; /* offset: 0x0134 size: 16 bit */
9975  /* Capture Value 4 Cycle Register */
9976  mcPWM_CVAL4CYC_16B_tag CVAL4CYC3; /* offset: 0x0136 size: 16 bit */
9977  /* Capture Value 5 Register */
9978  mcPWM_CVAL5_16B_tag CVAL53; /* offset: 0x0138 size: 16 bit */
9979  /* Capture Value 5 Cycle Register */
9980  mcPWM_CVAL5CYC_16B_tag CVAL5CYC3; /* offset: 0x013A size: 16 bit */
9981  int8_t mcPWM_reserved_013C_E2[4];
9982  };
9983 
9984  };
9985  /* Output Enable Register */
9986  mcPWM_OUTEN_16B_tag OUTEN; /* offset: 0x0140 size: 16 bit */
9987  /* Mask Register */
9988  mcPWM_MASK_16B_tag MASK; /* offset: 0x0142 size: 16 bit */
9989  /* Software Controlled Output Register */
9990  mcPWM_SWCOUT_16B_tag SWCOUT; /* offset: 0x0144 size: 16 bit */
9991  /* Deadtime Source Select Register */
9992  mcPWM_DTSRCSEL_16B_tag DTSRCSEL; /* offset: 0x0146 size: 16 bit */
9993  /* Master Control Register */
9994  mcPWM_MCTRL_16B_tag MCTRL; /* offset: 0x0148 size: 16 bit */
9995  int8_t mcPWM_reserved_014A[2];
9996  /* Fault Control Register */
9997  mcPWM_FCTRL_16B_tag FCTRL; /* offset: 0x014C size: 16 bit */
9998  /* Fault Status Register */
9999  mcPWM_FSTS_16B_tag FSTS; /* offset: 0x014E size: 16 bit */
10000  /* Fault Filter Register */
10001  mcPWM_FFILT_16B_tag FFILT; /* offset: 0x0150 size: 16 bit */
10002  } mcPWM_tag;
10003 
10004 
10005 #define mcPWM_A (*(volatile mcPWM_tag *) 0xFFE24000UL)
10006 #define mcPWM_B (*(volatile mcPWM_tag *) 0xFFE28000UL)
10007 
10008 
10009 
10010 /****************************************************************/
10011 /* */
10012 /* Module: LINFLEX */
10013 /* */
10014 /****************************************************************/
10015 
10016  typedef union { /* LIN Control Register */
10017  vuint32_t R;
10018  struct {
10019  vuint32_t:16;
10020  vuint32_t CCD:1; /* Checksum Calculation Disable */
10021  vuint32_t CFD:1; /* Checksum Field Disable */
10022  vuint32_t LASE:1; /* LIN Auto Synchronization Enable */
10023 #ifndef USE_FIELD_ALIASES_LINFLEX
10024  vuint32_t AUTOWU:1; /* Auto Wake Up */
10025 #else
10026  vuint32_t AWUM:1; /* deprecated name - please avoid */
10027 #endif
10028  vuint32_t MBL:4; /* Master Break Length */
10029  vuint32_t BF:1; /* By-Pass Filter */
10030 #ifndef USE_FIELD_ALIASES_LINFLEX
10031  vuint32_t SLFM:1; /* Selftest Mode */
10032 #else
10033  vuint32_t SFTM:1; /* deprecated name - please avoid */
10034 #endif
10035  vuint32_t LBKM:1; /* Loopback Mode */
10036  vuint32_t MME:1; /* Master Mode Enable */
10037 #ifndef USE_FIELD_ALIASES_LINFLEX
10038  vuint32_t SSBL:1; /* Slave Mode Synch Break Length */
10039 #else
10040  vuint32_t SSDT:1; /* deprecated name - please avoid */
10041 #endif
10042  vuint32_t RBLM:1; /* Receiver Buffer Locked Mode */
10043  vuint32_t SLEEP:1; /* Sleep Mode Request */
10044  vuint32_t INIT:1; /* Initialization Mode Request */
10045  } B;
10046  } LINFLEX_LINCR1_32B_tag;
10047 
10048  typedef union { /* LIN Interrupt Enable Register */
10049  vuint32_t R;
10050  struct {
10051  vuint32_t:16;
10052  vuint32_t SZIE:1; /* Stuck at Zero Interrupt Enable */
10053  vuint32_t OCIE:1; /* Output Compare Interrupt Enable */
10054  vuint32_t BEIE:1; /* Bit Error Interrupt Enable */
10055  vuint32_t CEIE:1; /* Checksum Error Interrupt Enable */
10056  vuint32_t HEIE:1; /* Header Error Interrupt Enable */
10057  vuint32_t:2;
10058  vuint32_t FEIE:1; /* Frame Error Interrupt Enable */
10059  vuint32_t BOIE:1; /* Buffer Overrun Error Interrupt Enable */
10060  vuint32_t LSIE:1; /* LIN State Interrupt Enable */
10061  vuint32_t WUIE:1; /* Wakeup Interrupt Enable */
10062  vuint32_t DBFIE:1; /* Data Buffer Full Interrupt Enable */
10063 #ifndef USE_FIELD_ALIASES_LINFLEX
10064  vuint32_t DBEIE_TOIE:1; /* Data Buffer Empty Interrupt Enable */
10065 #else
10066  vuint32_t DBEIE:1; /* deprecated name - please avoid */
10067 #endif
10068  vuint32_t DRIE:1; /* Data Reception complete Interrupt Enable */
10069  vuint32_t DTIE:1; /* Data Transmitted Interrupt Enable */
10070  vuint32_t HRIE:1; /* Header Received Interrupt Enable */
10071  } B;
10072  } LINFLEX_LINIER_32B_tag;
10073 
10074  typedef union { /* LIN Status Register */
10075  vuint32_t R;
10076  struct {
10077  vuint32_t:16;
10078  vuint32_t LINS:4; /* LIN State */
10079  vuint32_t:2;
10080  vuint32_t RMB:1; /* Release Message Buffer */
10081  vuint32_t:1;
10082 #ifndef USE_FIELD_ALIASES_LINFLEX
10083  vuint32_t RXBUSY:1; /* Receiver Busy Flag */
10084 #else
10085  vuint32_t RBSY:1; /* deprecated name - please avoid */
10086 #endif
10087 #ifndef USE_FIELD_ALIASES_LINFLEX
10088  vuint32_t RDI:1; /* LIN Receive Signal */
10089 #else
10090  vuint32_t RPS:1; /* deprecated name - please avoid */
10091 #endif
10092  vuint32_t WUF:1; /* Wake Up Flag */
10093  vuint32_t DBFF:1; /* Data Buffer Full Flag */
10094  vuint32_t DBEF:1; /* Data Buffer Empty Flag */
10095  vuint32_t DRF:1; /* Data Reception Completed Flag */
10096  vuint32_t DTF:1; /* Data Transmission Completed Flag */
10097  vuint32_t HRF:1; /* Header Received Flag */
10098  } B;
10099  } LINFLEX_LINSR_32B_tag;
10100 
10101  typedef union { /* LIN Error Status Register */
10102  vuint32_t R;
10103  struct {
10104  vuint32_t:16;
10105  vuint32_t SZF:1; /* Stuck at Zero Flag */
10106  vuint32_t OCF:1; /* Output Compare Flag */
10107  vuint32_t BEF:1; /* Bit Error Flag */
10108  vuint32_t CEF:1; /* Checksum Error Flag */
10109  vuint32_t SFEF:1; /* Sync Field Error Flag */
10110 #ifndef USE_FIELD_ALIASES_LINFLEX
10111  vuint32_t SDEF:1; /* Sync Delimiter Error Flag */
10112 #else
10113  vuint32_t BDEF:1; /* deprecated name - please avoid */
10114 #endif
10115  vuint32_t IDPEF:1; /* ID Parity Error Flag */
10116  vuint32_t FEF:1; /* Framing Error Flag */
10117  vuint32_t BOF:1; /* Buffer Overrun Flag */
10118  vuint32_t:6;
10119  vuint32_t NF:1; /* Noise Flag */
10120  } B;
10121  } LINFLEX_LINESR_32B_tag;
10122 
10123  typedef union { /* UART Mode Control Register */
10124  vuint32_t R;
10125  struct {
10126  vuint32_t:16;
10127  vuint32_t TDFL_TFC:3; /* Transmitter Data Field Length/TX FIFO Counter */
10128  vuint32_t RDFL_RFC0:3; /* Reception Data Field Length/RX FIFO Counter */
10129  vuint32_t RFBM:1; /* RX FIFO/ Buffer Mode */
10130  vuint32_t TFBM:1; /* TX FIFO/ Buffer Mode */
10131  vuint32_t WL1:1; /* Word Length in UART mode - bit 1 */
10132  vuint32_t PC1:1; /* Parity Check - bit 1 */
10133  vuint32_t RXEN:1; /* Receiver Enable */
10134  vuint32_t TXEN:1; /* Transmitter Enable */
10135 #ifndef USE_FIELD_ALIASES_LINFLEX
10136  vuint32_t PC0:1; /* Parity Check - bit 0 */
10137 #else
10138  vuint32_t OP:1; /* deprecated name - please avoid */
10139 #endif
10140  vuint32_t PCE:1; /* Parity Control Enable */
10141 #ifndef USE_FIELD_ALIASES_LINFLEX
10142  vuint32_t WL0:1; /* Word Length in UART Mode - bit 0 */
10143 #else
10144  vuint32_t WL:1; /* deprecated name - please avoid */
10145 #endif
10146  vuint32_t UART:1; /* UART Mode */
10147  } B;
10148  } LINFLEX_UARTCR_32B_tag;
10149 
10150  typedef union { /* UART Mode Status Register */
10151  vuint32_t R;
10152  struct {
10153  vuint32_t:16;
10154  vuint32_t SZF:1; /* Stuck at Zero Flag */
10155  vuint32_t OCF:1; /* Output Compare Flag */
10156  vuint32_t PE:4; /* Parity Error Flag */
10157  vuint32_t RMB:1; /* Release Message Buffer */
10158  vuint32_t FEF:1; /* Framing Error Flag */
10159  vuint32_t BOF:1; /* Buffer Overrun Flag */
10160  vuint32_t RDI:1; /* Receiver Data Input Signal */
10161  vuint32_t WUF:1; /* Wakeup Flag */
10162  vuint32_t:1;
10163  vuint32_t TO:1; /* Time Out */
10164 #ifndef USE_FIELD_ALIASES_LINFLEX
10165  vuint32_t DRF_RFE:1; /* Data Reception Completed Flag/RX FIFO Empty Flag */
10166 #else
10167  vuint32_t DRF:1; /* deprecated name - please avoid */
10168 #endif
10169 #ifndef USE_FIELD_ALIASES_LINFLEX
10170  vuint32_t DTF_TFF:1; /* Data Transmission Completed Flag/TX FIFO Full Flag */
10171 #else
10172  vuint32_t DTF:1; /* deprecated name - please avoid */
10173 #endif
10174  vuint32_t NF:1; /* Noise Flag */
10175  } B;
10176  } LINFLEX_UARTSR_32B_tag;
10177 
10178  typedef union { /* LIN Time-Out Control Status Register */
10179  vuint32_t R;
10180  struct {
10181  vuint32_t:21;
10182 #ifndef USE_FIELD_ALIASES_LINFLEX
10183  vuint32_t MODE:1; /* Time-out Counter Mode */
10184 #else
10185  vuint32_t LTOM:1; /* deprecated name - please avoid */
10186 #endif
10187  vuint32_t IOT:1; /* Idle on Timeout */
10188  vuint32_t TOCE:1; /* Time-Out Counter Enable */
10189  vuint32_t CNT:8; /* Counter Value */
10190  } B;
10191  } LINFLEX_LINTCSR_32B_tag;
10192 
10193  typedef union { /* LIN Output Compare Register */
10194  vuint32_t R;
10195  struct {
10196  vuint32_t:16;
10197  vuint32_t OC2:8; /* Output Compare Value 2 */
10198  vuint32_t OC1:8; /* Output Compare Value 1 */
10199  } B;
10200  } LINFLEX_LINOCR_32B_tag;
10201 
10202  typedef union { /* LIN Time-Out Control Register */
10203  vuint32_t R;
10204  struct {
10205  vuint32_t:20;
10206  vuint32_t RTO:4; /* Response Time-Out Value */
10207  vuint32_t:1;
10208  vuint32_t HTO:7; /* Header Time-Out Value */
10209  } B;
10210  } LINFLEX_LINTOCR_32B_tag;
10211 
10212  typedef union { /* LIN Fractional Baud Rate Register */
10213  vuint32_t R;
10214  struct {
10215  vuint32_t:28;
10216 #ifndef USE_FIELD_ALIASES_LINFLEX
10217  vuint32_t FBR:4; /* Fractional Baud Rates */
10218 #else
10219  vuint32_t DIV_F:4; /* deprecated name - please avoid */
10220 #endif
10221  } B;
10222  } LINFLEX_LINFBRR_32B_tag;
10223 
10224  typedef union { /* LIN Integer Baud Rate Register */
10225  vuint32_t R;
10226  struct {
10227  vuint32_t:13;
10228 #ifndef USE_FIELD_ALIASES_LINFLEX
10229  vuint32_t IBR:19; /* Integer Baud Rates */
10230 #else
10231  vuint32_t DIV_M:19; /* deprecated name - please avoid */
10232 #endif
10233  } B;
10234  } LINFLEX_LINIBRR_32B_tag;
10235 
10236  typedef union { /* LIN Checksum Field Register */
10237  vuint32_t R;
10238  struct {
10239  vuint32_t:24;
10240  vuint32_t CF:8; /* Checksum Bits */
10241  } B;
10242  } LINFLEX_LINCFR_32B_tag;
10243 
10244  typedef union { /* LIN Control Register 2 */
10245  vuint32_t R;
10246  struct {
10247  vuint32_t:17;
10248  vuint32_t IOBE:1; /* Idle on Bit Error */
10249  vuint32_t IOPE:1; /* Idle on Identifier Parity Error */
10250  vuint32_t WURQ:1; /* Wakeup Generate Request */
10251  vuint32_t DDRQ:1; /* Data Discard Request */
10252  vuint32_t DTRQ:1; /* Data Transmission Request */
10253  vuint32_t ABRQ:1; /* Abort Request */
10254  vuint32_t HTRQ:1; /* Header Transmission Request */
10255  vuint32_t:8;
10256  } B;
10257  } LINFLEX_LINCR2_32B_tag;
10258 
10259  typedef union { /* Buffer Identifier Register */
10260  vuint32_t R;
10261  struct {
10262  vuint32_t:16;
10263  vuint32_t DFL:6; /* Data Field Length */
10264  vuint32_t DIR:1; /* Direction */
10265  vuint32_t CCS:1; /* Classic Checksum */
10266  vuint32_t:2;
10267  vuint32_t ID:6; /* Identifier */
10268  } B;
10269  } LINFLEX_BIDR_32B_tag;
10270 
10271  typedef union { /* Buffer Data Register Least Significant */
10272  vuint32_t R;
10273  struct {
10274  vuint32_t DATA3:8; /* Data3 */
10275  vuint32_t DATA2:8; /* Data2 */
10276  vuint32_t DATA1:8; /* Data1 */
10277  vuint32_t DATA0:8; /* Data0 */
10278  } B;
10279  } LINFLEX_BDRL_32B_tag;
10280 
10281  typedef union { /* Buffer Data Register Most Significant */
10282  vuint32_t R;
10283  struct {
10284  vuint32_t DATA7:8; /* Data7 */
10285  vuint32_t DATA6:8; /* Data6 */
10286  vuint32_t DATA5:8; /* Data5 */
10287  vuint32_t DATA4:8; /* Data4 */
10288  } B;
10289  } LINFLEX_BDRM_32B_tag;
10290 
10291  typedef union { /* Identifier Filter Enable Register */
10292  vuint32_t R;
10293  struct {
10294  vuint32_t:24;
10295  vuint32_t FACT:8; /* Filter Active */
10296  } B;
10297  } LINFLEX_IFER_32B_tag;
10298 
10299  typedef union { /* Identifier Filter Match Index */
10300  vuint32_t R;
10301  struct {
10302  vuint32_t:28;
10303  vuint32_t IFMI_IFMI:4; /* Filter Match Index */
10304  } B;
10305  } LINFLEX_IFMI_32B_tag;
10306 
10307  typedef union { /* Identifier Filter Mode Register */
10308  vuint32_t R;
10309  struct {
10310  vuint32_t:28;
10311  vuint32_t IFM:4; /* Filter Mode */
10312  } B;
10313  } LINFLEX_IFMR_32B_tag;
10314 
10315 
10316  /* Register layout for all registers IFCR... */
10317 
10318  typedef union { /* Identifier Filter Control Register */
10319  vuint32_t R;
10320  struct {
10321  vuint32_t:16;
10322  vuint32_t DFL:6; /* Data Field Length */
10323  vuint32_t DIR:1; /* Direction */
10324  vuint32_t CCS:1; /* Classic Checksum */
10325  vuint32_t:2;
10326  vuint32_t ID:6; /* Identifier */
10327  } B;
10328  } LINFLEX_IFCR_32B_tag;
10329 
10330  typedef union { /* Global Control Register */
10331  vuint32_t R;
10332  struct {
10333  vuint32_t:26;
10334  vuint32_t TDFBM:1; /* Transmit Data First Bit MSB */
10335  vuint32_t RDFBM:1; /* Received Data First Bit MSB */
10336  vuint32_t TDLIS:1; /* Transmit Data Level Inversion Selection */
10337  vuint32_t RDLIS:1; /* Received Data Level Inversion Selection */
10338  vuint32_t STOP:1; /* 1/2 stop bit configuration */
10339  vuint32_t SR:1; /* Soft Reset */
10340  } B;
10341  } LINFLEX_GCR_32B_tag;
10342 
10343  typedef union { /* UART Preset Time Out Register */
10344  vuint32_t R;
10345  struct {
10346  vuint32_t:20;
10347  vuint32_t PTO:12; /* Preset Time Out */
10348  } B;
10349  } LINFLEX_UARTPTO_32B_tag;
10350 
10351  typedef union { /* UART Current Time Out Register */
10352  vuint32_t R;
10353  struct {
10354  vuint32_t:20;
10355  vuint32_t CTO:12; /* Current Time Out */
10356  } B;
10357  } LINFLEX_UARTCTO_32B_tag;
10358 
10359  typedef union { /* DMA TX Enable Register */
10360  vuint32_t R;
10361  struct {
10362  vuint32_t:17;
10363  vuint32_t DTE:15; /* DMA Tx channel Enable */
10364  } B;
10365  } LINFLEX_DMATXE_32B_tag;
10366 
10367  typedef union { /* DMA RX Enable Register */
10368  vuint32_t R;
10369  struct {
10370  vuint32_t:17;
10371  vuint32_t DRE:15; /* DMA Rx channel Enable */
10372  } B;
10373  } LINFLEX_DMARXE_32B_tag;
10374 
10375 
10376 
10377  typedef struct LINFLEX_tag{ /* start of LINFLEX_tag */
10378  /* LIN Control Register */
10379  LINFLEX_LINCR1_32B_tag LINCR1; /* offset: 0x0000 size: 32 bit */
10380  /* LIN Interrupt Enable Register */
10381  LINFLEX_LINIER_32B_tag LINIER; /* offset: 0x0004 size: 32 bit */
10382  /* LIN Status Register */
10383  LINFLEX_LINSR_32B_tag LINSR; /* offset: 0x0008 size: 32 bit */
10384  /* LIN Error Status Register */
10385  LINFLEX_LINESR_32B_tag LINESR; /* offset: 0x000C size: 32 bit */
10386  /* UART Mode Control Register */
10387  LINFLEX_UARTCR_32B_tag UARTCR; /* offset: 0x0010 size: 32 bit */
10388  /* UART Mode Status Register */
10389  LINFLEX_UARTSR_32B_tag UARTSR; /* offset: 0x0014 size: 32 bit */
10390  /* LIN Time-Out Control Status Register */
10391  LINFLEX_LINTCSR_32B_tag LINTCSR; /* offset: 0x0018 size: 32 bit */
10392  /* LIN Output Compare Register */
10393  LINFLEX_LINOCR_32B_tag LINOCR; /* offset: 0x001C size: 32 bit */
10394  /* LIN Time-Out Control Register */
10395  LINFLEX_LINTOCR_32B_tag LINTOCR; /* offset: 0x0020 size: 32 bit */
10396  /* LIN Fractional Baud Rate Register */
10397  LINFLEX_LINFBRR_32B_tag LINFBRR; /* offset: 0x0024 size: 32 bit */
10398  /* LIN Integer Baud Rate Register */
10399  LINFLEX_LINIBRR_32B_tag LINIBRR; /* offset: 0x0028 size: 32 bit */
10400  /* LIN Checksum Field Register */
10401  LINFLEX_LINCFR_32B_tag LINCFR; /* offset: 0x002C size: 32 bit */
10402  /* LIN Control Register 2 */
10403  LINFLEX_LINCR2_32B_tag LINCR2; /* offset: 0x0030 size: 32 bit */
10404  /* Buffer Identifier Register */
10405  LINFLEX_BIDR_32B_tag BIDR; /* offset: 0x0034 size: 32 bit */
10406  /* Buffer Data Register Least Significant */
10407  LINFLEX_BDRL_32B_tag BDRL; /* offset: 0x0038 size: 32 bit */
10408  /* Buffer Data Register Most Significant */
10409  LINFLEX_BDRM_32B_tag BDRM; /* offset: 0x003C size: 32 bit */
10410  /* Identifier Filter Enable Register */
10411  LINFLEX_IFER_32B_tag IFER; /* offset: 0x0040 size: 32 bit */
10412  /* Identifier Filter Match Index */
10413  LINFLEX_IFMI_32B_tag IFMI; /* offset: 0x0044 size: 32 bit */
10414  /* Identifier Filter Mode Register */
10415  LINFLEX_IFMR_32B_tag IFMR; /* offset: 0x0048 size: 32 bit */
10416  union {
10417  /* Identifier Filter Control Register */
10418  LINFLEX_IFCR_32B_tag IFCR[8]; /* offset: 0x004C (0x0004 x 8) */
10419 
10420  struct {
10421  /* Identifier Filter Control Register */
10422  LINFLEX_IFCR_32B_tag IFCR0; /* offset: 0x004C size: 32 bit */
10423  LINFLEX_IFCR_32B_tag IFCR1; /* offset: 0x0050 size: 32 bit */
10424  LINFLEX_IFCR_32B_tag IFCR2; /* offset: 0x0054 size: 32 bit */
10425  LINFLEX_IFCR_32B_tag IFCR3; /* offset: 0x0058 size: 32 bit */
10426  LINFLEX_IFCR_32B_tag IFCR4; /* offset: 0x005C size: 32 bit */
10427  LINFLEX_IFCR_32B_tag IFCR5; /* offset: 0x0060 size: 32 bit */
10428  LINFLEX_IFCR_32B_tag IFCR6; /* offset: 0x0064 size: 32 bit */
10429  LINFLEX_IFCR_32B_tag IFCR7; /* offset: 0x0068 size: 32 bit */
10430  };
10431 
10432  };
10433  int8_t LINFLEX_reserved_006C[32];
10434  /* Global Control Register */
10435  LINFLEX_GCR_32B_tag GCR; /* offset: 0x008C size: 32 bit */
10436  /* UART Preset Time Out Register */
10437  LINFLEX_UARTPTO_32B_tag UARTPTO; /* offset: 0x0090 size: 32 bit */
10438  /* UART Current Time Out Register */
10439  LINFLEX_UARTCTO_32B_tag UARTCTO; /* offset: 0x0094 size: 32 bit */
10440  /* DMA TX Enable Register */
10441  LINFLEX_DMATXE_32B_tag DMATXE; /* offset: 0x0098 size: 32 bit */
10442  /* DMA RX Enable Register */
10443  LINFLEX_DMARXE_32B_tag DMARXE; /* offset: 0x009C size: 32 bit */
10444  } LINFLEX_tag;
10445 
10446 
10447 #define LINFLEX0 (*(volatile LINFLEX_tag *) 0xFFE40000UL)
10448 #define LINFLEX1 (*(volatile LINFLEX_tag *) 0xFFE44000UL)
10449 
10450 
10451 
10452 /****************************************************************/
10453 /* */
10454 /* Module: CRC */
10455 /* */
10456 /****************************************************************/
10457 
10458 
10459  /* Register layout for all registers CFG... */
10460 
10461  typedef union { /* CRC_CFG - CRC Configuration register */
10462  vuint32_t R;
10463  vuint8_t BYTE[4]; /* individual bytes can be accessed */
10464  vuint16_t HALF[2]; /* individual halfwords can be accessed */
10465  vuint32_t WORD; /* individual words can be accessed */
10466  struct {
10467  vuint32_t:29;
10468  vuint32_t POLYG:1; /* Polynomal selection 0- CRC-CCITT, 1- CRC-CRC-32 INV selection */
10469  vuint32_t SWAP:1; /* SWAP selection */
10470  vuint32_t INV:1; /* INV selection */
10471  } B;
10472  } CRC_CFG_32B_tag;
10473 
10474 
10475  /* Register layout for all registers INP... */
10476 
10477  typedef union { /* CRC_INP - CRC Input register */
10478  vuint32_t R;
10479  vuint8_t BYTE[4]; /* individual bytes can be accessed */
10480  vuint16_t HALF[2]; /* individual halfwords can be accessed */
10481  vuint32_t WORD; /* individual words can be accessed */
10482  } CRC_INP_32B_tag;
10483 
10484 
10485  /* Register layout for all registers CSTAT... */
10486 
10487  typedef union { /* CRC_STATUS - CRC Status register */
10488  vuint32_t R;
10489  vuint8_t BYTE[4]; /* individual bytes can be accessed */
10490  vuint16_t HALF[2]; /* individual halfwords can be accessed */
10491  vuint32_t WORD; /* individual words can be accessed */
10492  } CRC_CSTAT_32B_tag;
10493 
10494 
10495  /* Register layout for all registers OUTP... */
10496 
10497  typedef union { /* CRC_STATUS - CRC OUTPUT register */
10498  vuint32_t R;
10499  vuint8_t BYTE[4]; /* individual bytes can be accessed */
10500  vuint16_t HALF[2]; /* individual halfwords can be accessed */
10501  vuint32_t WORD; /* individual words can be accessed */
10502  } CRC_OUTP_32B_tag;
10503 
10504 
10505  typedef struct CRC_CNTX_struct_tag {
10506 
10507  /* CRC_CFG - CRC Configuration register */
10508  CRC_CFG_32B_tag CFG; /* relative offset: 0x0000 */
10509  /* CRC_INP - CRC Input register */
10510  CRC_INP_32B_tag INP; /* relative offset: 0x0004 */
10511  /* CRC_STATUS - CRC Status register */
10512  CRC_CSTAT_32B_tag CSTAT; /* relative offset: 0x0008 */
10513  /* CRC_STATUS - CRC OUTPUT register */
10514  CRC_OUTP_32B_tag OUTP; /* relative offset: 0x000C */
10515 
10516  } CRC_CNTX_tag;
10517 
10518 
10519  typedef struct CRC_struct_tag { /* start of CRC_tag */
10520  union {
10521  /* Register set CNTX */
10522  CRC_CNTX_tag CNTX[3]; /* offset: 0x0000 (0x0010 x 3) */
10523 
10524  struct {
10525  /* CRC_CFG - CRC Configuration register */
10526  CRC_CFG_32B_tag CFG0; /* offset: 0x0000 size: 32 bit */
10527  /* CRC_INP - CRC Input register */
10528  CRC_INP_32B_tag INP0; /* offset: 0x0004 size: 32 bit */
10529  /* CRC_STATUS - CRC Status register */
10530  CRC_CSTAT_32B_tag CSTAT0; /* offset: 0x0008 size: 32 bit */
10531  /* CRC_STATUS - CRC OUTPUT register */
10532  CRC_OUTP_32B_tag OUTP0; /* offset: 0x000C size: 32 bit */
10533  /* CRC_CFG - CRC Configuration register */
10534  CRC_CFG_32B_tag CFG1; /* offset: 0x0010 size: 32 bit */
10535  /* CRC_INP - CRC Input register */
10536  CRC_INP_32B_tag INP1; /* offset: 0x0014 size: 32 bit */
10537  /* CRC_STATUS - CRC Status register */
10538  CRC_CSTAT_32B_tag CSTAT1; /* offset: 0x0018 size: 32 bit */
10539  /* CRC_STATUS - CRC OUTPUT register */
10540  CRC_OUTP_32B_tag OUTP1; /* offset: 0x001C size: 32 bit */
10541  /* CRC_CFG - CRC Configuration register */
10542  CRC_CFG_32B_tag CFG2; /* offset: 0x0020 size: 32 bit */
10543  /* CRC_INP - CRC Input register */
10544  CRC_INP_32B_tag INP2; /* offset: 0x0024 size: 32 bit */
10545  /* CRC_STATUS - CRC Status register */
10546  CRC_CSTAT_32B_tag CSTAT2; /* offset: 0x0028 size: 32 bit */
10547  /* CRC_STATUS - CRC OUTPUT register */
10548  CRC_OUTP_32B_tag OUTP2; /* offset: 0x002C size: 32 bit */
10549  };
10550 
10551  };
10552  } CRC_tag;
10553 
10554 
10555 #define CRC (*(volatile CRC_tag *) 0xFFE68000UL)
10556 
10557 
10558 
10559 /****************************************************************/
10560 /* */
10561 /* Module: FCCU */
10562 /* */
10563 /****************************************************************/
10564 
10565  typedef union { /* FCCU Control Register */
10566  vuint32_t R;
10567  struct {
10568  vuint32_t:23;
10569  vuint32_t NVML:1; /* NVM configuration loaded */
10570  vuint32_t OPS:2; /* Operation status */
10571  vuint32_t:1;
10572  vuint32_t OPR:5; /* Operation run */
10573  } B;
10574  } FCCU_CTRL_32B_tag;
10575 
10576  typedef union { /* FCCU CTRL Key Register */
10577  vuint32_t R;
10578  } FCCU_CTRLK_32B_tag;
10579 
10580  typedef union { /* FCCU Configuration Register */
10581  vuint32_t R;
10582  struct {
10583  vuint32_t:10;
10584  vuint32_t RCCE1:1; /* RCC1 enable */
10585  vuint32_t RCCE0:1; /* RCC0 enable */
10586  vuint32_t SMRT:4; /* Safe Mode Request Timer */
10587  vuint32_t:4;
10588  vuint32_t CM:1; /* Config mode */
10589  vuint32_t SM:1; /* Switching mode */
10590  vuint32_t PS:1; /* Polarity Selection */
10591  vuint32_t FOM:3; /* Fault Output Mode Selection */
10592  vuint32_t FOP:6; /* Fault Output Prescaler */
10593  } B;
10594  } FCCU_CFG_32B_tag;
10595 
10596  typedef union { /* FCCU CF Configuration Register 0 */
10597  vuint32_t R;
10598  struct {
10599  vuint32_t CFC31:1; /* CF 31 configuration */
10600  vuint32_t CFC30:1; /* CF 30 configuration */
10601  vuint32_t CFC29:1; /* CF 29 configuration */
10602  vuint32_t CFC28:1; /* CF 28 configuration */
10603  vuint32_t CFC27:1; /* CF 27 configuration */
10604  vuint32_t CFC26:1; /* CF 26 configuration */
10605  vuint32_t CFC25:1; /* CF 25 configuration */
10606  vuint32_t CFC24:1; /* CF 24 configuration */
10607  vuint32_t CFC23:1; /* CF 23 configuration */
10608  vuint32_t CFC22:1; /* CF 22 configuration */
10609  vuint32_t CFC21:1; /* CF 21 configuration */
10610  vuint32_t CFC20:1; /* CF 20 configuration */
10611  vuint32_t CFC19:1; /* CF 19 configuration */
10612  vuint32_t CFC18:1; /* CF 18 configuration */
10613  vuint32_t CFC17:1; /* CF 17 configuration */
10614  vuint32_t CFC16:1; /* CF 16 configuration */
10615  vuint32_t CFC15:1; /* CF 15 configuration */
10616  vuint32_t CFC14:1; /* CF 14 configuration */
10617  vuint32_t CFC13:1; /* CF 13 configuration */
10618  vuint32_t CFC12:1; /* CF 12 configuration */
10619  vuint32_t CFC11:1; /* CF 11 configuration */
10620  vuint32_t CFC10:1; /* CF 10 configuration */
10621  vuint32_t CFC9:1; /* CF 9 configuration */
10622  vuint32_t CFC8:1; /* CF 8 configuration */
10623  vuint32_t CFC7:1; /* CF 7 configuration */
10624  vuint32_t CFC6:1; /* CF 6 configuration */
10625  vuint32_t CFC5:1; /* CF 5 configuration */
10626  vuint32_t CFC4:1; /* CF 4 configuration */
10627  vuint32_t CFC3:1; /* CF 3 configuration */
10628  vuint32_t CFC2:1; /* CF 2 configuration */
10629  vuint32_t CFC1:1; /* CF 1 configuration */
10630  vuint32_t CFC0:1; /* CF 0 configuration */
10631  } B;
10632  } FCCU_CF_CFG0_32B_tag;
10633 
10634  typedef union { /* FCCU CF Configuration Register 1 */
10635  vuint32_t R;
10636  struct {
10637  vuint32_t CFC63:1; /* CF 63 configuration */
10638  vuint32_t CFC62:1; /* CF 62 configuration */
10639  vuint32_t CFC61:1; /* CF 61 configuration */
10640  vuint32_t CFC60:1; /* CF 60 configuration */
10641  vuint32_t CFC59:1; /* CF 59 configuration */
10642  vuint32_t CFC58:1; /* CF 58 configuration */
10643  vuint32_t CFC57:1; /* CF 57 configuration */
10644  vuint32_t CFC56:1; /* CF 56 configuration */
10645  vuint32_t CFC55:1; /* CF 55 configuration */
10646  vuint32_t CFC54:1; /* CF 54 configuration */
10647  vuint32_t CFC53:1; /* CF 53 configuration */
10648  vuint32_t CFC52:1; /* CF 52 configuration */
10649  vuint32_t CFC51:1; /* CF 51 configuration */
10650  vuint32_t CFC50:1; /* CF 50 configuration */
10651  vuint32_t CFC49:1; /* CF 49 configuration */
10652  vuint32_t CFC48:1; /* CF 48 configuration */
10653  vuint32_t CFC47:1; /* CF 47 configuration */
10654  vuint32_t CFC46:1; /* CF 46 configuration */
10655  vuint32_t CFC45:1; /* CF 45 configuration */
10656  vuint32_t CFC44:1; /* CF 44 configuration */
10657  vuint32_t CFC43:1; /* CF 43 configuration */
10658  vuint32_t CFC42:1; /* CF 42 configuration */
10659  vuint32_t CFC41:1; /* CF 41 configuration */
10660  vuint32_t CFC40:1; /* CF 40 configuration */
10661  vuint32_t CFC39:1; /* CF 39 configuration */
10662  vuint32_t CFC38:1; /* CF 38 configuration */
10663  vuint32_t CFC37:1; /* CF 37 configuration */
10664  vuint32_t CFC36:1; /* CF 36 configuration */
10665  vuint32_t CFC35:1; /* CF 35 configuration */
10666  vuint32_t CFC34:1; /* CF 34 configuration */
10667  vuint32_t CFC33:1; /* CF 33 configuration */
10668  vuint32_t CFC32:1; /* CF 32 configuration */
10669  } B;
10670  } FCCU_CF_CFG1_32B_tag;
10671 
10672  typedef union { /* FCCU CF Configuration Register 2 */
10673  vuint32_t R;
10674  struct {
10675  vuint32_t CFC95:1; /* CF 95 configuration */
10676  vuint32_t CFC94:1; /* CF 94 configuration */
10677  vuint32_t CFC93:1; /* CF 93 configuration */
10678  vuint32_t CFC92:1; /* CF 92 configuration */
10679  vuint32_t CFC91:1; /* CF 91 configuration */
10680  vuint32_t CFC90:1; /* CF 90 configuration */
10681  vuint32_t CFC89:1; /* CF 89 configuration */
10682  vuint32_t CFC88:1; /* CF 88 configuration */
10683  vuint32_t CFC87:1; /* CF 87 configuration */
10684  vuint32_t CFC86:1; /* CF 86 configuration */
10685  vuint32_t CFC85:1; /* CF 85 configuration */
10686  vuint32_t CFC84:1; /* CF 84 configuration */
10687  vuint32_t CFC83:1; /* CF 83 configuration */
10688  vuint32_t CFC82:1; /* CF 82 configuration */
10689  vuint32_t CFC81:1; /* CF 81 configuration */
10690  vuint32_t CFC80:1; /* CF 80 configuration */
10691  vuint32_t CFC79:1; /* CF 79 configuration */
10692  vuint32_t CFC78:1; /* CF 78 configuration */
10693  vuint32_t CFC77:1; /* CF 77 configuration */
10694  vuint32_t CFC76:1; /* CF 76 configuration */
10695  vuint32_t CFC75:1; /* CF 75 configuration */
10696  vuint32_t CFC74:1; /* CF 74 configuration */
10697  vuint32_t CFC73:1; /* CF 73 configuration */
10698  vuint32_t CFC72:1; /* CF 72 configuration */
10699  vuint32_t CFC71:1; /* CF 71 configuration */
10700  vuint32_t CFC70:1; /* CF 70 configuration */
10701  vuint32_t CFC69:1; /* CF 69 configuration */
10702  vuint32_t CFC68:1; /* CF 68 configuration */
10703  vuint32_t CFC67:1; /* CF 67 configuration */
10704  vuint32_t CFC66:1; /* CF 66 configuration */
10705  vuint32_t CFC65:1; /* CF 65 configuration */
10706  vuint32_t CFC64:1; /* CF 64 configuration */
10707  } B;
10708  } FCCU_CF_CFG2_32B_tag;
10709 
10710  typedef union { /* FCCU CF Configuration Register 3 */
10711  vuint32_t R;
10712  struct {
10713  vuint32_t CFC127:1; /* CF 127 configuration */
10714  vuint32_t CFC126:1; /* CF 126 configuration */
10715  vuint32_t CFC125:1; /* CF 125 configuration */
10716  vuint32_t CFC124:1; /* CF 124 configuration */
10717  vuint32_t CFC123:1; /* CF 123 configuration */
10718  vuint32_t CFC122:1; /* CF 122 configuration */
10719  vuint32_t CFC121:1; /* CF 121 configuration */
10720  vuint32_t CFC120:1; /* CF 120 configuration */
10721  vuint32_t CFC119:1; /* CF 119 configuration */
10722  vuint32_t CFC118:1; /* CF 118 configuration */
10723  vuint32_t CFC117:1; /* CF 117 configuration */
10724  vuint32_t CFC116:1; /* CF 116 configuration */
10725  vuint32_t CFC115:1; /* CF 115 configuration */
10726  vuint32_t CFC114:1; /* CF 114 configuration */
10727  vuint32_t CFC113:1; /* CF 113 configuration */
10728  vuint32_t CFC112:1; /* CF 112 configuration */
10729  vuint32_t CFC111:1; /* CF 111 configuration */
10730  vuint32_t CFC110:1; /* CF 110 configuration */
10731  vuint32_t CFC109:1; /* CF 109 configuration */
10732  vuint32_t CFC108:1; /* CF 108 configuration */
10733  vuint32_t CFC107:1; /* CF 107 configuration */
10734  vuint32_t CFC106:1; /* CF 106 configuration */
10735  vuint32_t CFC105:1; /* CF 105 configuration */
10736  vuint32_t CFC104:1; /* CF 104 configuration */
10737  vuint32_t CFC103:1; /* CF 103 configuration */
10738  vuint32_t CFC102:1; /* CF 102 configuration */
10739  vuint32_t CFC101:1; /* CF 101 configuration */
10740  vuint32_t CFC100:1; /* CF 100 configuration */
10741  vuint32_t CFC99:1; /* CF 99 configuration */
10742  vuint32_t CFC98:1; /* CF 98 configuration */
10743  vuint32_t CFC97:1; /* CF 97 configuration */
10744  vuint32_t CFC96:1; /* CF 96 configuration */
10745  } B;
10746  } FCCU_CF_CFG3_32B_tag;
10747 
10748  typedef union { /* FCCU NCF Configuration Register 0 */
10749  vuint32_t R;
10750  struct {
10751  vuint32_t NCFC31:1; /* NCF 31 configuration */
10752  vuint32_t NCFC30:1; /* NCF 30 configuration */
10753  vuint32_t NCFC29:1; /* NCF 29 configuration */
10754  vuint32_t NCFC28:1; /* NCF 28 configuration */
10755  vuint32_t NCFC27:1; /* NCF 27 configuration */
10756  vuint32_t NCFC26:1; /* NCF 26 configuration */
10757  vuint32_t NCFC25:1; /* NCF 25 configuration */
10758  vuint32_t NCFC24:1; /* NCF 24 configuration */
10759  vuint32_t NCFC23:1; /* NCF 23 configuration */
10760  vuint32_t NCFC22:1; /* NCF 22 configuration */
10761  vuint32_t NCFC21:1; /* NCF 21 configuration */
10762  vuint32_t NCFC20:1; /* NCF 20 configuration */
10763  vuint32_t NCFC19:1; /* NCF 19 configuration */
10764  vuint32_t NCFC18:1; /* NCF 18 configuration */
10765  vuint32_t NCFC17:1; /* NCF 17 configuration */
10766  vuint32_t NCFC16:1; /* NCF 16 configuration */
10767  vuint32_t NCFC15:1; /* NCF 15 configuration */
10768  vuint32_t NCFC14:1; /* NCF 14 configuration */
10769  vuint32_t NCFC13:1; /* NCF 13 configuration */
10770  vuint32_t NCFC12:1; /* NCF 12 configuration */
10771  vuint32_t NCFC11:1; /* NCF 11 configuration */
10772  vuint32_t NCFC10:1; /* NCF 10 configuration */
10773  vuint32_t NCFC9:1; /* NCF 9 configuration */
10774  vuint32_t NCFC8:1; /* NCF 8 configuration */
10775  vuint32_t NCFC7:1; /* NCF 7 configuration */
10776  vuint32_t NCFC6:1; /* NCF 6 configuration */
10777  vuint32_t NCFC5:1; /* NCF 5 configuration */
10778  vuint32_t NCFC4:1; /* NCF 4 configuration */
10779  vuint32_t NCFC3:1; /* NCF 3 configuration */
10780  vuint32_t NCFC2:1; /* NCF 2 configuration */
10781  vuint32_t NCFC1:1; /* NCF 1 configuration */
10782  vuint32_t NCFC0:1; /* NCF 0 configuration */
10783  } B;
10784  } FCCU_NCF_CFG0_32B_tag;
10785 
10786  typedef union { /* FCCU NCF Configuration Register 1 */
10787  vuint32_t R;
10788  struct {
10789  vuint32_t NCFC63:1; /* NCF 63 configuration */
10790  vuint32_t NCFC62:1; /* NCF 62 configuration */
10791  vuint32_t NCFC61:1; /* NCF 61 configuration */
10792  vuint32_t NCFC60:1; /* NCF 60 configuration */
10793  vuint32_t NCFC59:1; /* NCF 59 configuration */
10794  vuint32_t NCFC58:1; /* NCF 58 configuration */
10795  vuint32_t NCFC57:1; /* NCF 57 configuration */
10796  vuint32_t NCFC56:1; /* NCF 56 configuration */
10797  vuint32_t NCFC55:1; /* NCF 55 configuration */
10798  vuint32_t NCFC54:1; /* NCF 54 configuration */
10799  vuint32_t NCFC53:1; /* NCF 53 configuration */
10800  vuint32_t NCFC52:1; /* NCF 52 configuration */
10801  vuint32_t NCFC51:1; /* NCF 51 configuration */
10802  vuint32_t NCFC50:1; /* NCF 50 configuration */
10803  vuint32_t NCFC49:1; /* NCF 49 configuration */
10804  vuint32_t NCFC48:1; /* NCF 48 configuration */
10805  vuint32_t NCFC47:1; /* NCF 47 configuration */
10806  vuint32_t NCFC46:1; /* NCF 46 configuration */
10807  vuint32_t NCFC45:1; /* NCF 45 configuration */
10808  vuint32_t NCFC44:1; /* NCF 44 configuration */
10809  vuint32_t NCFC43:1; /* NCF 43 configuration */
10810  vuint32_t NCFC42:1; /* NCF 42 configuration */
10811  vuint32_t NCFC41:1; /* NCF 41 configuration */
10812  vuint32_t NCFC40:1; /* NCF 40 configuration */
10813  vuint32_t NCFC39:1; /* NCF 39 configuration */
10814  vuint32_t NCFC38:1; /* NCF 38 configuration */
10815  vuint32_t NCFC37:1; /* NCF 37 configuration */
10816  vuint32_t NCFC36:1; /* NCF 36 configuration */
10817  vuint32_t NCFC35:1; /* NCF 35 configuration */
10818  vuint32_t NCFC34:1; /* NCF 34 configuration */
10819  vuint32_t NCFC33:1; /* NCF 33 configuration */
10820  vuint32_t NCFC32:1; /* NCF 32 configuration */
10821  } B;
10822  } FCCU_NCF_CFG1_32B_tag;
10823 
10824  typedef union { /* FCCU NCF Configuration Register 2 */
10825  vuint32_t R;
10826  struct {
10827  vuint32_t NCFC95:1; /* NCF 95 configuration */
10828  vuint32_t NCFC94:1; /* NCF 94 configuration */
10829  vuint32_t NCFC93:1; /* NCF 93 configuration */
10830  vuint32_t NCFC92:1; /* NCF 92 configuration */
10831  vuint32_t NCFC91:1; /* NCF 91 configuration */
10832  vuint32_t NCFC90:1; /* NCF 90 configuration */
10833  vuint32_t NCFC89:1; /* NCF 89 configuration */
10834  vuint32_t NCFC88:1; /* NCF 88 configuration */
10835  vuint32_t NCFC87:1; /* NCF 87 configuration */
10836  vuint32_t NCFC86:1; /* NCF 86 configuration */
10837  vuint32_t NCFC85:1; /* NCF 85 configuration */
10838  vuint32_t NCFC84:1; /* NCF 84 configuration */
10839  vuint32_t NCFC83:1; /* NCF 83 configuration */
10840  vuint32_t NCFC82:1; /* NCF 82 configuration */
10841  vuint32_t NCFC81:1; /* NCF 81 configuration */
10842  vuint32_t NCFC80:1; /* NCF 80 configuration */
10843  vuint32_t NCFC79:1; /* NCF 79 configuration */
10844  vuint32_t NCFC78:1; /* NCF 78 configuration */
10845  vuint32_t NCFC77:1; /* NCF 77 configuration */
10846  vuint32_t NCFC76:1; /* NCF 76 configuration */
10847  vuint32_t NCFC75:1; /* NCF 75 configuration */
10848  vuint32_t NCFC74:1; /* NCF 74 configuration */
10849  vuint32_t NCFC73:1; /* NCF 73 configuration */
10850  vuint32_t NCFC72:1; /* NCF 72 configuration */
10851  vuint32_t NCFC71:1; /* NCF 71 configuration */
10852  vuint32_t NCFC70:1; /* NCF 70 configuration */
10853  vuint32_t NCFC69:1; /* NCF 69 configuration */
10854  vuint32_t NCFC68:1; /* NCF 68 configuration */
10855  vuint32_t NCFC67:1; /* NCF 67 configuration */
10856  vuint32_t NCFC66:1; /* NCF 66 configuration */
10857  vuint32_t NCFC65:1; /* NCF 65 configuration */
10858  vuint32_t NCFC64:1; /* NCF 64 configuration */
10859  } B;
10860  } FCCU_NCF_CFG2_32B_tag;
10861 
10862  typedef union { /* FCCU NCF Configuration Register 3 */
10863  vuint32_t R;
10864  struct {
10865  vuint32_t NCFC127:1; /* NCF 127 configuration */
10866  vuint32_t NCFC126:1; /* NCF 126 configuration */
10867  vuint32_t NCFC125:1; /* NCF 125 configuration */
10868  vuint32_t NCFC124:1; /* NCF 124 configuration */
10869  vuint32_t NCFC123:1; /* NCF 123 configuration */
10870  vuint32_t NCFC122:1; /* NCF 122 configuration */
10871  vuint32_t NCFC121:1; /* NCF 121 configuration */
10872  vuint32_t NCFC120:1; /* NCF 120 configuration */
10873  vuint32_t NCFC119:1; /* NCF 119 configuration */
10874  vuint32_t NCFC118:1; /* NCF 118 configuration */
10875  vuint32_t NCFC117:1; /* NCF 117 configuration */
10876  vuint32_t NCFC116:1; /* NCF 116 configuration */
10877  vuint32_t NCFC115:1; /* NCF 115 configuration */
10878  vuint32_t NCFC114:1; /* NCF 114 configuration */
10879  vuint32_t NCFC113:1; /* NCF 113 configuration */
10880  vuint32_t NCFC112:1; /* NCF 112 configuration */
10881  vuint32_t NCFC111:1; /* NCF 111 configuration */
10882  vuint32_t NCFC110:1; /* NCF 110 configuration */
10883  vuint32_t NCFC109:1; /* NCF 109 configuration */
10884  vuint32_t NCFC108:1; /* NCF 108 configuration */
10885  vuint32_t NCFC107:1; /* NCF 107 configuration */
10886  vuint32_t NCFC106:1; /* NCF 106 configuration */
10887  vuint32_t NCFC105:1; /* NCF 105 configuration */
10888  vuint32_t NCFC104:1; /* NCF 104 configuration */
10889  vuint32_t NCFC103:1; /* NCF 103 configuration */
10890  vuint32_t NCFC102:1; /* NCF 102 configuration */
10891  vuint32_t NCFC101:1; /* NCF 101 configuration */
10892  vuint32_t NCFC100:1; /* NCF 100 configuration */
10893  vuint32_t NCFC99:1; /* NCF 99 configuration */
10894  vuint32_t NCFC98:1; /* NCF 98 configuration */
10895  vuint32_t NCFC97:1; /* NCF 97 configuration */
10896  vuint32_t NCFC96:1; /* NCF 96 configuration */
10897  } B;
10898  } FCCU_NCF_CFG3_32B_tag;
10899 
10900  typedef union { /* FCCU CFS Configuration Register 0 */
10901  vuint32_t R;
10902  struct {
10903  vuint32_t CFSC15:2; /* CF 15 state configuration */
10904  vuint32_t CFSC14:2; /* CF 14 state configuration */
10905  vuint32_t CFSC13:2; /* CF 13 state configuration */
10906  vuint32_t CFSC12:2; /* CF 12 state configuration */
10907  vuint32_t CFSC11:2; /* CF 11 state configuration */
10908  vuint32_t CFSC10:2; /* CF 10 state configuration */
10909  vuint32_t CFSC9:2; /* CF 9 state configuration */
10910  vuint32_t CFSC8:2; /* CF 8 state configuration */
10911  vuint32_t CFSC7:2; /* CF 7 state configuration */
10912  vuint32_t CFSC6:2; /* CF 6 state configuration */
10913  vuint32_t CFSC5:2; /* CF 5 state configuration */
10914  vuint32_t CFSC4:2; /* CF 4 state configuration */
10915  vuint32_t CFSC3:2; /* CF 3 state configuration */
10916  vuint32_t CFSC2:2; /* CF 2 state configuration */
10917  vuint32_t CFSC1:2; /* CF 1 state configuration */
10918  vuint32_t CFSC0:2; /* CF 0 state configuration */
10919  } B;
10920  } FCCU_CFS_CFG0_32B_tag;
10921 
10922  typedef union { /* FCCU CFS Configuration Register 1 */
10923  vuint32_t R;
10924  struct {
10925  vuint32_t CFSC31:2; /* CF 31 state configuration */
10926  vuint32_t CFSC30:2; /* CF 30 state configuration */
10927  vuint32_t CFSC29:2; /* CF 29 state configuration */
10928  vuint32_t CFSC28:2; /* CF 28 state configuration */
10929  vuint32_t CFSC27:2; /* CF 27 state configuration */
10930  vuint32_t CFSC26:2; /* CF 26 state configuration */
10931  vuint32_t CFSC25:2; /* CF 25 state configuration */
10932  vuint32_t CFSC24:2; /* CF 24 state configuration */
10933  vuint32_t CFSC23:2; /* CF 23 state configuration */
10934  vuint32_t CFSC22:2; /* CF 22 state configuration */
10935  vuint32_t CFSC21:2; /* CF 21 state configuration */
10936  vuint32_t CFSC20:2; /* CF 20 state configuration */
10937  vuint32_t CFSC19:2; /* CF 19 state configuration */
10938  vuint32_t CFSC18:2; /* CF 18 state configuration */
10939  vuint32_t CFSC17:2; /* CF 17 state configuration */
10940  vuint32_t CFSC16:2; /* CF 16 state configuration */
10941  } B;
10942  } FCCU_CFS_CFG1_32B_tag;
10943 
10944  typedef union { /* FCCU CFS Configuration Register 2 */
10945  vuint32_t R;
10946  struct {
10947  vuint32_t CFSC47:2; /* CF 47 state configuration */
10948  vuint32_t CFSC46:2; /* CF 46 state configuration */
10949  vuint32_t CFSC45:2; /* CF 45 state configuration */
10950  vuint32_t CFSC44:2; /* CF 44 state configuration */
10951  vuint32_t CFSC43:2; /* CF 43 state configuration */
10952  vuint32_t CFSC42:2; /* CF 42 state configuration */
10953  vuint32_t CFSC41:2; /* CF 41 state configuration */
10954  vuint32_t CFSC40:2; /* CF 40 state configuration */
10955  vuint32_t CFSC39:2; /* CF 39 state configuration */
10956  vuint32_t CFSC38:2; /* CF 38 state configuration */
10957  vuint32_t CFSC37:2; /* CF 37 state configuration */
10958  vuint32_t CFSC36:2; /* CF 36 state configuration */
10959  vuint32_t CFSC35:2; /* CF 35 state configuration */
10960  vuint32_t CFSC34:2; /* CF 34 state configuration */
10961  vuint32_t CFSC33:2; /* CF 33 state configuration */
10962  vuint32_t CFSC32:2; /* CF 32 state configuration */
10963  } B;
10964  } FCCU_CFS_CFG2_32B_tag;
10965 
10966  typedef union { /* FCCU CFS Configuration Register 3 */
10967  vuint32_t R;
10968  struct {
10969  vuint32_t CFSC63:2; /* CF 63 state configuration */
10970  vuint32_t CFSC62:2; /* CF 62 state configuration */
10971  vuint32_t CFSC61:2; /* CF 61 state configuration */
10972  vuint32_t CFSC60:2; /* CF 60 state configuration */
10973  vuint32_t CFSC59:2; /* CF 59 state configuration */
10974  vuint32_t CFSC58:2; /* CF 58 state configuration */
10975  vuint32_t CFSC57:2; /* CF 57 state configuration */
10976  vuint32_t CFSC56:2; /* CF 56 state configuration */
10977  vuint32_t CFSC55:2; /* CF 55 state configuration */
10978  vuint32_t CFSC54:2; /* CF 54 state configuration */
10979  vuint32_t CFSC53:2; /* CF 53 state configuration */
10980  vuint32_t CFSC52:2; /* CF 52 state configuration */
10981  vuint32_t CFSC51:2; /* CF 51 state configuration */
10982  vuint32_t CFSC50:2; /* CF 50 state configuration */
10983  vuint32_t CFSC49:2; /* CF 49 state configuration */
10984  vuint32_t CFSC48:2; /* CF 48 state configuration */
10985  } B;
10986  } FCCU_CFS_CFG3_32B_tag;
10987 
10988  typedef union { /* FCCU CFS Configuration Register 4 */
10989  vuint32_t R;
10990  struct {
10991  vuint32_t CFSC79:2; /* CF 79 state configuration */
10992  vuint32_t CFSC78:2; /* CF 78 state configuration */
10993  vuint32_t CFSC77:2; /* CF 77 state configuration */
10994  vuint32_t CFSC76:2; /* CF 76 state configuration */
10995  vuint32_t CFSC75:2; /* CF 75 state configuration */
10996  vuint32_t CFSC74:2; /* CF 74 state configuration */
10997  vuint32_t CFSC73:2; /* CF 73 state configuration */
10998  vuint32_t CFSC72:2; /* CF 72 state configuration */
10999  vuint32_t CFSC71:2; /* CF 71 state configuration */
11000  vuint32_t CFSC70:2; /* CF 70 state configuration */
11001  vuint32_t CFSC69:2; /* CF 69 state configuration */
11002  vuint32_t CFSC68:2; /* CF 68 state configuration */
11003  vuint32_t CFSC67:2; /* CF 67 state configuration */
11004  vuint32_t CFSC66:2; /* CF 66 state configuration */
11005  vuint32_t CFSC65:2; /* CF 65 state configuration */
11006  vuint32_t CFSC64:2; /* CF 64 state configuration */
11007  } B;
11008  } FCCU_CFS_CFG4_32B_tag;
11009 
11010  typedef union { /* FCCU CFS Configuration Register 5 */
11011  vuint32_t R;
11012  struct {
11013  vuint32_t CFSC95:2; /* CF 95 state configuration */
11014  vuint32_t CFSC94:2; /* CF 94 state configuration */
11015  vuint32_t CFSC93:2; /* CF 93 state configuration */
11016  vuint32_t CFSC92:2; /* CF 92 state configuration */
11017  vuint32_t CFSC91:2; /* CF 91 state configuration */
11018  vuint32_t CFSC90:2; /* CF 90 state configuration */
11019  vuint32_t CFSC89:2; /* CF 89 state configuration */
11020  vuint32_t CFSC88:2; /* CF 88 state configuration */
11021  vuint32_t CFSC87:2; /* CF 87 state configuration */
11022  vuint32_t CFSC86:2; /* CF 86 state configuration */
11023  vuint32_t CFSC85:2; /* CF 85 state configuration */
11024  vuint32_t CFSC84:2; /* CF 84 state configuration */
11025  vuint32_t CFSC83:2; /* CF 83 state configuration */
11026  vuint32_t CFSC82:2; /* CF 82 state configuration */
11027  vuint32_t CFSC81:2; /* CF 81 state configuration */
11028  vuint32_t CFSC80:2; /* CF 80 state configuration */
11029  } B;
11030  } FCCU_CFS_CFG5_32B_tag;
11031 
11032  typedef union { /* FCCU CFS Configuration Register 6 */
11033  vuint32_t R;
11034  struct {
11035  vuint32_t CFSC111:2; /* CF 111 state configuration */
11036  vuint32_t CFSC110:2; /* CF 110 state configuration */
11037  vuint32_t CFSC109:2; /* CF 109 state configuration */
11038  vuint32_t CFSC108:2; /* CF 108 state configuration */
11039  vuint32_t CFSC107:2; /* CF 107 state configuration */
11040  vuint32_t CFSC106:2; /* CF 106 state configuration */
11041  vuint32_t CFSC105:2; /* CF 105 state configuration */
11042  vuint32_t CFSC104:2; /* CF 104 state configuration */
11043  vuint32_t CFSC103:2; /* CF 103 state configuration */
11044  vuint32_t CFSC102:2; /* CF 102 state configuration */
11045  vuint32_t CFSC101:2; /* CF 101 state configuration */
11046  vuint32_t CFSC100:2; /* CF 100 state configuration */
11047  vuint32_t CFSC99:2; /* CF 99 state configuration */
11048  vuint32_t CFSC98:2; /* CF 98 state configuration */
11049  vuint32_t CFSC97:2; /* CF 97 state configuration */
11050  vuint32_t CFSC96:2; /* CF 96 state configuration */
11051  } B;
11052  } FCCU_CFS_CFG6_32B_tag;
11053 
11054  typedef union { /* FCCU CFS Configuration Register 7 */
11055  vuint32_t R;
11056  struct {
11057  vuint32_t CFSC127:2; /* CF 127 state configuration */
11058  vuint32_t CFSC126:2; /* CF 126 state configuration */
11059  vuint32_t CFSC125:2; /* CF 125 state configuration */
11060  vuint32_t CFSC124:2; /* CF 124 state configuration */
11061  vuint32_t CFSC123:2; /* CF 123 state configuration */
11062  vuint32_t CFSC122:2; /* CF 122 state configuration */
11063  vuint32_t CFSC121:2; /* CF 121 state configuration */
11064  vuint32_t CFSC120:2; /* CF 120 state configuration */
11065  vuint32_t CFSC119:2; /* CF 119 state configuration */
11066  vuint32_t CFSC118:2; /* CF 118 state configuration */
11067  vuint32_t CFSC117:2; /* CF 117 state configuration */
11068  vuint32_t CFSC116:2; /* CF 116 state configuration */
11069  vuint32_t CFSC115:2; /* CF 115 state configuration */
11070  vuint32_t CFSC114:2; /* CF 114 state configuration */
11071  vuint32_t CFSC113:2; /* CF 113 state configuration */
11072  vuint32_t CFSC112:2; /* CF 112 state configuration */
11073  } B;
11074  } FCCU_CFS_CFG7_32B_tag;
11075 
11076  typedef union { /* FCCU NCFS Configuration Register 0 */
11077  vuint32_t R;
11078  struct {
11079  vuint32_t NCFSC15:2; /* NCF 15 state configuration */
11080  vuint32_t NCFSC14:2; /* NCF 14 state configuration */
11081  vuint32_t NCFSC13:2; /* NCF 13 state configuration */
11082  vuint32_t NCFSC12:2; /* NCF 12 state configuration */
11083  vuint32_t NCFSC11:2; /* NCF 11 state configuration */
11084  vuint32_t NCFSC10:2; /* NCF 10 state configuration */
11085  vuint32_t NCFSC9:2; /* NCF 9 state configuration */
11086  vuint32_t NCFSC8:2; /* NCF 8 state configuration */
11087  vuint32_t NCFSC7:2; /* NCF 7 state configuration */
11088  vuint32_t NCFSC6:2; /* NCF 6 state configuration */
11089  vuint32_t NCFSC5:2; /* NCF 5 state configuration */
11090  vuint32_t NCFSC4:2; /* NCF 4 state configuration */
11091  vuint32_t NCFSC3:2; /* NCF 3 state configuration */
11092  vuint32_t NCFSC2:2; /* NCF 2 state configuration */
11093  vuint32_t NCFSC1:2; /* NCF 1 state configuration */
11094  vuint32_t NCFSC0:2; /* NCF 0 state configuration */
11095  } B;
11096  } FCCU_NCFS_CFG0_32B_tag;
11097 
11098  typedef union { /* FCCU NCFS Configuration Register 1 */
11099  vuint32_t R;
11100  struct {
11101  vuint32_t NCFSC31:2; /* NCF 31 state configuration */
11102  vuint32_t NCFSC30:2; /* NCF 30 state configuration */
11103  vuint32_t NCFSC29:2; /* NCF 29 state configuration */
11104  vuint32_t NCFSC28:2; /* NCF 28 state configuration */
11105  vuint32_t NCFSC27:2; /* NCF 27 state configuration */
11106  vuint32_t NCFSC26:2; /* NCF 26 state configuration */
11107  vuint32_t NCFSC25:2; /* NCF 25 state configuration */
11108  vuint32_t NCFSC24:2; /* NCF 24 state configuration */
11109  vuint32_t NCFSC23:2; /* NCF 23 state configuration */
11110  vuint32_t NCFSC22:2; /* NCF 22 state configuration */
11111  vuint32_t NCFSC21:2; /* NCF 21 state configuration */
11112  vuint32_t NCFSC20:2; /* NCF 20 state configuration */
11113  vuint32_t NCFSC19:2; /* NCF 19 state configuration */
11114  vuint32_t NCFSC18:2; /* NCF 18 state configuration */
11115  vuint32_t NCFSC17:2; /* NCF 17 state configuration */
11116  vuint32_t NCFSC16:2; /* NCF 16 state configuration */
11117  } B;
11118  } FCCU_NCFS_CFG1_32B_tag;
11119 
11120  typedef union { /* FCCU NCFS Configuration Register 2 */
11121  vuint32_t R;
11122  struct {
11123  vuint32_t NCFSC47:2; /* NCF 47 state configuration */
11124  vuint32_t NCFSC46:2; /* NCF 46 state configuration */
11125  vuint32_t NCFSC45:2; /* NCF 45 state configuration */
11126  vuint32_t NCFSC44:2; /* NCF 44 state configuration */
11127  vuint32_t NCFSC43:2; /* NCF 43 state configuration */
11128  vuint32_t NCFSC42:2; /* NCF 42 state configuration */
11129  vuint32_t NCFSC41:2; /* NCF 41 state configuration */
11130  vuint32_t NCFSC40:2; /* NCF 40 state configuration */
11131  vuint32_t NCFSC39:2; /* NCF 39 state configuration */
11132  vuint32_t NCFSC38:2; /* NCF 38 state configuration */
11133  vuint32_t NCFSC37:2; /* NCF 37 state configuration */
11134  vuint32_t NCFSC36:2; /* NCF 36 state configuration */
11135  vuint32_t NCFSC35:2; /* NCF 35 state configuration */
11136  vuint32_t NCFSC34:2; /* NCF 34 state configuration */
11137  vuint32_t NCFSC33:2; /* NCF 33 state configuration */
11138  vuint32_t NCFSC32:2; /* NCF 32 state configuration */
11139  } B;
11140  } FCCU_NCFS_CFG2_32B_tag;
11141 
11142  typedef union { /* FCCU NCFS Configuration Register 3 */
11143  vuint32_t R;
11144  struct {
11145  vuint32_t NCFSC63:2; /* NCF 63 state configuration */
11146  vuint32_t NCFSC62:2; /* NCF 62 state configuration */
11147  vuint32_t NCFSC61:2; /* NCF 61 state configuration */
11148  vuint32_t NCFSC60:2; /* NCF 60 state configuration */
11149  vuint32_t NCFSC59:2; /* NCF 59 state configuration */
11150  vuint32_t NCFSC58:2; /* NCF 58 state configuration */
11151  vuint32_t NCFSC57:2; /* NCF 57 state configuration */
11152  vuint32_t NCFSC56:2; /* NCF 56 state configuration */
11153  vuint32_t NCFSC55:2; /* NCF 55 state configuration */
11154  vuint32_t NCFSC54:2; /* NCF 54 state configuration */
11155  vuint32_t NCFSC53:2; /* NCF 53 state configuration */
11156  vuint32_t NCFSC52:2; /* NCF 52 state configuration */
11157  vuint32_t NCFSC51:2; /* NCF 51 state configuration */
11158  vuint32_t NCFSC50:2; /* NCF 50 state configuration */
11159  vuint32_t NCFSC49:2; /* NCF 49 state configuration */
11160  vuint32_t NCFSC48:2; /* NCF 48 state configuration */
11161  } B;
11162  } FCCU_NCFS_CFG3_32B_tag;
11163 
11164  typedef union { /* FCCU NCFS Configuration Register 4 */
11165  vuint32_t R;
11166  struct {
11167  vuint32_t NCFSC79:2; /* NCF 79 state configuration */
11168  vuint32_t NCFSC78:2; /* NCF 78 state configuration */
11169  vuint32_t NCFSC77:2; /* NCF 77 state configuration */
11170  vuint32_t NCFSC76:2; /* NCF 76 state configuration */
11171  vuint32_t NCFSC75:2; /* NCF 75 state configuration */
11172  vuint32_t NCFSC74:2; /* NCF 74 state configuration */
11173  vuint32_t NCFSC73:2; /* NCF 73 state configuration */
11174  vuint32_t NCFSC72:2; /* NCF 72 state configuration */
11175  vuint32_t NCFSC71:2; /* NCF 71 state configuration */
11176  vuint32_t NCFSC70:2; /* NCF 70 state configuration */
11177  vuint32_t NCFSC69:2; /* NCF 69 state configuration */
11178  vuint32_t NCFSC68:2; /* NCF 68 state configuration */
11179  vuint32_t NCFSC67:2; /* NCF 67 state configuration */
11180  vuint32_t NCFSC66:2; /* NCF 66 state configuration */
11181  vuint32_t NCFSC65:2; /* NCF 65 state configuration */
11182  vuint32_t NCFSC64:2; /* NCF 64 state configuration */
11183  } B;
11184  } FCCU_NCFS_CFG4_32B_tag;
11185 
11186  typedef union { /* FCCU NCFS Configuration Register 5 */
11187  vuint32_t R;
11188  struct {
11189  vuint32_t NCFSC95:2; /* NCF 95 state configuration */
11190  vuint32_t NCFSC94:2; /* NCF 94 state configuration */
11191  vuint32_t NCFSC93:2; /* NCF 93 state configuration */
11192  vuint32_t NCFSC92:2; /* NCF 92 state configuration */
11193  vuint32_t NCFSC91:2; /* NCF 91 state configuration */
11194  vuint32_t NCFSC90:2; /* NCF 90 state configuration */
11195  vuint32_t NCFSC89:2; /* NCF 89 state configuration */
11196  vuint32_t NCFSC88:2; /* NCF 88 state configuration */
11197  vuint32_t NCFSC87:2; /* NCF 87 state configuration */
11198  vuint32_t NCFSC86:2; /* NCF 86 state configuration */
11199  vuint32_t NCFSC85:2; /* NCF 85 state configuration */
11200  vuint32_t NCFSC84:2; /* NCF 84 state configuration */
11201  vuint32_t NCFSC83:2; /* NCF 83 state configuration */
11202  vuint32_t NCFSC82:2; /* NCF 82 state configuration */
11203  vuint32_t NCFSC81:2; /* NCF 81 state configuration */
11204  vuint32_t NCFSC80:2; /* NCF 80 state configuration */
11205  } B;
11206  } FCCU_NCFS_CFG5_32B_tag;
11207 
11208  typedef union { /* FCCU NCFS Configuration Register 6 */
11209  vuint32_t R;
11210  struct {
11211  vuint32_t NCFSC111:2; /* NCF 111 state configuration */
11212  vuint32_t NCFSC110:2; /* NCF 110 state configuration */
11213  vuint32_t NCFSC109:2; /* NCF 109 state configuration */
11214  vuint32_t NCFSC108:2; /* NCF 108 state configuration */
11215  vuint32_t NCFSC107:2; /* NCF 107 state configuration */
11216  vuint32_t NCFSC106:2; /* NCF 106 state configuration */
11217  vuint32_t NCFSC105:2; /* NCF 105 state configuration */
11218  vuint32_t NCFSC104:2; /* NCF 104 state configuration */
11219  vuint32_t NCFSC103:2; /* NCF 103 state configuration */
11220  vuint32_t NCFSC102:2; /* NCF 102 state configuration */
11221  vuint32_t NCFSC101:2; /* NCF 101 state configuration */
11222  vuint32_t NCFSC100:2; /* NCF 100 state configuration */
11223  vuint32_t NCFSC99:2; /* NCF 99 state configuration */
11224  vuint32_t NCFSC98:2; /* NCF 98 state configuration */
11225  vuint32_t NCFSC97:2; /* NCF 97 state configuration */
11226  vuint32_t NCFSC96:2; /* NCF 96 state configuration */
11227  } B;
11228  } FCCU_NCFS_CFG6_32B_tag;
11229 
11230  typedef union { /* FCCU NCFS Configuration Register 7 */
11231  vuint32_t R;
11232  struct {
11233  vuint32_t NCFSC127:2; /* NCF 127 state configuration */
11234  vuint32_t NCFSC126:2; /* NCF 126 state configuration */
11235  vuint32_t NCFSC125:2; /* NCF 125 state configuration */
11236  vuint32_t NCFSC124:2; /* NCF 124 state configuration */
11237  vuint32_t NCFSC123:2; /* NCF 123 state configuration */
11238  vuint32_t NCFSC122:2; /* NCF 122 state configuration */
11239  vuint32_t NCFSC121:2; /* NCF 121 state configuration */
11240  vuint32_t NCFSC120:2; /* NCF 120 state configuration */
11241  vuint32_t NCFSC119:2; /* NCF 119 state configuration */
11242  vuint32_t NCFSC118:2; /* NCF 118 state configuration */
11243  vuint32_t NCFSC117:2; /* NCF 117 state configuration */
11244  vuint32_t NCFSC116:2; /* NCF 116 state configuration */
11245  vuint32_t NCFSC115:2; /* NCF 115 state configuration */
11246  vuint32_t NCFSC114:2; /* NCF 114 state configuration */
11247  vuint32_t NCFSC113:2; /* NCF 113 state configuration */
11248  vuint32_t NCFSC112:2; /* NCF 112 state configuration */
11249  } B;
11250  } FCCU_NCFS_CFG7_32B_tag;
11251 
11252  typedef union { /* FCCU CF Status Register 0 */
11253  vuint32_t R;
11254  struct {
11255  vuint32_t CFS31:1; /* CF 31 status */
11256  vuint32_t CFS30:1; /* CF 30 status */
11257  vuint32_t CFS29:1; /* CF 29 status */
11258  vuint32_t CFS28:1; /* CF 28 status */
11259  vuint32_t CFS27:1; /* CF 27 status */
11260  vuint32_t CFS26:1; /* CF 26 status */
11261  vuint32_t CFS25:1; /* CF 25 status */
11262  vuint32_t CFS24:1; /* CF 24 status */
11263  vuint32_t CFS23:1; /* CF 23 status */
11264  vuint32_t CFS22:1; /* CF 22 status */
11265  vuint32_t CFS21:1; /* CF 21 status */
11266  vuint32_t CFS20:1; /* CF 20 status */
11267  vuint32_t CFS19:1; /* CF 19 status */
11268  vuint32_t CFS18:1; /* CF 18 status */
11269  vuint32_t CFS17:1; /* CF 17 status */
11270  vuint32_t CFS16:1; /* CF 16 status */
11271  vuint32_t CFS15:1; /* CF 15 status */
11272  vuint32_t CFS14:1; /* CF 14 status */
11273  vuint32_t CFS13:1; /* CF 13 status */
11274  vuint32_t CFS12:1; /* CF 12 status */
11275  vuint32_t CFS11:1; /* CF 11 status */
11276  vuint32_t CFS10:1; /* CF 10 status */
11277  vuint32_t CFS9:1; /* CF 9 status */
11278  vuint32_t CFS8:1; /* CF 8 status */
11279  vuint32_t CFS7:1; /* CF 7 status */
11280  vuint32_t CFS6:1; /* CF 6 status */
11281  vuint32_t CFS5:1; /* CF 5 status */
11282  vuint32_t CFS4:1; /* CF 4 status */
11283  vuint32_t CFS3:1; /* CF 3 status */
11284  vuint32_t CFS2:1; /* CF 2 status */
11285  vuint32_t CFS1:1; /* CF 1 status */
11286  vuint32_t CFS0:1; /* CF 0 status */
11287  } B;
11288  } FCCU_CFS0_32B_tag;
11289 
11290  typedef union { /* FCCU CF Status Register 1 */
11291  vuint32_t R;
11292  struct {
11293  vuint32_t CFS63:1; /* CF 63 status */
11294  vuint32_t CFS62:1; /* CF 62 status */
11295  vuint32_t CFS61:1; /* CF 61 status */
11296  vuint32_t CFS60:1; /* CF 60 status */
11297  vuint32_t CFS59:1; /* CF 59 status */
11298  vuint32_t CFS58:1; /* CF 58 status */
11299  vuint32_t CFS57:1; /* CF 57 status */
11300  vuint32_t CFS56:1; /* CF 56 status */
11301  vuint32_t CFS55:1; /* CF 55 status */
11302  vuint32_t CFS54:1; /* CF 54 status */
11303  vuint32_t CFS53:1; /* CF 53 status */
11304  vuint32_t CFS52:1; /* CF 52 status */
11305  vuint32_t CFS51:1; /* CF 51 status */
11306  vuint32_t CFS50:1; /* CF 50 status */
11307  vuint32_t CFS49:1; /* CF 49 status */
11308  vuint32_t CFS48:1; /* CF 48 status */
11309  vuint32_t CFS47:1; /* CF 47 status */
11310  vuint32_t CFS46:1; /* CF 46 status */
11311  vuint32_t CFS45:1; /* CF 45 status */
11312  vuint32_t CFS44:1; /* CF 44 status */
11313  vuint32_t CFS43:1; /* CF 43 status */
11314  vuint32_t CFS42:1; /* CF 42 status */
11315  vuint32_t CFS41:1; /* CF 41 status */
11316  vuint32_t CFS40:1; /* CF 40 status */
11317  vuint32_t CFS39:1; /* CF 39 status */
11318  vuint32_t CFS38:1; /* CF 38 status */
11319  vuint32_t CFS37:1; /* CF 37 status */
11320  vuint32_t CFS36:1; /* CF 36 status */
11321  vuint32_t CFS35:1; /* CF 35 status */
11322  vuint32_t CFS34:1; /* CF 34 status */
11323  vuint32_t CFS33:1; /* CF 33 status */
11324  vuint32_t CFS32:1; /* CF 32 status */
11325  } B;
11326  } FCCU_CFS1_32B_tag;
11327 
11328  typedef union { /* FCCU CF Status Register 2 */
11329  vuint32_t R;
11330  struct {
11331  vuint32_t CFS95:1; /* CF 95 status */
11332  vuint32_t CFS94:1; /* CF 94 status */
11333  vuint32_t CFS93:1; /* CF 93 status */
11334  vuint32_t CFS92:1; /* CF 92 status */
11335  vuint32_t CFS91:1; /* CF 91 status */
11336  vuint32_t CFS90:1; /* CF 90 status */
11337  vuint32_t CFS89:1; /* CF 89 status */
11338  vuint32_t CFS88:1; /* CF 88 status */
11339  vuint32_t CFS87:1; /* CF 87 status */
11340  vuint32_t CFS86:1; /* CF 86 status */
11341  vuint32_t CFS85:1; /* CF 85 status */
11342  vuint32_t CFS84:1; /* CF 84 status */
11343  vuint32_t CFS83:1; /* CF 83 status */
11344  vuint32_t CFS82:1; /* CF 82 status */
11345  vuint32_t CFS81:1; /* CF 81 status */
11346  vuint32_t CFS80:1; /* CF 80 status */
11347  vuint32_t CFS79:1; /* CF 79 status */
11348  vuint32_t CFS78:1; /* CF 78 status */
11349  vuint32_t CFS77:1; /* CF 77 status */
11350  vuint32_t CFS76:1; /* CF 76 status */
11351  vuint32_t CFS75:1; /* CF 75 status */
11352  vuint32_t CFS74:1; /* CF 74 status */
11353  vuint32_t CFS73:1; /* CF 73 status */
11354  vuint32_t CFS72:1; /* CF 72 status */
11355  vuint32_t CFS71:1; /* CF 71 status */
11356  vuint32_t CFS70:1; /* CF 70 status */
11357  vuint32_t CFS69:1; /* CF 69 status */
11358  vuint32_t CFS68:1; /* CF 68 status */
11359  vuint32_t CFS67:1; /* CF 67 status */
11360  vuint32_t CFS66:1; /* CF 66 status */
11361  vuint32_t CFS65:1; /* CF 65 status */
11362  vuint32_t CFS64:1; /* CF 64 status */
11363  } B;
11364  } FCCU_CFS2_32B_tag;
11365 
11366  typedef union { /* FCCU CF Status Register 3 */
11367  vuint32_t R;
11368  struct {
11369  vuint32_t CFS127:1; /* CF 127 status */
11370  vuint32_t CFS126:1; /* CF 126 status */
11371  vuint32_t CFS125:1; /* CF 125 status */
11372  vuint32_t CFS124:1; /* CF 124 status */
11373  vuint32_t CFS123:1; /* CF 123 status */
11374  vuint32_t CFS122:1; /* CF 122 status */
11375  vuint32_t CFS121:1; /* CF 121 status */
11376  vuint32_t CFS120:1; /* CF 120 status */
11377  vuint32_t CFS119:1; /* CF 119 status */
11378  vuint32_t CFS118:1; /* CF 118 status */
11379  vuint32_t CFS117:1; /* CF 117 status */
11380  vuint32_t CFS116:1; /* CF 116 status */
11381  vuint32_t CFS115:1; /* CF 115 status */
11382  vuint32_t CFS114:1; /* CF 114 status */
11383  vuint32_t CFS113:1; /* CF 113 status */
11384  vuint32_t CFS112:1; /* CF 112 status */
11385  vuint32_t CFS111:1; /* CF 111 status */
11386  vuint32_t CFS110:1; /* CF 110 status */
11387  vuint32_t CFS109:1; /* CF 109 status */
11388  vuint32_t CFS108:1; /* CF 108 status */
11389  vuint32_t CFS107:1; /* CF 107 status */
11390  vuint32_t CFS106:1; /* CF 106 status */
11391  vuint32_t CFS105:1; /* CF 105 status */
11392  vuint32_t CFS104:1; /* CF 104 status */
11393  vuint32_t CFS103:1; /* CF 103 status */
11394  vuint32_t CFS102:1; /* CF 102 status */
11395  vuint32_t CFS101:1; /* CF 101 status */
11396  vuint32_t CFS100:1; /* CF 100 status */
11397  vuint32_t CFS99:1; /* CF 99 status */
11398  vuint32_t CFS98:1; /* CF 98 status */
11399  vuint32_t CFS97:1; /* CF 97 status */
11400  vuint32_t CFS96:1; /* CF 96 status */
11401  } B;
11402  } FCCU_CFS3_32B_tag;
11403 
11404  typedef union { /* FCCU_CFK - FCCU CF Key Register */
11405  vuint32_t R;
11406  } FCCU_CFK_32B_tag;
11407 
11408  typedef union { /* FCCU NCF Status Register 0 */
11409  vuint32_t R;
11410  struct {
11411  vuint32_t NCFS31:1; /* NCF 31 status */
11412  vuint32_t NCFS30:1; /* NCF 30 status */
11413  vuint32_t NCFS29:1; /* NCF 29 status */
11414  vuint32_t NCFS28:1; /* NCF 28 status */
11415  vuint32_t NCFS27:1; /* NCF 27 status */
11416  vuint32_t NCFS26:1; /* NCF 26 status */
11417  vuint32_t NCFS25:1; /* NCF 25 status */
11418  vuint32_t NCFS24:1; /* NCF 24 status */
11419  vuint32_t NCFS23:1; /* NCF 23 status */
11420  vuint32_t NCFS22:1; /* NCF 22 status */
11421  vuint32_t NCFS21:1; /* NCF 21 status */
11422  vuint32_t NCFS20:1; /* NCF 20 status */
11423  vuint32_t NCFS19:1; /* NCF 19 status */
11424  vuint32_t NCFS18:1; /* NCF 18 status */
11425  vuint32_t NCFS17:1; /* NCF 17 status */
11426  vuint32_t NCFS16:1; /* NCF 16 status */
11427  vuint32_t NCFS15:1; /* NCF 15 status */
11428  vuint32_t NCFS14:1; /* NCF 14 status */
11429  vuint32_t NCFS13:1; /* NCF 13 status */
11430  vuint32_t NCFS12:1; /* NCF 12 status */
11431  vuint32_t NCFS11:1; /* NCF 11 status */
11432  vuint32_t NCFS10:1; /* NCF 10 status */
11433  vuint32_t NCFS9:1; /* NCF 9 status */
11434  vuint32_t NCFS8:1; /* NCF 8 status */
11435  vuint32_t NCFS7:1; /* NCF 7 status */
11436  vuint32_t NCFS6:1; /* NCF 6 status */
11437  vuint32_t NCFS5:1; /* NCF 5 status */
11438  vuint32_t NCFS4:1; /* NCF 4 status */
11439  vuint32_t NCFS3:1; /* NCF 3 status */
11440  vuint32_t NCFS2:1; /* NCF 2 status */
11441  vuint32_t NCFS1:1; /* NCF 1 status */
11442  vuint32_t NCFS0:1; /* NCF 0 status */
11443  } B;
11444  } FCCU_NCFS0_32B_tag;
11445 
11446  typedef union { /* FCCU NCF Status Register 1 */
11447  vuint32_t R;
11448  struct {
11449  vuint32_t NCFS63:1; /* NCF 63 status */
11450  vuint32_t NCFS62:1; /* NCF 62 status */
11451  vuint32_t NCFS61:1; /* NCF 61 status */
11452  vuint32_t NCFS60:1; /* NCF 60 status */
11453  vuint32_t NCFS59:1; /* NCF 59 status */
11454  vuint32_t NCFS58:1; /* NCF 58 status */
11455  vuint32_t NCFS57:1; /* NCF 57 status */
11456  vuint32_t NCFS56:1; /* NCF 56 status */
11457  vuint32_t NCFS55:1; /* NCF 55 status */
11458  vuint32_t NCFS54:1; /* NCF 54 status */
11459  vuint32_t NCFS53:1; /* NCF 53 status */
11460  vuint32_t NCFS52:1; /* NCF 52 status */
11461  vuint32_t NCFS51:1; /* NCF 51 status */
11462  vuint32_t NCFS50:1; /* NCF 50 status */
11463  vuint32_t NCFS49:1; /* NCF 49 status */
11464  vuint32_t NCFS48:1; /* NCF 48 status */
11465  vuint32_t NCFS47:1; /* NCF 47 status */
11466  vuint32_t NCFS46:1; /* NCF 46 status */
11467  vuint32_t NCFS45:1; /* NCF 45 status */
11468  vuint32_t NCFS44:1; /* NCF 44 status */
11469  vuint32_t NCFS43:1; /* NCF 43 status */
11470  vuint32_t NCFS42:1; /* NCF 42 status */
11471  vuint32_t NCFS41:1; /* NCF 41 status */
11472  vuint32_t NCFS40:1; /* NCF 40 status */
11473  vuint32_t NCFS39:1; /* NCF 39 status */
11474  vuint32_t NCFS38:1; /* NCF 38 status */
11475  vuint32_t NCFS37:1; /* NCF 37 status */
11476  vuint32_t NCFS36:1; /* NCF 36 status */
11477  vuint32_t NCFS35:1; /* NCF 35 status */
11478  vuint32_t NCFS34:1; /* NCF 34 status */
11479  vuint32_t NCFS33:1; /* NCF 33 status */
11480  vuint32_t NCFS32:1; /* NCF 32 status */
11481  } B;
11482  } FCCU_NCFS1_32B_tag;
11483 
11484  typedef union { /* FCCU NCF Status Register 2 */
11485  vuint32_t R;
11486  struct {
11487  vuint32_t NCFS95:1; /* NCF 95 status */
11488  vuint32_t NCFS94:1; /* NCF 94 status */
11489  vuint32_t NCFS93:1; /* NCF 93 status */
11490  vuint32_t NCFS92:1; /* NCF 92 status */
11491  vuint32_t NCFS91:1; /* NCF 91 status */
11492  vuint32_t NCFS90:1; /* NCF 90 status */
11493  vuint32_t NCFS89:1; /* NCF 89 status */
11494  vuint32_t NCFS88:1; /* NCF 88 status */
11495  vuint32_t NCFS87:1; /* NCF 87 status */
11496  vuint32_t NCFS86:1; /* NCF 86 status */
11497  vuint32_t NCFS85:1; /* NCF 85 status */
11498  vuint32_t NCFS84:1; /* NCF 84 status */
11499  vuint32_t NCFS83:1; /* NCF 83 status */
11500  vuint32_t NCFS82:1; /* NCF 82 status */
11501  vuint32_t NCFS81:1; /* NCF 81 status */
11502  vuint32_t NCFS80:1; /* NCF 80 status */
11503  vuint32_t NCFS79:1; /* NCF 79 status */
11504  vuint32_t NCFS78:1; /* NCF 78 status */
11505  vuint32_t NCFS77:1; /* NCF 77 status */
11506  vuint32_t NCFS76:1; /* NCF 76 status */
11507  vuint32_t NCFS75:1; /* NCF 75 status */
11508  vuint32_t NCFS74:1; /* NCF 74 status */
11509  vuint32_t NCFS73:1; /* NCF 73 status */
11510  vuint32_t NCFS72:1; /* NCF 72 status */
11511  vuint32_t NCFS71:1; /* NCF 71 status */
11512  vuint32_t NCFS70:1; /* NCF 70 status */
11513  vuint32_t NCFS69:1; /* NCF 69 status */
11514  vuint32_t NCFS68:1; /* NCF 68 status */
11515  vuint32_t NCFS67:1; /* NCF 67 status */
11516  vuint32_t NCFS66:1; /* NCF 66 status */
11517  vuint32_t NCFS65:1; /* NCF 65 status */
11518  vuint32_t NCFS64:1; /* NCF 64 status */
11519  } B;
11520  } FCCU_NCFS2_32B_tag;
11521 
11522  typedef union { /* FCCU NCF Status Register 3 */
11523  vuint32_t R;
11524  struct {
11525  vuint32_t NCFS127:1; /* NCF 127 status */
11526  vuint32_t NCFS126:1; /* NCF 126 status */
11527  vuint32_t NCFS125:1; /* NCF 125 status */
11528  vuint32_t NCFS124:1; /* NCF 124 status */
11529  vuint32_t NCFS123:1; /* NCF 123 status */
11530  vuint32_t NCFS122:1; /* NCF 122 status */
11531  vuint32_t NCFS121:1; /* NCF 121 status */
11532  vuint32_t NCFS120:1; /* NCF 120 status */
11533  vuint32_t NCFS119:1; /* NCF 119 status */
11534  vuint32_t NCFS118:1; /* NCF 118 status */
11535  vuint32_t NCFS117:1; /* NCF 117 status */
11536  vuint32_t NCFS116:1; /* NCF 116 status */
11537  vuint32_t NCFS115:1; /* NCF 115 status */
11538  vuint32_t NCFS114:1; /* NCF 114 status */
11539  vuint32_t NCFS113:1; /* NCF 113 status */
11540  vuint32_t NCFS112:1; /* NCF 112 status */
11541  vuint32_t NCFS111:1; /* NCF 111 status */
11542  vuint32_t NCFS110:1; /* NCF 110 status */
11543  vuint32_t NCFS109:1; /* NCF 109 status */
11544  vuint32_t NCFS108:1; /* NCF 108 status */
11545  vuint32_t NCFS107:1; /* NCF 107 status */
11546  vuint32_t NCFS106:1; /* NCF 106 status */
11547  vuint32_t NCFS105:1; /* NCF 105 status */
11548  vuint32_t NCFS104:1; /* NCF 104 status */
11549  vuint32_t NCFS103:1; /* NCF 103 status */
11550  vuint32_t NCFS102:1; /* NCF 102 status */
11551  vuint32_t NCFS101:1; /* NCF 101 status */
11552  vuint32_t NCFS100:1; /* NCF 100 status */
11553  vuint32_t NCFS99:1; /* NCF 99 status */
11554  vuint32_t NCFS98:1; /* NCF 98 status */
11555  vuint32_t NCFS97:1; /* NCF 97 status */
11556  vuint32_t NCFS96:1; /* NCF 96 status */
11557  } B;
11558  } FCCU_NCFS3_32B_tag;
11559 
11560  typedef union { /* FCCU_NCFK - FCCU NCF Key Register */
11561  vuint32_t R;
11562  } FCCU_NCFK_32B_tag;
11563 
11564  typedef union { /* FCCU NCF Enable Register 0 */
11565  vuint32_t R;
11566  struct {
11567  vuint32_t NCFE31:1; /* NCF 31 enable */
11568  vuint32_t NCFE30:1; /* NCF 30 enable */
11569  vuint32_t NCFE29:1; /* NCF 29 enable */
11570  vuint32_t NCFE28:1; /* NCF 28 enable */
11571  vuint32_t NCFE27:1; /* NCF 27 enable */
11572  vuint32_t NCFE26:1; /* NCF 26 enable */
11573  vuint32_t NCFE25:1; /* NCF 25 enable */
11574  vuint32_t NCFE24:1; /* NCF 24 enable */
11575  vuint32_t NCFE23:1; /* NCF 23 enable */
11576  vuint32_t NCFE22:1; /* NCF 22 enable */
11577  vuint32_t NCFE21:1; /* NCF 21 enable */
11578  vuint32_t NCFE20:1; /* NCF 20 enable */
11579  vuint32_t NCFE19:1; /* NCF 19 enable */
11580  vuint32_t NCFE18:1; /* NCF 18 enable */
11581  vuint32_t NCFE17:1; /* NCF 17 enable */
11582  vuint32_t NCFE16:1; /* NCF 16 enable */
11583  vuint32_t NCFE15:1; /* NCF 15 enable */
11584  vuint32_t NCFE14:1; /* NCF 14 enable */
11585  vuint32_t NCFE13:1; /* NCF 13 enable */
11586  vuint32_t NCFE12:1; /* NCF 12 enable */
11587  vuint32_t NCFE11:1; /* NCF 11 enable */
11588  vuint32_t NCFE10:1; /* NCF 10 enable */
11589  vuint32_t NCFE9:1; /* NCF 9 enable */
11590  vuint32_t NCFE8:1; /* NCF 8 enable */
11591  vuint32_t NCFE7:1; /* NCF 7 enable */
11592  vuint32_t NCFE6:1; /* NCF 6 enable */
11593  vuint32_t NCFE5:1; /* NCF 5 enable */
11594  vuint32_t NCFE4:1; /* NCF 4 enable */
11595  vuint32_t NCFE3:1; /* NCF 3 enable */
11596  vuint32_t NCFE2:1; /* NCF 2 enable */
11597  vuint32_t NCFE1:1; /* NCF 1 enable */
11598  vuint32_t NCFE0:1; /* NCF 0 enable */
11599  } B;
11600  } FCCU_NCFE0_32B_tag;
11601 
11602  typedef union { /* FCCU NCF Enable Register 1 */
11603  vuint32_t R;
11604  struct {
11605  vuint32_t NCFE63:1; /* NCF 63 enable */
11606  vuint32_t NCFE62:1; /* NCF 62 enable */
11607  vuint32_t NCFE61:1; /* NCF 61 enable */
11608  vuint32_t NCFE60:1; /* NCF 60 enable */
11609  vuint32_t NCFE59:1; /* NCF 59 enable */
11610  vuint32_t NCFE58:1; /* NCF 58 enable */
11611  vuint32_t NCFE57:1; /* NCF 57 enable */
11612  vuint32_t NCFE56:1; /* NCF 56 enable */
11613  vuint32_t NCFE55:1; /* NCF 55 enable */
11614  vuint32_t NCFE54:1; /* NCF 54 enable */
11615  vuint32_t NCFE53:1; /* NCF 53 enable */
11616  vuint32_t NCFE52:1; /* NCF 52 enable */
11617  vuint32_t NCFE51:1; /* NCF 51 enable */
11618  vuint32_t NCFE50:1; /* NCF 50 enable */
11619  vuint32_t NCFE49:1; /* NCF 49 enable */
11620  vuint32_t NCFE48:1; /* NCF 48 enable */
11621  vuint32_t NCFE47:1; /* NCF 47 enable */
11622  vuint32_t NCFE46:1; /* NCF 46 enable */
11623  vuint32_t NCFE45:1; /* NCF 45 enable */
11624  vuint32_t NCFE44:1; /* NCF 44 enable */
11625  vuint32_t NCFE43:1; /* NCF 43 enable */
11626  vuint32_t NCFE42:1; /* NCF 42 enable */
11627  vuint32_t NCFE41:1; /* NCF 41 enable */
11628  vuint32_t NCFE40:1; /* NCF 40 enable */
11629  vuint32_t NCFE39:1; /* NCF 39 enable */
11630  vuint32_t NCFE38:1; /* NCF 38 enable */
11631  vuint32_t NCFE37:1; /* NCF 37 enable */
11632  vuint32_t NCFE36:1; /* NCF 36 enable */
11633  vuint32_t NCFE35:1; /* NCF 35 enable */
11634  vuint32_t NCFE34:1; /* NCF 34 enable */
11635  vuint32_t NCFE33:1; /* NCF 33 enable */
11636  vuint32_t NCFE32:1; /* NCF 32 enable */
11637  } B;
11638  } FCCU_NCFE1_32B_tag;
11639 
11640  typedef union { /* FCCU NCF Enable Register 2 */
11641  vuint32_t R;
11642  struct {
11643  vuint32_t NCFE95:1; /* NCF 95 enable */
11644  vuint32_t NCFE94:1; /* NCF 94 enable */
11645  vuint32_t NCFE93:1; /* NCF 93 enable */
11646  vuint32_t NCFE92:1; /* NCF 92 enable */
11647  vuint32_t NCFE91:1; /* NCF 91 enable */
11648  vuint32_t NCFE90:1; /* NCF 90 enable */
11649  vuint32_t NCFE89:1; /* NCF 89 enable */
11650  vuint32_t NCFE88:1; /* NCF 88 enable */
11651  vuint32_t NCFE87:1; /* NCF 87 enable */
11652  vuint32_t NCFE86:1; /* NCF 86 enable */
11653  vuint32_t NCFE85:1; /* NCF 85 enable */
11654  vuint32_t NCFE84:1; /* NCF 84 enable */
11655  vuint32_t NCFE83:1; /* NCF 83 enable */
11656  vuint32_t NCFE82:1; /* NCF 82 enable */
11657  vuint32_t NCFE81:1; /* NCF 81 enable */
11658  vuint32_t NCFE80:1; /* NCF 80 enable */
11659  vuint32_t NCFE79:1; /* NCF 79 enable */
11660  vuint32_t NCFE78:1; /* NCF 78 enable */
11661  vuint32_t NCFE77:1; /* NCF 77 enable */
11662  vuint32_t NCFE76:1; /* NCF 76 enable */
11663  vuint32_t NCFE75:1; /* NCF 75 enable */
11664  vuint32_t NCFE74:1; /* NCF 74 enable */
11665  vuint32_t NCFE73:1; /* NCF 73 enable */
11666  vuint32_t NCFE72:1; /* NCF 72 enable */
11667  vuint32_t NCFE71:1; /* NCF 71 enable */
11668  vuint32_t NCFE70:1; /* NCF 70 enable */
11669  vuint32_t NCFE69:1; /* NCF 69 enable */
11670  vuint32_t NCFE68:1; /* NCF 68 enable */
11671  vuint32_t NCFE67:1; /* NCF 67 enable */
11672  vuint32_t NCFE66:1; /* NCF 66 enable */
11673  vuint32_t NCFE65:1; /* NCF 65 enable */
11674  vuint32_t NCFE64:1; /* NCF 64 enable */
11675  } B;
11676  } FCCU_NCFE2_32B_tag;
11677 
11678  typedef union { /* FCCU NCF Enable Register 3 */
11679  vuint32_t R;
11680  struct {
11681  vuint32_t NCFE127:1; /* NCF 127 enable */
11682  vuint32_t NCFE126:1; /* NCF 126 enable */
11683  vuint32_t NCFE125:1; /* NCF 125 enable */
11684  vuint32_t NCFE124:1; /* NCF 124 enable */
11685  vuint32_t NCFE123:1; /* NCF 123 enable */
11686  vuint32_t NCFE122:1; /* NCF 122 enable */
11687  vuint32_t NCFE121:1; /* NCF 121 enable */
11688  vuint32_t NCFE120:1; /* NCF 120 enable */
11689  vuint32_t NCFE119:1; /* NCF 119 enable */
11690  vuint32_t NCFE118:1; /* NCF 118 enable */
11691  vuint32_t NCFE117:1; /* NCF 117 enable */
11692  vuint32_t NCFE116:1; /* NCF 116 enable */
11693  vuint32_t NCFE115:1; /* NCF 115 enable */
11694  vuint32_t NCFE114:1; /* NCF 114 enable */
11695  vuint32_t NCFE113:1; /* NCF 113 enable */
11696  vuint32_t NCFE112:1; /* NCF 112 enable */
11697  vuint32_t NCFE111:1; /* NCF 111 enable */
11698  vuint32_t NCFE110:1; /* NCF 110 enable */
11699  vuint32_t NCFE109:1; /* NCF 109 enable */
11700  vuint32_t NCFE108:1; /* NCF 108 enable */
11701  vuint32_t NCFE107:1; /* NCF 107 enable */
11702  vuint32_t NCFE106:1; /* NCF 106 enable */
11703  vuint32_t NCFE105:1; /* NCF 105 enable */
11704  vuint32_t NCFE104:1; /* NCF 104 enable */
11705  vuint32_t NCFE103:1; /* NCF 103 enable */
11706  vuint32_t NCFE102:1; /* NCF 102 enable */
11707  vuint32_t NCFE101:1; /* NCF 101 enable */
11708  vuint32_t NCFE100:1; /* NCF 100 enable */
11709  vuint32_t NCFE99:1; /* NCF 99 enable */
11710  vuint32_t NCFE98:1; /* NCF 98 enable */
11711  vuint32_t NCFE97:1; /* NCF 97 enable */
11712  vuint32_t NCFE96:1; /* NCF 96 enable */
11713  } B;
11714  } FCCU_NCFE3_32B_tag;
11715 
11716  typedef union { /* FCCU NCF Time-out Enable Register 0 */
11717  vuint32_t R;
11718  struct {
11719  vuint32_t NCFTOE31:1; /* NCF 31 time-out enable */
11720  vuint32_t NCFTOE30:1; /* NCF 30 time-out enable */
11721  vuint32_t NCFTOE29:1; /* NCF 29 time-out enable */
11722  vuint32_t NCFTOE28:1; /* NCF 28 time-out enable */
11723  vuint32_t NCFTOE27:1; /* NCF 27 time-out enable */
11724  vuint32_t NCFTOE26:1; /* NCF 26 time-out enable */
11725  vuint32_t NCFTOE25:1; /* NCF 25 time-out enable */
11726  vuint32_t NCFTOE24:1; /* NCF 24 time-out enable */
11727  vuint32_t NCFTOE23:1; /* NCF 23 time-out enable */
11728  vuint32_t NCFTOE22:1; /* NCF 22 time-out enable */
11729  vuint32_t NCFTOE21:1; /* NCF 21 time-out enable */
11730  vuint32_t NCFTOE20:1; /* NCF 20 time-out enable */
11731  vuint32_t NCFTOE19:1; /* NCF 19 time-out enable */
11732  vuint32_t NCFTOE18:1; /* NCF 18 time-out enable */
11733  vuint32_t NCFTOE17:1; /* NCF 17 time-out enable */
11734  vuint32_t NCFTOE16:1; /* NCF 16 time-out enable */
11735  vuint32_t NCFTOE15:1; /* NCF 15 time-out enable */
11736  vuint32_t NCFTOE14:1; /* NCF 14 time-out enable */
11737  vuint32_t NCFTOE13:1; /* NCF 13 time-out enable */
11738  vuint32_t NCFTOE12:1; /* NCF 12 time-out enable */
11739  vuint32_t NCFTOE11:1; /* NCF 11 time-out enable */
11740  vuint32_t NCFTOE10:1; /* NCF 10 time-out enable */
11741  vuint32_t NCFTOE9:1; /* NCF 9 time-out enable */
11742  vuint32_t NCFTOE8:1; /* NCF 8 time-out enable */
11743  vuint32_t NCFTOE7:1; /* NCF 7 time-out enable */
11744  vuint32_t NCFTOE6:1; /* NCF 6 time-out enable */
11745  vuint32_t NCFTOE5:1; /* NCF 5 time-out enable */
11746  vuint32_t NCFTOE4:1; /* NCF 4 time-out enable */
11747  vuint32_t NCFTOE3:1; /* NCF 3 time-out enable */
11748  vuint32_t NCFTOE2:1; /* NCF 2 time-out enable */
11749  vuint32_t NCFTOE1:1; /* NCF 1 time-out enable */
11750  vuint32_t NCFTOE0:1; /* NCF 0 time-out enable */
11751  } B;
11752  } FCCU_NCF_TOE0_32B_tag;
11753 
11754  typedef union { /* FCCU NCF Time-out Enable Register 1 */
11755  vuint32_t R;
11756  struct {
11757  vuint32_t NCFTOE63:1; /* NCF 63 time-out enable */
11758  vuint32_t NCFTOE62:1; /* NCF 62 time-out enable */
11759  vuint32_t NCFTOE61:1; /* NCF 61 time-out enable */
11760  vuint32_t NCFTOE60:1; /* NCF 60 time-out enable */
11761  vuint32_t NCFTOE59:1; /* NCF 59 time-out enable */
11762  vuint32_t NCFTOE58:1; /* NCF 58 time-out enable */
11763  vuint32_t NCFTOE57:1; /* NCF 57 time-out enable */
11764  vuint32_t NCFTOE56:1; /* NCF 56 time-out enable */
11765  vuint32_t NCFTOE55:1; /* NCF 55 time-out enable */
11766  vuint32_t NCFTOE54:1; /* NCF 54 time-out enable */
11767  vuint32_t NCFTOE53:1; /* NCF 53 time-out enable */
11768  vuint32_t NCFTOE52:1; /* NCF 52 time-out enable */
11769  vuint32_t NCFTOE51:1; /* NCF 51 time-out enable */
11770  vuint32_t NCFTOE50:1; /* NCF 50 time-out enable */
11771  vuint32_t NCFTOE49:1; /* NCF 49 time-out enable */
11772  vuint32_t NCFTOE48:1; /* NCF 48 time-out enable */
11773  vuint32_t NCFTOE47:1; /* NCF 47 time-out enable */
11774  vuint32_t NCFTOE46:1; /* NCF 46 time-out enable */
11775  vuint32_t NCFTOE45:1; /* NCF 45 time-out enable */
11776  vuint32_t NCFTOE44:1; /* NCF 44 time-out enable */
11777  vuint32_t NCFTOE43:1; /* NCF 43 time-out enable */
11778  vuint32_t NCFTOE42:1; /* NCF 42 time-out enable */
11779  vuint32_t NCFTOE41:1; /* NCF 41 time-out enable */
11780  vuint32_t NCFTOE40:1; /* NCF 40 time-out enable */
11781  vuint32_t NCFTOE39:1; /* NCF 39 time-out enable */
11782  vuint32_t NCFTOE38:1; /* NCF 38 time-out enable */
11783  vuint32_t NCFTOE37:1; /* NCF 37 time-out enable */
11784  vuint32_t NCFTOE36:1; /* NCF 36 time-out enable */
11785  vuint32_t NCFTOE35:1; /* NCF 35 time-out enable */
11786  vuint32_t NCFTOE34:1; /* NCF 34 time-out enable */
11787  vuint32_t NCFTOE33:1; /* NCF 33 time-out enable */
11788  vuint32_t NCFTOE32:1; /* NCF 32 time-out enable */
11789  } B;
11790  } FCCU_NCF_TOE1_32B_tag;
11791 
11792  typedef union { /* FCCU NCF Time-out Enable Register 2 */
11793  vuint32_t R;
11794  struct {
11795  vuint32_t NCFTOE95:1; /* NCF 95 time-out enable */
11796  vuint32_t NCFTOE94:1; /* NCF 94 time-out enable */
11797  vuint32_t NCFTOE93:1; /* NCF 93 time-out enable */
11798  vuint32_t NCFTOE92:1; /* NCF 92 time-out enable */
11799  vuint32_t NCFTOE91:1; /* NCF 91 time-out enable */
11800  vuint32_t NCFTOE90:1; /* NCF 90 time-out enable */
11801  vuint32_t NCFTOE89:1; /* NCF 89 time-out enable */
11802  vuint32_t NCFTOE88:1; /* NCF 88 time-out enable */
11803  vuint32_t NCFTOE87:1; /* NCF 87 time-out enable */
11804  vuint32_t NCFTOE86:1; /* NCF 86 time-out enable */
11805  vuint32_t NCFTOE85:1; /* NCF 85 time-out enable */
11806  vuint32_t NCFTOE84:1; /* NCF 84 time-out enable */
11807  vuint32_t NCFTOE83:1; /* NCF 83 time-out enable */
11808  vuint32_t NCFTOE82:1; /* NCF 82 time-out enable */
11809  vuint32_t NCFTOE81:1; /* NCF 81 time-out enable */
11810  vuint32_t NCFTOE80:1; /* NCF 80 time-out enable */
11811  vuint32_t NCFTOE79:1; /* NCF 79 time-out enable */
11812  vuint32_t NCFTOE78:1; /* NCF 78 time-out enable */
11813  vuint32_t NCFTOE77:1; /* NCF 77 time-out enable */
11814  vuint32_t NCFTOE76:1; /* NCF 76 time-out enable */
11815  vuint32_t NCFTOE75:1; /* NCF 75 time-out enable */
11816  vuint32_t NCFTOE74:1; /* NCF 74 time-out enable */
11817  vuint32_t NCFTOE73:1; /* NCF 73 time-out enable */
11818  vuint32_t NCFTOE72:1; /* NCF 72 time-out enable */
11819  vuint32_t NCFTOE71:1; /* NCF 71 time-out enable */
11820  vuint32_t NCFTOE70:1; /* NCF 70 time-out enable */
11821  vuint32_t NCFTOE69:1; /* NCF 69 time-out enable */
11822  vuint32_t NCFTOE68:1; /* NCF 68 time-out enable */
11823  vuint32_t NCFTOE67:1; /* NCF 67 time-out enable */
11824  vuint32_t NCFTOE66:1; /* NCF 66 time-out enable */
11825  vuint32_t NCFTOE65:1; /* NCF 65 time-out enable */
11826  vuint32_t NCFTOE64:1; /* NCF 64 time-out enable */
11827  } B;
11828  } FCCU_NCF_TOE2_32B_tag;
11829 
11830  typedef union { /* FCCU NCF Time-out Enable Register 3 */
11831  vuint32_t R;
11832  struct {
11833  vuint32_t NCFTOE127:1; /* NCF 127 time-out enable */
11834  vuint32_t NCFTOE126:1; /* NCF 126 time-out enable */
11835  vuint32_t NCFTOE125:1; /* NCF 125 time-out enable */
11836  vuint32_t NCFTOE124:1; /* NCF 124 time-out enable */
11837  vuint32_t NCFTOE123:1; /* NCF 123 time-out enable */
11838  vuint32_t NCFTOE122:1; /* NCF 122 time-out enable */
11839  vuint32_t NCFTOE121:1; /* NCF 121 time-out enable */
11840  vuint32_t NCFTOE120:1; /* NCF 120 time-out enable */
11841  vuint32_t NCFTOE119:1; /* NCF 119 time-out enable */
11842  vuint32_t NCFTOE118:1; /* NCF 118 time-out enable */
11843  vuint32_t NCFTOE117:1; /* NCF 117 time-out enable */
11844  vuint32_t NCFTOE116:1; /* NCF 116 time-out enable */
11845  vuint32_t NCFTOE115:1; /* NCF 115 time-out enable */
11846  vuint32_t NCFTOE114:1; /* NCF 114 time-out enable */
11847  vuint32_t NCFTOE113:1; /* NCF 113 time-out enable */
11848  vuint32_t NCFTOE112:1; /* NCF 112 time-out enable */
11849  vuint32_t NCFTOE111:1; /* NCF 111 time-out enable */
11850  vuint32_t NCFTOE110:1; /* NCF 110 time-out enable */
11851  vuint32_t NCFTOE109:1; /* NCF 109 time-out enable */
11852  vuint32_t NCFTOE108:1; /* NCF 108 time-out enable */
11853  vuint32_t NCFTOE107:1; /* NCF 107 time-out enable */
11854  vuint32_t NCFTOE106:1; /* NCF 106 time-out enable */
11855  vuint32_t NCFTOE105:1; /* NCF 105 time-out enable */
11856  vuint32_t NCFTOE104:1; /* NCF 104 time-out enable */
11857  vuint32_t NCFTOE103:1; /* NCF 103 time-out enable */
11858  vuint32_t NCFTOE102:1; /* NCF 102 time-out enable */
11859  vuint32_t NCFTOE101:1; /* NCF 101 time-out enable */
11860  vuint32_t NCFTOE100:1; /* NCF 100 time-out enable */
11861  vuint32_t NCFTOE99:1; /* NCF 99 time-out enable */
11862  vuint32_t NCFTOE98:1; /* NCF 98 time-out enable */
11863  vuint32_t NCFTOE97:1; /* NCF 97 time-out enable */
11864  vuint32_t NCFTOE96:1; /* NCF 96 time-out enable */
11865  } B;
11866  } FCCU_NCF_TOE3_32B_tag;
11867 
11868  typedef union { /* FCCU_NCF_TO - FCCU NCF Time-out Register */
11869  vuint32_t R;
11870  } FCCU_NCF_TO_32B_tag;
11871 
11872  typedef union { /* FCCU_CFG_TO - FCCU CFG Timeout Register */
11873  vuint32_t R;
11874  struct {
11875  vuint32_t:29;
11876  vuint32_t TO:3; /* Configuration time-out */
11877  } B;
11878  } FCCU_CFG_TO_32B_tag;
11879 
11880  typedef union { /* FCCU_EINOUT - FCCU IO Control Register */
11881  vuint32_t R;
11882  struct {
11883  vuint32_t:26;
11884  vuint32_t EIN1:1; /* Error input 1 */
11885  vuint32_t EIN0:1; /* Error input 0 */
11886  vuint32_t:2;
11887  vuint32_t EOUT1:1; /* Error out 1 */
11888  vuint32_t EOUT0:1; /* Error out 0 */
11889  } B;
11890  } FCCU_EINOUT_32B_tag;
11891 
11892  typedef union { /* FCCU_STAT - FCCU Status Register */
11893  vuint32_t R;
11894  struct {
11895  vuint32_t:29;
11896  vuint32_t STATUS:3; /* FCCU status */
11897  } B;
11898  } FCCU_STAT_32B_tag;
11899 
11900  typedef union { /* FCCU_NAFS - FCCU NA Freeze Status Register */
11901  vuint32_t R;
11902  struct {
11903  vuint32_t:24;
11904  vuint32_t N2AFSTATUS:8; /* Normal to Alarm Frozen Status */
11905  } B;
11906  } FCCU_NAFS_32B_tag;
11907 
11908  typedef union { /* FCCU_AFFS - FCCU AF Freeze Status Register */
11909  vuint32_t R;
11910  struct {
11911  vuint32_t:22;
11912  vuint32_t AFFS_SRC:2; /* Fault source */
11913  vuint32_t A2AFSTATUS:8; /* Alarm to Fault Frozen Status */
11914  } B;
11915  } FCCU_AFFS_32B_tag;
11916 
11917  typedef union { /* FCCU_NFFS - FCCU NF Freeze Status Register */
11918  vuint32_t R;
11919  struct {
11920  vuint32_t:22;
11921  vuint32_t NFFS_SRC:2; /* Fault source */
11922  vuint32_t NFFS_NFFS:8; /* Normal to Fault Frozen Status */
11923  } B;
11924  } FCCU_NFFS_32B_tag;
11925 
11926  typedef union { /* FCCU_FAFS - FCCU FA Freeze Status Register */
11927  vuint32_t R;
11928  struct {
11929  vuint32_t:24;
11930  vuint32_t FAFS_FAFS:8; /* Fault to Normal Frozen Status */
11931  } B;
11932  } FCCU_FAFS_32B_tag;
11933 
11934  typedef union { /* FCCU_SCFS - FCCU SC Freeze Status Register */
11935  vuint32_t R;
11936  struct {
11937  vuint32_t:30;
11938  vuint32_t RCCS1:1; /* RCC1 Status */
11939  vuint32_t RCCS0:1; /* RCC0 Status */
11940  } B;
11941  } FCCU_SCFS_32B_tag;
11942 
11943  typedef union { /* FCCU_CFF - FCCU CF Fake Register */
11944  vuint32_t R;
11945  struct {
11946  vuint32_t:25;
11947  vuint32_t FCFC:7; /* Fake critical fault code */
11948  } B;
11949  } FCCU_CFF_32B_tag;
11950 
11951  typedef union { /* FCCU_NCFF - FCCU NCF Fake Register */
11952  vuint32_t R;
11953  struct {
11954  vuint32_t:25;
11955  vuint32_t FNCFC:7; /* Fake non-critical fault code */
11956  } B;
11957  } FCCU_NCFF_32B_tag;
11958 
11959  typedef union { /* FCCU_IRQ_STAT - FCCU IRQ Status Register */
11960  vuint32_t R;
11961  struct {
11962  vuint32_t:29;
11963  vuint32_t NMI_STAT:1; /* NMI Interrupt Status */
11964  vuint32_t ALRM_STAT:1; /* Alarm Interrupt Status */
11965  vuint32_t CFG_TO_STAT:1; /* Configuration Time-out Status */
11966  } B;
11967  } FCCU_IRQ_STAT_32B_tag;
11968 
11969  typedef union { /* FCCU_IRQ_EN - FCCU IRQ Enable Register */
11970  vuint32_t R;
11971  struct {
11972  vuint32_t:31;
11973  vuint32_t CFG_TO_IEN:1; /* Configuration Time-out Interrupt Enable */
11974  } B;
11975  } FCCU_IRQ_EN_32B_tag;
11976 
11977  typedef union { /* FCCU_XTMR - FCCU XTMR Register */
11978  vuint32_t R;
11979  struct {
11980  vuint32_t XTMR_XTMR:32; /* Alarm/Watchdog/safe request timer */
11981  } B;
11982  } FCCU_XTMR_32B_tag;
11983 
11984  typedef union { /* FCCU_MCS - FCCU MCS Register */
11985  vuint32_t R;
11986  struct {
11987  vuint32_t VL3:1; /* Valid */
11988  vuint32_t FS3:1; /* Fault Status */
11989  vuint32_t:2;
11990  vuint32_t MCS3:4; /* Magic Carpet oldest state */
11991  vuint32_t VL2:1; /* Valid */
11992  vuint32_t FS2:1; /* Fault Status */
11993  vuint32_t:2;
11994  vuint32_t MCS2:4; /* Magic Carpet previous-previous state */
11995  vuint32_t VL1:1; /* Valid */
11996  vuint32_t FS1:1; /* Fault Status */
11997  vuint32_t:2;
11998  vuint32_t MCS1:4; /* Magic Carpet previous state */
11999  vuint32_t VL0:1; /* Valid */
12000  vuint32_t FS0:1; /* Fault Status */
12001  vuint32_t:2;
12002  vuint32_t MCS0:4; /* Magic Carpet latest state */
12003  } B;
12004  } FCCU_MCS_32B_tag;
12005 
12006 
12007  /* Register layout for generated register(s) CF_CFG... */
12008 
12009  typedef union { /* */
12010  vuint32_t R;
12011  } FCCU_CF_CFG_32B_tag;
12012 
12013 
12014  /* Register layout for generated register(s) NCF_CFG... */
12015 
12016  typedef union { /* */
12017  vuint32_t R;
12018  } FCCU_NCF_CFG_32B_tag;
12019 
12020 
12021  /* Register layout for generated register(s) CFS_CFG... */
12022 
12023  typedef union { /* */
12024  vuint32_t R;
12025  } FCCU_CFS_CFG_32B_tag;
12026 
12027 
12028  /* Register layout for generated register(s) NCFS_CFG... */
12029 
12030  typedef union { /* */
12031  vuint32_t R;
12032  } FCCU_NCFS_CFG_32B_tag;
12033 
12034 
12035  /* Register layout for generated register(s) CFS... */
12036 
12037  typedef union { /* */
12038  vuint32_t R;
12039  } FCCU_CFS_32B_tag;
12040 
12041 
12042  /* Register layout for generated register(s) NCFS... */
12043 
12044  typedef union { /* */
12045  vuint32_t R;
12046  } FCCU_NCFS_32B_tag;
12047 
12048 
12049  /* Register layout for generated register(s) NCFE... */
12050 
12051  typedef union { /* */
12052  vuint32_t R;
12053  } FCCU_NCFE_32B_tag;
12054 
12055 
12056  /* Register layout for generated register(s) NCF_TOE... */
12057 
12058  typedef union { /* */
12059  vuint32_t R;
12060  } FCCU_NCF_TOE_32B_tag;
12061 
12062 
12063 
12064  typedef struct FCCU_struct_tag { /* start of FCCU_tag */
12065  /* FCCU Control Register */
12066  FCCU_CTRL_32B_tag CTRL; /* offset: 0x0000 size: 32 bit */
12067  /* FCCU CTRL Key Register */
12068  FCCU_CTRLK_32B_tag CTRLK; /* offset: 0x0004 size: 32 bit */
12069  /* FCCU Configuration Register */
12070  FCCU_CFG_32B_tag CFG; /* offset: 0x0008 size: 32 bit */
12071  union {
12072  FCCU_CF_CFG_32B_tag CF_CFG[4]; /* offset: 0x000C (0x0004 x 4) */
12073 
12074  struct {
12075  /* FCCU CF Configuration Register 0 */
12076  FCCU_CF_CFG0_32B_tag CF_CFG0; /* offset: 0x000C size: 32 bit */
12077  /* FCCU CF Configuration Register 1 */
12078  FCCU_CF_CFG1_32B_tag CF_CFG1; /* offset: 0x0010 size: 32 bit */
12079  /* FCCU CF Configuration Register 2 */
12080  FCCU_CF_CFG2_32B_tag CF_CFG2; /* offset: 0x0014 size: 32 bit */
12081  /* FCCU CF Configuration Register 3 */
12082  FCCU_CF_CFG3_32B_tag CF_CFG3; /* offset: 0x0018 size: 32 bit */
12083  };
12084 
12085  };
12086  union {
12087  FCCU_NCF_CFG_32B_tag NCF_CFG[4]; /* offset: 0x001C (0x0004 x 4) */
12088 
12089  struct {
12090  /* FCCU NCF Configuration Register 0 */
12091  FCCU_NCF_CFG0_32B_tag NCF_CFG0; /* offset: 0x001C size: 32 bit */
12092  /* FCCU NCF Configuration Register 1 */
12093  FCCU_NCF_CFG1_32B_tag NCF_CFG1; /* offset: 0x0020 size: 32 bit */
12094  /* FCCU NCF Configuration Register 2 */
12095  FCCU_NCF_CFG2_32B_tag NCF_CFG2; /* offset: 0x0024 size: 32 bit */
12096  /* FCCU NCF Configuration Register 3 */
12097  FCCU_NCF_CFG3_32B_tag NCF_CFG3; /* offset: 0x0028 size: 32 bit */
12098  };
12099 
12100  };
12101  union {
12102  FCCU_CFS_CFG_32B_tag CFS_CFG[8]; /* offset: 0x002C (0x0004 x 8) */
12103 
12104  struct {
12105  /* FCCU CFS Configuration Register 0 */
12106  FCCU_CFS_CFG0_32B_tag CFS_CFG0; /* offset: 0x002C size: 32 bit */
12107  /* FCCU CFS Configuration Register 1 */
12108  FCCU_CFS_CFG1_32B_tag CFS_CFG1; /* offset: 0x0030 size: 32 bit */
12109  /* FCCU CFS Configuration Register 2 */
12110  FCCU_CFS_CFG2_32B_tag CFS_CFG2; /* offset: 0x0034 size: 32 bit */
12111  /* FCCU CFS Configuration Register 3 */
12112  FCCU_CFS_CFG3_32B_tag CFS_CFG3; /* offset: 0x0038 size: 32 bit */
12113  /* FCCU CFS Configuration Register 4 */
12114  FCCU_CFS_CFG4_32B_tag CFS_CFG4; /* offset: 0x003C size: 32 bit */
12115  /* FCCU CFS Configuration Register 5 */
12116  FCCU_CFS_CFG5_32B_tag CFS_CFG5; /* offset: 0x0040 size: 32 bit */
12117  /* FCCU CFS Configuration Register 6 */
12118  FCCU_CFS_CFG6_32B_tag CFS_CFG6; /* offset: 0x0044 size: 32 bit */
12119  /* FCCU CFS Configuration Register 7 */
12120  FCCU_CFS_CFG7_32B_tag CFS_CFG7; /* offset: 0x0048 size: 32 bit */
12121  };
12122 
12123  };
12124  union {
12125  FCCU_NCFS_CFG_32B_tag NCFS_CFG[8]; /* offset: 0x004C (0x0004 x 8) */
12126 
12127  struct {
12128  /* FCCU NCFS Configuration Register 0 */
12129  FCCU_NCFS_CFG0_32B_tag NCFS_CFG0; /* offset: 0x004C size: 32 bit */
12130  /* FCCU NCFS Configuration Register 1 */
12131  FCCU_NCFS_CFG1_32B_tag NCFS_CFG1; /* offset: 0x0050 size: 32 bit */
12132  /* FCCU NCFS Configuration Register 2 */
12133  FCCU_NCFS_CFG2_32B_tag NCFS_CFG2; /* offset: 0x0054 size: 32 bit */
12134  /* FCCU NCFS Configuration Register 3 */
12135  FCCU_NCFS_CFG3_32B_tag NCFS_CFG3; /* offset: 0x0058 size: 32 bit */
12136  /* FCCU NCFS Configuration Register 4 */
12137  FCCU_NCFS_CFG4_32B_tag NCFS_CFG4; /* offset: 0x005C size: 32 bit */
12138  /* FCCU NCFS Configuration Register 5 */
12139  FCCU_NCFS_CFG5_32B_tag NCFS_CFG5; /* offset: 0x0060 size: 32 bit */
12140  /* FCCU NCFS Configuration Register 6 */
12141  FCCU_NCFS_CFG6_32B_tag NCFS_CFG6; /* offset: 0x0064 size: 32 bit */
12142  /* FCCU NCFS Configuration Register 7 */
12143  FCCU_NCFS_CFG7_32B_tag NCFS_CFG7; /* offset: 0x0068 size: 32 bit */
12144  };
12145 
12146  };
12147  union {
12148  FCCU_CFS_32B_tag CFS[4]; /* offset: 0x006C (0x0004 x 4) */
12149 
12150  struct {
12151  /* FCCU CF Status Register 0 */
12152  FCCU_CFS0_32B_tag CFS0; /* offset: 0x006C size: 32 bit */
12153  /* FCCU CF Status Register 1 */
12154  FCCU_CFS1_32B_tag CFS1; /* offset: 0x0070 size: 32 bit */
12155  /* FCCU CF Status Register 2 */
12156  FCCU_CFS2_32B_tag CFS2; /* offset: 0x0074 size: 32 bit */
12157  /* FCCU CF Status Register 3 */
12158  FCCU_CFS3_32B_tag CFS3; /* offset: 0x0078 size: 32 bit */
12159  };
12160 
12161  };
12162  /* FCCU_CFK - FCCU CF Key Register */
12163  FCCU_CFK_32B_tag CFK; /* offset: 0x007C size: 32 bit */
12164  union {
12165  FCCU_NCFS_32B_tag NCFS[4]; /* offset: 0x0080 (0x0004 x 4) */
12166 
12167  struct {
12168  /* FCCU NCF Status Register 0 */
12169  FCCU_NCFS0_32B_tag NCFS0; /* offset: 0x0080 size: 32 bit */
12170  /* FCCU NCF Status Register 1 */
12171  FCCU_NCFS1_32B_tag NCFS1; /* offset: 0x0084 size: 32 bit */
12172  /* FCCU NCF Status Register 2 */
12173  FCCU_NCFS2_32B_tag NCFS2; /* offset: 0x0088 size: 32 bit */
12174  /* FCCU NCF Status Register 3 */
12175  FCCU_NCFS3_32B_tag NCFS3; /* offset: 0x008C size: 32 bit */
12176  };
12177 
12178  };
12179  /* FCCU_NCFK - FCCU NCF Key Register */
12180  FCCU_NCFK_32B_tag NCFK; /* offset: 0x0090 size: 32 bit */
12181  union {
12182  FCCU_NCFE_32B_tag NCFE[4]; /* offset: 0x0094 (0x0004 x 4) */
12183 
12184  struct {
12185  /* FCCU NCF Enable Register 0 */
12186  FCCU_NCFE0_32B_tag NCFE0; /* offset: 0x0094 size: 32 bit */
12187  /* FCCU NCF Enable Register 1 */
12188  FCCU_NCFE1_32B_tag NCFE1; /* offset: 0x0098 size: 32 bit */
12189  /* FCCU NCF Enable Register 2 */
12190  FCCU_NCFE2_32B_tag NCFE2; /* offset: 0x009C size: 32 bit */
12191  /* FCCU NCF Enable Register 3 */
12192  FCCU_NCFE3_32B_tag NCFE3; /* offset: 0x00A0 size: 32 bit */
12193  };
12194 
12195  };
12196  union {
12197  FCCU_NCF_TOE_32B_tag NCF_TOE[4]; /* offset: 0x00A4 (0x0004 x 4) */
12198 
12199  struct {
12200  /* FCCU NCF Time-out Enable Register 0 */
12201  FCCU_NCF_TOE0_32B_tag NCF_TOE0; /* offset: 0x00A4 size: 32 bit */
12202  /* FCCU NCF Time-out Enable Register 1 */
12203  FCCU_NCF_TOE1_32B_tag NCF_TOE1; /* offset: 0x00A8 size: 32 bit */
12204  /* FCCU NCF Time-out Enable Register 2 */
12205  FCCU_NCF_TOE2_32B_tag NCF_TOE2; /* offset: 0x00AC size: 32 bit */
12206  /* FCCU NCF Time-out Enable Register 3 */
12207  FCCU_NCF_TOE3_32B_tag NCF_TOE3; /* offset: 0x00B0 size: 32 bit */
12208  };
12209 
12210  };
12211  /* FCCU_NCF_TO - FCCU NCF Time-out Register */
12212  FCCU_NCF_TO_32B_tag NCF_TO; /* offset: 0x00B4 size: 32 bit */
12213  /* FCCU_CFG_TO - FCCU CFG Timeout Register */
12214  FCCU_CFG_TO_32B_tag CFG_TO; /* offset: 0x00B8 size: 32 bit */
12215  /* FCCU_EINOUT - FCCU IO Control Register */
12216  FCCU_EINOUT_32B_tag EINOUT; /* offset: 0x00BC size: 32 bit */
12217  /* FCCU_STAT - FCCU Status Register */
12218  FCCU_STAT_32B_tag STAT; /* offset: 0x00C0 size: 32 bit */
12219  /* FCCU_NAFS - FCCU NA Freeze Status Register */
12220  FCCU_NAFS_32B_tag NAFS; /* offset: 0x00C4 size: 32 bit */
12221  /* FCCU_AFFS - FCCU AF Freeze Status Register */
12222  FCCU_AFFS_32B_tag AFFS; /* offset: 0x00C8 size: 32 bit */
12223  /* FCCU_NFFS - FCCU NF Freeze Status Register */
12224  FCCU_NFFS_32B_tag NFFS; /* offset: 0x00CC size: 32 bit */
12225  /* FCCU_FAFS - FCCU FA Freeze Status Register */
12226  FCCU_FAFS_32B_tag FAFS; /* offset: 0x00D0 size: 32 bit */
12227  /* FCCU_SCFS - FCCU SC Freeze Status Register */
12228  FCCU_SCFS_32B_tag SCFS; /* offset: 0x00D4 size: 32 bit */
12229  /* FCCU_CFF - FCCU CF Fake Register */
12230  FCCU_CFF_32B_tag CFF; /* offset: 0x00D8 size: 32 bit */
12231  /* FCCU_NCFF - FCCU NCF Fake Register */
12232  FCCU_NCFF_32B_tag NCFF; /* offset: 0x00DC size: 32 bit */
12233  /* FCCU_IRQ_STAT - FCCU IRQ Status Register */
12234  FCCU_IRQ_STAT_32B_tag IRQ_STAT; /* offset: 0x00E0 size: 32 bit */
12235  /* FCCU_IRQ_EN - FCCU IRQ Enable Register */
12236  FCCU_IRQ_EN_32B_tag IRQ_EN; /* offset: 0x00E4 size: 32 bit */
12237  /* FCCU_XTMR - FCCU XTMR Register */
12238  FCCU_XTMR_32B_tag XTMR; /* offset: 0x00E8 size: 32 bit */
12239  /* FCCU_MCS - FCCU MCS Register */
12240  FCCU_MCS_32B_tag MCS; /* offset: 0x00EC size: 32 bit */
12241  } FCCU_tag;
12242 
12243 
12244 #define FCCU (*(volatile FCCU_tag *) 0xFFE6C000UL)
12245 
12246 
12247 
12248 /****************************************************************/
12249 /* */
12250 /* Module: SGENDIG */
12251 /* */
12252 /****************************************************************/
12253 
12254  typedef union { /* SGENDIG_CTRL - SGENDIG Control Register */
12255  vuint32_t R;
12256  struct {
12257  vuint32_t LDOS:1; /* Operation Status */
12258  vuint32_t IOAMPL:5; /* Define the AMPLitude value on I/O pad */
12259  vuint32_t:2;
12260  vuint32_t SEMASK:1; /* Sine wave generator Error MASK interrupt register */
12261  vuint32_t:5;
12262  vuint32_t S0H1:1; /* Operation Status */
12263  vuint32_t PDS:1; /* Operation Status */
12264  vuint32_t IOFREQ:16; /* Define the FREQuency value on I/O pad */
12265  } B;
12266  } SGENDIG_CTRL_32B_tag;
12267 
12268  typedef union { /* SGENDIG_IRQE - SGENDIG Interrupt Request Enable Register */
12269  vuint32_t R;
12270  struct {
12271  vuint32_t:8;
12272  vuint32_t SERR:1; /* Sine wave generator Error bit */
12273  vuint32_t:3;
12274  vuint32_t FERR:1; /* Sine wave generator Force Error bit */
12275  vuint32_t:19;
12276  } B;
12277  } SGENDIG_IRQE_32B_tag;
12278 
12279 
12280 
12281  typedef struct SGENDIG_struct_tag { /* start of SGENDIG_tag */
12282  /* SGENDIG_CTRL - SGENDIG Control Register */
12283  SGENDIG_CTRL_32B_tag CTRL; /* offset: 0x0000 size: 32 bit */
12284  /* SGENDIG_IRQE - SGENDIG Interrupt Request Enable Register */
12285  SGENDIG_IRQE_32B_tag IRQE; /* offset: 0x0004 size: 32 bit */
12286  } SGENDIG_tag;
12287 
12288 
12289 #define SGENDIG (*(volatile SGENDIG_tag *) 0xFFE78000UL)
12290 
12291 
12292 
12293 /****************************************************************/
12294 /* */
12295 /* Module: AIPS */
12296 /* */
12297 /****************************************************************/
12298 
12299  typedef union { /* MPROT - Master Privilege Registers */
12300  vuint32_t R;
12301  struct {
12302  vuint32_t MPROT0_MBW:1; /* Master 0 Buffer Writes */
12303  vuint32_t MPROT0_MTR:1; /* Master 0 Trusted for Reads */
12304  vuint32_t MPROT0_MTW:1; /* Master 0 Trusted for Writes */
12305  vuint32_t MPROT0_MPL:1; /* Master 0 Priviledge Level */
12306  vuint32_t MPROT1_MBW:1; /* Master 1 Buffer Writes */
12307  vuint32_t MPROT1_MTR:1; /* Master 1 Trusted for Reads */
12308  vuint32_t MPROT1_MTW:1; /* Master 1 Trusted for Writes */
12309  vuint32_t MPROT1_MPL:1; /* Master 1 Priviledge Level */
12310  vuint32_t MPROT2_MBW:1; /* Master 2 Buffer Writes */
12311  vuint32_t MPROT2_MTR:1; /* Master 2 Trusted for Reads */
12312  vuint32_t MPROT2_MTW:1; /* Master 2 Trusted for Writes */
12313  vuint32_t MPROT2_MPL:1; /* Master 2 Priviledge Level */
12314  vuint32_t MPROT3_MBW:1; /* Master 3 Buffer Writes */
12315  vuint32_t MPROT3_MTR:1; /* Master 3 Trusted for Reads */
12316  vuint32_t MPROT3_MTW:1; /* Master 3 Trusted for Writes */
12317  vuint32_t MPROT3_MPL:1; /* Master 3 Priviledge Level */
12318  vuint32_t MPROT4_MBW:1; /* Master 4 Buffer Writes */
12319  vuint32_t MPROT4_MTR:1; /* Master 4 Trusted for Reads */
12320  vuint32_t MPROT4_MTW:1; /* Master 4 Trusted for Writes */
12321  vuint32_t MPROT4_MPL:1; /* Master 4 Priviledge Level */
12322  vuint32_t MPROT5_MBW:1; /* Master 5 Buffer Writes */
12323  vuint32_t MPROT5_MTR:1; /* Master 5 Trusted for Reads */
12324  vuint32_t MPROT5_MTW:1; /* Master 5 Trusted for Writes */
12325  vuint32_t MPROT5_MPL:1; /* Master 5 Priviledge Level */
12326  vuint32_t MPROT6_MBW:1; /* Master 6 Buffer Writes */
12327  vuint32_t MPROT6_MTR:1; /* Master 6 Trusted for Reads */
12328  vuint32_t MPROT6_MTW:1; /* Master 6 Trusted for Writes */
12329  vuint32_t MPROT6_MPL:1; /* Master 6 Priviledge Level */
12330  vuint32_t MPROT7_MBW:1; /* Master 7 Buffer Writes */
12331  vuint32_t MPROT7_MTR:1; /* Master 7 Trusted for Reads */
12332  vuint32_t MPROT7_MTW:1; /* Master 7 Trusted for Writes */
12333  vuint32_t MPROT7_MPL:1; /* Master 7 Priviledge Level */
12334  } B;
12335  } AIPS_MPROT_32B_tag;
12336 
12337  typedef union { /* PACR0_7 - Peripheral Access Control Registers */
12338  vuint32_t R;
12339  struct {
12340  vuint32_t PACR0_BW:1; /* Buffer Writes */
12341  vuint32_t PACR0_SP:1; /* Supervisor Protect */
12342  vuint32_t PACR0_WP:1; /* Write Protect */
12343  vuint32_t PACR0_TP:1; /* Trusted Protect */
12344  vuint32_t PACR1_BW:1; /* Buffer Writes */
12345  vuint32_t PACR1_SP:1; /* Supervisor Protect */
12346  vuint32_t PACR1_WP:1; /* Write Protect */
12347  vuint32_t PACR1_TP:1; /* Trusted Protect */
12348  vuint32_t PACR2_BW:1; /* Buffer Writes */
12349  vuint32_t PACR2_SP:1; /* Supervisor Protect */
12350  vuint32_t PACR2_WP:1; /* Write Protect */
12351  vuint32_t PACR2_TP:1; /* Trusted Protect */
12352  vuint32_t PACR3_BW:1; /* Buffer Writes */
12353  vuint32_t PACR3_SP:1; /* Supervisor Protect */
12354  vuint32_t PACR3_WP:1; /* Write Protect */
12355  vuint32_t PACR3_TP:1; /* Trusted Protect */
12356  vuint32_t PACR4_BW:1; /* Buffer Writes */
12357  vuint32_t PACR4_SP:1; /* Supervisor Protect */
12358  vuint32_t PACR4_WP:1; /* Write Protect */
12359  vuint32_t PACR4_TP:1; /* Trusted Protect */
12360  vuint32_t PACR5_BW:1; /* Buffer Writes */
12361  vuint32_t PACR5_SP:1; /* Supervisor Protect */
12362  vuint32_t PACR5_WP:1; /* Write Protect */
12363  vuint32_t PACR5_TP:1; /* Trusted Protect */
12364  vuint32_t PACR6_BW:1; /* Buffer Writes */
12365  vuint32_t PACR6_SP:1; /* Supervisor Protect */
12366  vuint32_t PACR6_WP:1; /* Write Protect */
12367  vuint32_t PACR6_TP:1; /* Trusted Protect */
12368  vuint32_t PACR7_BW:1; /* Buffer Writes */
12369  vuint32_t PACR7_SP:1; /* Supervisor Protect */
12370  vuint32_t PACR7_WP:1; /* Write Protect */
12371  vuint32_t PACR7_TP:1; /* Trusted Protect */
12372  } B;
12373  } AIPS_PACR0_7_32B_tag;
12374 
12375  typedef union { /* PACR8_15 - Peripheral Access Control Registers */
12376  vuint32_t R;
12377  struct {
12378  vuint32_t PACR8_BW:1; /* Buffer Writes */
12379  vuint32_t PACR8_SP:1; /* Supervisor Protect */
12380  vuint32_t PACR8_WP:1; /* Write Protect */
12381  vuint32_t PACR8_TP:1; /* Trusted Protect */
12382  vuint32_t PACR9_BW:1; /* Buffer Writes */
12383  vuint32_t PACR9_SP:1; /* Supervisor Protect */
12384  vuint32_t PACR9_WP:1; /* Write Protect */
12385  vuint32_t PACR9_TP:1; /* Trusted Protect */
12386  vuint32_t PACR10_BW:1; /* Buffer Writes */
12387  vuint32_t PACR10_SP:1; /* Supervisor Protect */
12388  vuint32_t PACR10_WP:1; /* Write Protect */
12389  vuint32_t PACR10_TP:1; /* Trusted Protect */
12390  vuint32_t PACR11_BW:1; /* Buffer Writes */
12391  vuint32_t PACR11_SP:1; /* Supervisor Protect */
12392  vuint32_t PACR11_WP:1; /* Write Protect */
12393  vuint32_t PACR11_TP:1; /* Trusted Protect */
12394  vuint32_t PACR12_BW:1; /* Buffer Writes */
12395  vuint32_t PACR12_SP:1; /* Supervisor Protect */
12396  vuint32_t PACR12_WP:1; /* Write Protect */
12397  vuint32_t PACR12_TP:1; /* Trusted Protect */
12398  vuint32_t PACR13_BW:1; /* Buffer Writes */
12399  vuint32_t PACR13_SP:1; /* Supervisor Protect */
12400  vuint32_t PACR13_WP:1; /* Write Protect */
12401  vuint32_t PACR13_TP:1; /* Trusted Protect */
12402  vuint32_t PACR14_BW:1; /* Buffer Writes */
12403  vuint32_t PACR14_SP:1; /* Supervisor Protect */
12404  vuint32_t PACR14_WP:1; /* Write Protect */
12405  vuint32_t PACR14_TP:1; /* Trusted Protect */
12406  vuint32_t PACR15_BW:1; /* Buffer Writes */
12407  vuint32_t PACR15_SP:1; /* Supervisor Protect */
12408  vuint32_t PACR15_WP:1; /* Write Protect */
12409  vuint32_t PACR15_TP:1; /* Trusted Protect */
12410  } B;
12411  } AIPS_PACR8_15_32B_tag;
12412 
12413  typedef union { /* PACR16_23 - Peripheral Access Control Registers */
12414  vuint32_t R;
12415  struct {
12416  vuint32_t PACR16_BW:1; /* Buffer Writes */
12417  vuint32_t PACR16_SP:1; /* Supervisor Protect */
12418  vuint32_t PACR16_WP:1; /* Write Protect */
12419  vuint32_t PACR16_TP:1; /* Trusted Protect */
12420  vuint32_t PACR17_BW:1; /* Buffer Writes */
12421  vuint32_t PACR17_SP:1; /* Supervisor Protect */
12422  vuint32_t PACR17_WP:1; /* Write Protect */
12423  vuint32_t PACR17_TP:1; /* Trusted Protect */
12424  vuint32_t PACR18_BW:1; /* Buffer Writes */
12425  vuint32_t PACR18_SP:1; /* Supervisor Protect */
12426  vuint32_t PACR18_WP:1; /* Write Protect */
12427  vuint32_t PACR18_TP:1; /* Trusted Protect */
12428  vuint32_t PACR19_BW:1; /* Buffer Writes */
12429  vuint32_t PACR19_SP:1; /* Supervisor Protect */
12430  vuint32_t PACR19_WP:1; /* Write Protect */
12431  vuint32_t PACR19_TP:1; /* Trusted Protect */
12432  vuint32_t PACR20_BW:1; /* Buffer Writes */
12433  vuint32_t PACR20_SP:1; /* Supervisor Protect */
12434  vuint32_t PACR20_WP:1; /* Write Protect */
12435  vuint32_t PACR20_TP:1; /* Trusted Protect */
12436  vuint32_t PACR21_BW:1; /* Buffer Writes */
12437  vuint32_t PACR21_SP:1; /* Supervisor Protect */
12438  vuint32_t PACR21_WP:1; /* Write Protect */
12439  vuint32_t PACR21_TP:1; /* Trusted Protect */
12440  vuint32_t PACR22_BW:1; /* Buffer Writes */
12441  vuint32_t PACR22_SP:1; /* Supervisor Protect */
12442  vuint32_t PACR22_WP:1; /* Write Protect */
12443  vuint32_t PACR22_TP:1; /* Trusted Protect */
12444  vuint32_t PACR23_BW:1; /* Buffer Writes */
12445  vuint32_t PACR23_SP:1; /* Supervisor Protect */
12446  vuint32_t PACR23_WP:1; /* Write Protect */
12447  vuint32_t PACR23_TP:1; /* Trusted Protect */
12448  } B;
12449  } AIPS_PACR16_23_32B_tag;
12450 
12451  typedef union { /* PACR24_31 - Peripheral Access Control Registers */
12452  vuint32_t R;
12453  struct {
12454  vuint32_t PACR24_BW:1; /* Buffer Writes */
12455  vuint32_t PACR24_SP:1; /* Supervisor Protect */
12456  vuint32_t PACR24_WP:1; /* Write Protect */
12457  vuint32_t PACR24_TP:1; /* Trusted Protect */
12458  vuint32_t PACR25_BW:1; /* Buffer Writes */
12459  vuint32_t PACR25_SP:1; /* Supervisor Protect */
12460  vuint32_t PACR25_WP:1; /* Write Protect */
12461  vuint32_t PACR25_TP:1; /* Trusted Protect */
12462  vuint32_t PACR26_BW:1; /* Buffer Writes */
12463  vuint32_t PACR26_SP:1; /* Supervisor Protect */
12464  vuint32_t PACR26_WP:1; /* Write Protect */
12465  vuint32_t PACR26_TP:1; /* Trusted Protect */
12466  vuint32_t PACR27_BW:1; /* Buffer Writes */
12467  vuint32_t PACR27_SP:1; /* Supervisor Protect */
12468  vuint32_t PACR27_WP:1; /* Write Protect */
12469  vuint32_t PACR27_TP:1; /* Trusted Protect */
12470  vuint32_t PACR28_BW:1; /* Buffer Writes */
12471  vuint32_t PACR28_SP:1; /* Supervisor Protect */
12472  vuint32_t PACR28_WP:1; /* Write Protect */
12473  vuint32_t PACR28_TP:1; /* Trusted Protect */
12474  vuint32_t PACR29_BW:1; /* Buffer Writes */
12475  vuint32_t PACR29_SP:1; /* Supervisor Protect */
12476  vuint32_t PACR29_WP:1; /* Write Protect */
12477  vuint32_t PACR29_TP:1; /* Trusted Protect */
12478  vuint32_t PACR30_BW:1; /* Buffer Writes */
12479  vuint32_t PACR30_SP:1; /* Supervisor Protect */
12480  vuint32_t PACR30_WP:1; /* Write Protect */
12481  vuint32_t PACR30_TP:1; /* Trusted Protect */
12482  vuint32_t PACR31_BW:1; /* Buffer Writes */
12483  vuint32_t PACR31_SP:1; /* Supervisor Protect */
12484  vuint32_t PACR31_WP:1; /* Write Protect */
12485  vuint32_t PACR31_TP:1; /* Trusted Protect */
12486  } B;
12487  } AIPS_PACR24_31_32B_tag;
12488 
12489  typedef union { /* OPACR0_7 - Off-Platform Peripheral Access Control Registers */
12490  vuint32_t R;
12491  struct {
12492  vuint32_t OPACR0_BW:1; /* Buffer Writes */
12493  vuint32_t OPACR0_SP:1; /* Supervisor Protect */
12494  vuint32_t OPACR0_WP:1; /* Write Protect */
12495  vuint32_t OPACR0_TP:1; /* Trusted Protect */
12496  vuint32_t OPACR1_BW:1; /* Buffer Writes */
12497  vuint32_t OPACR1_SP:1; /* Supervisor Protect */
12498  vuint32_t OPACR1_WP:1; /* Write Protect */
12499  vuint32_t OPACR1_TP:1; /* Trusted Protect */
12500  vuint32_t OPACR2_BW:1; /* Buffer Writes */
12501  vuint32_t OPACR2_SP:1; /* Supervisor Protect */
12502  vuint32_t OPACR2_WP:1; /* Write Protect */
12503  vuint32_t OPACR2_TP:1; /* Trusted Protect */
12504  vuint32_t OPACR3_BW:1; /* Buffer Writes */
12505  vuint32_t OPACR3_SP:1; /* Supervisor Protect */
12506  vuint32_t OPACR3_WP:1; /* Write Protect */
12507  vuint32_t OPACR3_TP:1; /* Trusted Protect */
12508  vuint32_t OPACR4_BW:1; /* Buffer Writes */
12509  vuint32_t OPACR4_SP:1; /* Supervisor Protect */
12510  vuint32_t OPACR4_WP:1; /* Write Protect */
12511  vuint32_t OPACR4_TP:1; /* Trusted Protect */
12512  vuint32_t OPACR5_BW:1; /* Buffer Writes */
12513  vuint32_t OPACR5_SP:1; /* Supervisor Protect */
12514  vuint32_t OPACR5_WP:1; /* Write Protect */
12515  vuint32_t OPACR5_TP:1; /* Trusted Protect */
12516  vuint32_t OPACR6_BW:1; /* Buffer Writes */
12517  vuint32_t OPACR6_SP:1; /* Supervisor Protect */
12518  vuint32_t OPACR6_WP:1; /* Write Protect */
12519  vuint32_t OPACR6_TP:1; /* Trusted Protect */
12520  vuint32_t OPACR7_BW:1; /* Buffer Writes */
12521  vuint32_t OPACR7_SP:1; /* Supervisor Protect */
12522  vuint32_t OPACR7_WP:1; /* Write Protect */
12523  vuint32_t OPACR7_TP:1; /* Trusted Protect */
12524  } B;
12525  } AIPS_OPACR0_7_32B_tag;
12526 
12527  typedef union { /* OPACR8_15 - Off-Platform Peripheral Access Control Registers */
12528  vuint32_t R;
12529  struct {
12530  vuint32_t OPACR8_BW:1; /* Buffer Writes */
12531  vuint32_t OPACR8_SP:1; /* Supervisor Protect */
12532  vuint32_t OPACR8_WP:1; /* Write Protect */
12533  vuint32_t OPACR8_TP:1; /* Trusted Protect */
12534  vuint32_t OPACR9_BW:1; /* Buffer Writes */
12535  vuint32_t OPACR9_SP:1; /* Supervisor Protect */
12536  vuint32_t OPACR9_WP:1; /* Write Protect */
12537  vuint32_t OPACR9_TP:1; /* Trusted Protect */
12538  vuint32_t OPACR10_BW:1; /* Buffer Writes */
12539  vuint32_t OPACR10_SP:1; /* Supervisor Protect */
12540  vuint32_t OPACR10_WP:1; /* Write Protect */
12541  vuint32_t OPACR10_TP:1; /* Trusted Protect */
12542  vuint32_t OPACR11_BW:1; /* Buffer Writes */
12543  vuint32_t OPACR11_SP:1; /* Supervisor Protect */
12544  vuint32_t OPACR11_WP:1; /* Write Protect */
12545  vuint32_t OPACR11_TP:1; /* Trusted Protect */
12546  vuint32_t OPACR12_BW:1; /* Buffer Writes */
12547  vuint32_t OPACR12_SP:1; /* Supervisor Protect */
12548  vuint32_t OPACR12_WP:1; /* Write Protect */
12549  vuint32_t OPACR12_TP:1; /* Trusted Protect */
12550  vuint32_t OPACR13_BW:1; /* Buffer Writes */
12551  vuint32_t OPACR13_SP:1; /* Supervisor Protect */
12552  vuint32_t OPACR13_WP:1; /* Write Protect */
12553  vuint32_t OPACR13_TP:1; /* Trusted Protect */
12554  vuint32_t OPACR14_BW:1; /* Buffer Writes */
12555  vuint32_t OPACR14_SP:1; /* Supervisor Protect */
12556  vuint32_t OPACR14_WP:1; /* Write Protect */
12557  vuint32_t OPACR14_TP:1; /* Trusted Protect */
12558  vuint32_t OPACR15_BW:1; /* Buffer Writes */
12559  vuint32_t OPACR15_SP:1; /* Supervisor Protect */
12560  vuint32_t OPACR15_WP:1; /* Write Protect */
12561  vuint32_t OPACR15_TP:1; /* Trusted Protect */
12562  } B;
12563  } AIPS_OPACR8_15_32B_tag;
12564 
12565  typedef union { /* OPACR16_23 - Off-Platform Peripheral Access Control Registers */
12566  vuint32_t R;
12567  struct {
12568  vuint32_t OPACR16_BW:1; /* Buffer Writes */
12569  vuint32_t OPACR16_SP:1; /* Supervisor Protect */
12570  vuint32_t OPACR16_WP:1; /* Write Protect */
12571  vuint32_t OPACR16_TP:1; /* Trusted Protect */
12572  vuint32_t OPACR17_BW:1; /* Buffer Writes */
12573  vuint32_t OPACR17_SP:1; /* Supervisor Protect */
12574  vuint32_t OPACR17_WP:1; /* Write Protect */
12575  vuint32_t OPACR17_TP:1; /* Trusted Protect */
12576  vuint32_t OPACR18_BW:1; /* Buffer Writes */
12577  vuint32_t OPACR18_SP:1; /* Supervisor Protect */
12578  vuint32_t OPACR18_WP:1; /* Write Protect */
12579  vuint32_t OPACR18_TP:1; /* Trusted Protect */
12580  vuint32_t OPACR19_BW:1; /* Buffer Writes */
12581  vuint32_t OPACR19_SP:1; /* Supervisor Protect */
12582  vuint32_t OPACR19_WP:1; /* Write Protect */
12583  vuint32_t OPACR19_TP:1; /* Trusted Protect */
12584  vuint32_t OPACR20_BW:1; /* Buffer Writes */
12585  vuint32_t OPACR20_SP:1; /* Supervisor Protect */
12586  vuint32_t OPACR20_WP:1; /* Write Protect */
12587  vuint32_t OPACR20_TP:1; /* Trusted Protect */
12588  vuint32_t OPACR21_BW:1; /* Buffer Writes */
12589  vuint32_t OPACR21_SP:1; /* Supervisor Protect */
12590  vuint32_t OPACR21_WP:1; /* Write Protect */
12591  vuint32_t OPACR21_TP:1; /* Trusted Protect */
12592  vuint32_t OPACR22_BW:1; /* Buffer Writes */
12593  vuint32_t OPACR22_SP:1; /* Supervisor Protect */
12594  vuint32_t OPACR22_WP:1; /* Write Protect */
12595  vuint32_t OPACR22_TP:1; /* Trusted Protect */
12596  vuint32_t OPACR23_BW:1; /* Buffer Writes */
12597  vuint32_t OPACR23_SP:1; /* Supervisor Protect */
12598  vuint32_t OPACR23_WP:1; /* Write Protect */
12599  vuint32_t OPACR23_TP:1; /* Trusted Protect */
12600  } B;
12601  } AIPS_OPACR16_23_32B_tag;
12602 
12603  typedef union { /* OPACR24_31 - Off-Platform Peripheral Access Control Registers */
12604  vuint32_t R;
12605  struct {
12606  vuint32_t OPACR24_BW:1; /* Buffer Writes */
12607  vuint32_t OPACR24_SP:1; /* Supervisor Protect */
12608  vuint32_t OPACR24_WP:1; /* Write Protect */
12609  vuint32_t OPACR24_TP:1; /* Trusted Protect */
12610  vuint32_t OPACR25_BW:1; /* Buffer Writes */
12611  vuint32_t OPACR25_SP:1; /* Supervisor Protect */
12612  vuint32_t OPACR25_WP:1; /* Write Protect */
12613  vuint32_t OPACR25_TP:1; /* Trusted Protect */
12614  vuint32_t OPACR26_BW:1; /* Buffer Writes */
12615  vuint32_t OPACR26_SP:1; /* Supervisor Protect */
12616  vuint32_t OPACR26_WP:1; /* Write Protect */
12617  vuint32_t OPACR26_TP:1; /* Trusted Protect */
12618  vuint32_t OPACR27_BW:1; /* Buffer Writes */
12619  vuint32_t OPACR27_SP:1; /* Supervisor Protect */
12620  vuint32_t OPACR27_WP:1; /* Write Protect */
12621  vuint32_t OPACR27_TP:1; /* Trusted Protect */
12622  vuint32_t OPACR28_BW:1; /* Buffer Writes */
12623  vuint32_t OPACR28_SP:1; /* Supervisor Protect */
12624  vuint32_t OPACR28_WP:1; /* Write Protect */
12625  vuint32_t OPACR28_TP:1; /* Trusted Protect */
12626  vuint32_t OPACR29_BW:1; /* Buffer Writes */
12627  vuint32_t OPACR29_SP:1; /* Supervisor Protect */
12628  vuint32_t OPACR29_WP:1; /* Write Protect */
12629  vuint32_t OPACR29_TP:1; /* Trusted Protect */
12630  vuint32_t OPACR30_BW:1; /* Buffer Writes */
12631  vuint32_t OPACR30_SP:1; /* Supervisor Protect */
12632  vuint32_t OPACR30_WP:1; /* Write Protect */
12633  vuint32_t OPACR30_TP:1; /* Trusted Protect */
12634  vuint32_t OPACR31_BW:1; /* Buffer Writes */
12635  vuint32_t OPACR31_SP:1; /* Supervisor Protect */
12636  vuint32_t OPACR31_WP:1; /* Write Protect */
12637  vuint32_t OPACR31_TP:1; /* Trusted Protect */
12638  } B;
12639  } AIPS_OPACR24_31_32B_tag;
12640 
12641  typedef union { /* OPACR32_39 - Off-Platform Peripheral Access Control Registers */
12642  vuint32_t R;
12643  struct {
12644  vuint32_t OPACR32_BW:1; /* Buffer Writes */
12645  vuint32_t OPACR32_SP:1; /* Supervisor Protect */
12646  vuint32_t OPACR32_WP:1; /* Write Protect */
12647  vuint32_t OPACR32_TP:1; /* Trusted Protect */
12648  vuint32_t OPACR33_BW:1; /* Buffer Writes */
12649  vuint32_t OPACR33_SP:1; /* Supervisor Protect */
12650  vuint32_t OPACR33_WP:1; /* Write Protect */
12651  vuint32_t OPACR33_TP:1; /* Trusted Protect */
12652  vuint32_t OPACR34_BW:1; /* Buffer Writes */
12653  vuint32_t OPACR34_SP:1; /* Supervisor Protect */
12654  vuint32_t OPACR34_WP:1; /* Write Protect */
12655  vuint32_t OPACR34_TP:1; /* Trusted Protect */
12656  vuint32_t OPACR35_BW:1; /* Buffer Writes */
12657  vuint32_t OPACR35_SP:1; /* Supervisor Protect */
12658  vuint32_t OPACR35_WP:1; /* Write Protect */
12659  vuint32_t OPACR35_TP:1; /* Trusted Protect */
12660  vuint32_t OPACR36_BW:1; /* Buffer Writes */
12661  vuint32_t OPACR36_SP:1; /* Supervisor Protect */
12662  vuint32_t OPACR36_WP:1; /* Write Protect */
12663  vuint32_t OPACR36_TP:1; /* Trusted Protect */
12664  vuint32_t OPACR37_BW:1; /* Buffer Writes */
12665  vuint32_t OPACR37_SP:1; /* Supervisor Protect */
12666  vuint32_t OPACR37_WP:1; /* Write Protect */
12667  vuint32_t OPACR37_TP:1; /* Trusted Protect */
12668  vuint32_t OPACR38_BW:1; /* Buffer Writes */
12669  vuint32_t OPACR38_SP:1; /* Supervisor Protect */
12670  vuint32_t OPACR38_WP:1; /* Write Protect */
12671  vuint32_t OPACR38_TP:1; /* Trusted Protect */
12672  vuint32_t OPACR39_BW:1; /* Buffer Writes */
12673  vuint32_t OPACR39_SP:1; /* Supervisor Protect */
12674  vuint32_t OPACR39_WP:1; /* Write Protect */
12675  vuint32_t OPACR39_TP:1; /* Trusted Protect */
12676  } B;
12677  } AIPS_OPACR32_39_32B_tag;
12678 
12679  typedef union { /* OPACR40_47 - Off-Platform Peripheral Access Control Registers */
12680  vuint32_t R;
12681  struct {
12682  vuint32_t OPACR40_BW:1; /* Buffer Writes */
12683  vuint32_t OPACR40_SP:1; /* Supervisor Protect */
12684  vuint32_t OPACR40_WP:1; /* Write Protect */
12685  vuint32_t OPACR40_TP:1; /* Trusted Protect */
12686  vuint32_t OPACR41_BW:1; /* Buffer Writes */
12687  vuint32_t OPACR41_SP:1; /* Supervisor Protect */
12688  vuint32_t OPACR41_WP:1; /* Write Protect */
12689  vuint32_t OPACR41_TP:1; /* Trusted Protect */
12690  vuint32_t OPACR42_BW:1; /* Buffer Writes */
12691  vuint32_t OPACR42_SP:1; /* Supervisor Protect */
12692  vuint32_t OPACR42_WP:1; /* Write Protect */
12693  vuint32_t OPACR42_TP:1; /* Trusted Protect */
12694  vuint32_t OPACR43_BW:1; /* Buffer Writes */
12695  vuint32_t OPACR43_SP:1; /* Supervisor Protect */
12696  vuint32_t OPACR43_WP:1; /* Write Protect */
12697  vuint32_t OPACR43_TP:1; /* Trusted Protect */
12698  vuint32_t OPACR44_BW:1; /* Buffer Writes */
12699  vuint32_t OPACR44_SP:1; /* Supervisor Protect */
12700  vuint32_t OPACR44_WP:1; /* Write Protect */
12701  vuint32_t OPACR44_TP:1; /* Trusted Protect */
12702  vuint32_t OPACR45_BW:1; /* Buffer Writes */
12703  vuint32_t OPACR45_SP:1; /* Supervisor Protect */
12704  vuint32_t OPACR45_WP:1; /* Write Protect */
12705  vuint32_t OPACR45_TP:1; /* Trusted Protect */
12706  vuint32_t OPACR46_BW:1; /* Buffer Writes */
12707  vuint32_t OPACR46_SP:1; /* Supervisor Protect */
12708  vuint32_t OPACR46_WP:1; /* Write Protect */
12709  vuint32_t OPACR46_TP:1; /* Trusted Protect */
12710  vuint32_t OPACR47_BW:1; /* Buffer Writes */
12711  vuint32_t OPACR47_SP:1; /* Supervisor Protect */
12712  vuint32_t OPACR47_WP:1; /* Write Protect */
12713  vuint32_t OPACR47_TP:1; /* Trusted Protect */
12714  } B;
12715  } AIPS_OPACR40_47_32B_tag;
12716 
12717  typedef union { /* OPACR48_55 - Off-Platform Peripheral Access Control Registers */
12718  vuint32_t R;
12719  struct {
12720  vuint32_t OPACR48_BW:1; /* Buffer Writes */
12721  vuint32_t OPACR48_SP:1; /* Supervisor Protect */
12722  vuint32_t OPACR48_WP:1; /* Write Protect */
12723  vuint32_t OPACR48_TP:1; /* Trusted Protect */
12724  vuint32_t OPACR49_BW:1; /* Buffer Writes */
12725  vuint32_t OPACR49_SP:1; /* Supervisor Protect */
12726  vuint32_t OPACR49_WP:1; /* Write Protect */
12727  vuint32_t OPACR49_TP:1; /* Trusted Protect */
12728  vuint32_t OPACR50_BW:1; /* Buffer Writes */
12729  vuint32_t OPACR50_SP:1; /* Supervisor Protect */
12730  vuint32_t OPACR50_WP:1; /* Write Protect */
12731  vuint32_t OPACR50_TP:1; /* Trusted Protect */
12732  vuint32_t OPACR51_BW:1; /* Buffer Writes */
12733  vuint32_t OPACR51_SP:1; /* Supervisor Protect */
12734  vuint32_t OPACR51_WP:1; /* Write Protect */
12735  vuint32_t OPACR51_TP:1; /* Trusted Protect */
12736  vuint32_t OPACR52_BW:1; /* Buffer Writes */
12737  vuint32_t OPACR52_SP:1; /* Supervisor Protect */
12738  vuint32_t OPACR52_WP:1; /* Write Protect */
12739  vuint32_t OPACR52_TP:1; /* Trusted Protect */
12740  vuint32_t OPACR53_BW:1; /* Buffer Writes */
12741  vuint32_t OPACR53_SP:1; /* Supervisor Protect */
12742  vuint32_t OPACR53_WP:1; /* Write Protect */
12743  vuint32_t OPACR53_TP:1; /* Trusted Protect */
12744  vuint32_t OPACR54_BW:1; /* Buffer Writes */
12745  vuint32_t OPACR54_SP:1; /* Supervisor Protect */
12746  vuint32_t OPACR54_WP:1; /* Write Protect */
12747  vuint32_t OPACR54_TP:1; /* Trusted Protect */
12748  vuint32_t OPACR55_BW:1; /* Buffer Writes */
12749  vuint32_t OPACR55_SP:1; /* Supervisor Protect */
12750  vuint32_t OPACR55_WP:1; /* Write Protect */
12751  vuint32_t OPACR55_TP:1; /* Trusted Protect */
12752  } B;
12753  } AIPS_OPACR48_55_32B_tag;
12754 
12755  typedef union { /* OPACR56_63 - Off-Platform Peripheral Access Control Registers */
12756  vuint32_t R;
12757  struct {
12758  vuint32_t OPACR56_BW:1; /* Buffer Writes */
12759  vuint32_t OPACR56_SP:1; /* Supervisor Protect */
12760  vuint32_t OPACR56_WP:1; /* Write Protect */
12761  vuint32_t OPACR56_TP:1; /* Trusted Protect */
12762  vuint32_t OPACR57_BW:1; /* Buffer Writes */
12763  vuint32_t OPACR57_SP:1; /* Supervisor Protect */
12764  vuint32_t OPACR57_WP:1; /* Write Protect */
12765  vuint32_t OPACR57_TP:1; /* Trusted Protect */
12766  vuint32_t OPACR58_BW:1; /* Buffer Writes */
12767  vuint32_t OPACR58_SP:1; /* Supervisor Protect */
12768  vuint32_t OPACR58_WP:1; /* Write Protect */
12769  vuint32_t OPACR58_TP:1; /* Trusted Protect */
12770  vuint32_t OPACR59_BW:1; /* Buffer Writes */
12771  vuint32_t OPACR59_SP:1; /* Supervisor Protect */
12772  vuint32_t OPACR59_WP:1; /* Write Protect */
12773  vuint32_t OPACR59_TP:1; /* Trusted Protect */
12774  vuint32_t OPACR60_BW:1; /* Buffer Writes */
12775  vuint32_t OPACR60_SP:1; /* Supervisor Protect */
12776  vuint32_t OPACR60_WP:1; /* Write Protect */
12777  vuint32_t OPACR60_TP:1; /* Trusted Protect */
12778  vuint32_t OPACR61_BW:1; /* Buffer Writes */
12779  vuint32_t OPACR61_SP:1; /* Supervisor Protect */
12780  vuint32_t OPACR61_WP:1; /* Write Protect */
12781  vuint32_t OPACR61_TP:1; /* Trusted Protect */
12782  vuint32_t OPACR62_BW:1; /* Buffer Writes */
12783  vuint32_t OPACR62_SP:1; /* Supervisor Protect */
12784  vuint32_t OPACR62_WP:1; /* Write Protect */
12785  vuint32_t OPACR62_TP:1; /* Trusted Protect */
12786  vuint32_t OPACR63_BW:1; /* Buffer Writes */
12787  vuint32_t OPACR63_SP:1; /* Supervisor Protect */
12788  vuint32_t OPACR63_WP:1; /* Write Protect */
12789  vuint32_t OPACR63_TP:1; /* Trusted Protect */
12790  } B;
12791  } AIPS_OPACR56_63_32B_tag;
12792 
12793  typedef union { /* OPACR64_71 - Off-Platform Peripheral Access Control Registers */
12794  vuint32_t R;
12795  struct {
12796  vuint32_t OPACR64_BW:1; /* Buffer Writes */
12797  vuint32_t OPACR64_SP:1; /* Supervisor Protect */
12798  vuint32_t OPACR64_WP:1; /* Write Protect */
12799  vuint32_t OPACR64_TP:1; /* Trusted Protect */
12800  vuint32_t OPACR65_BW:1; /* Buffer Writes */
12801  vuint32_t OPACR65_SP:1; /* Supervisor Protect */
12802  vuint32_t OPACR65_WP:1; /* Write Protect */
12803  vuint32_t OPACR65_TP:1; /* Trusted Protect */
12804  vuint32_t OPACR66_BW:1; /* Buffer Writes */
12805  vuint32_t OPACR66_SP:1; /* Supervisor Protect */
12806  vuint32_t OPACR66_WP:1; /* Write Protect */
12807  vuint32_t OPACR66_TP:1; /* Trusted Protect */
12808  vuint32_t OPACR67_BW:1; /* Buffer Writes */
12809  vuint32_t OPACR67_SP:1; /* Supervisor Protect */
12810  vuint32_t OPACR67_WP:1; /* Write Protect */
12811  vuint32_t OPACR67_TP:1; /* Trusted Protect */
12812  vuint32_t OPACR68_BW:1; /* Buffer Writes */
12813  vuint32_t OPACR68_SP:1; /* Supervisor Protect */
12814  vuint32_t OPACR68_WP:1; /* Write Protect */
12815  vuint32_t OPACR68_TP:1; /* Trusted Protect */
12816  vuint32_t OPACR69_BW:1; /* Buffer Writes */
12817  vuint32_t OPACR69_SP:1; /* Supervisor Protect */
12818  vuint32_t OPACR69_WP:1; /* Write Protect */
12819  vuint32_t OPACR69_TP:1; /* Trusted Protect */
12820  vuint32_t OPACR70_BW:1; /* Buffer Writes */
12821  vuint32_t OPACR70_SP:1; /* Supervisor Protect */
12822  vuint32_t OPACR70_WP:1; /* Write Protect */
12823  vuint32_t OPACR70_TP:1; /* Trusted Protect */
12824  vuint32_t OPACR71_BW:1; /* Buffer Writes */
12825  vuint32_t OPACR71_SP:1; /* Supervisor Protect */
12826  vuint32_t OPACR71_WP:1; /* Write Protect */
12827  vuint32_t OPACR71_TP:1; /* Trusted Protect */
12828  } B;
12829  } AIPS_OPACR64_71_32B_tag;
12830 
12831  typedef union { /* OPACR72_79 - Off-Platform Peripheral Access Control Registers */
12832  vuint32_t R;
12833  struct {
12834  vuint32_t OPACR72_BW:1; /* Buffer Writes */
12835  vuint32_t OPACR72_SP:1; /* Supervisor Protect */
12836  vuint32_t OPACR72_WP:1; /* Write Protect */
12837  vuint32_t OPACR72_TP:1; /* Trusted Protect */
12838  vuint32_t OPACR73_BW:1; /* Buffer Writes */
12839  vuint32_t OPACR73_SP:1; /* Supervisor Protect */
12840  vuint32_t OPACR73_WP:1; /* Write Protect */
12841  vuint32_t OPACR73_TP:1; /* Trusted Protect */
12842  vuint32_t OPACR74_BW:1; /* Buffer Writes */
12843  vuint32_t OPACR74_SP:1; /* Supervisor Protect */
12844  vuint32_t OPACR74_WP:1; /* Write Protect */
12845  vuint32_t OPACR74_TP:1; /* Trusted Protect */
12846  vuint32_t OPACR75_BW:1; /* Buffer Writes */
12847  vuint32_t OPACR75_SP:1; /* Supervisor Protect */
12848  vuint32_t OPACR75_WP:1; /* Write Protect */
12849  vuint32_t OPACR75_TP:1; /* Trusted Protect */
12850  vuint32_t OPACR76_BW:1; /* Buffer Writes */
12851  vuint32_t OPACR76_SP:1; /* Supervisor Protect */
12852  vuint32_t OPACR76_WP:1; /* Write Protect */
12853  vuint32_t OPACR76_TP:1; /* Trusted Protect */
12854  vuint32_t OPACR77_BW:1; /* Buffer Writes */
12855  vuint32_t OPACR77_SP:1; /* Supervisor Protect */
12856  vuint32_t OPACR77_WP:1; /* Write Protect */
12857  vuint32_t OPACR77_TP:1; /* Trusted Protect */
12858  vuint32_t OPACR78_BW:1; /* Buffer Writes */
12859  vuint32_t OPACR78_SP:1; /* Supervisor Protect */
12860  vuint32_t OPACR78_WP:1; /* Write Protect */
12861  vuint32_t OPACR78_TP:1; /* Trusted Protect */
12862  vuint32_t OPACR79_BW:1; /* Buffer Writes */
12863  vuint32_t OPACR79_SP:1; /* Supervisor Protect */
12864  vuint32_t OPACR79_WP:1; /* Write Protect */
12865  vuint32_t OPACR79_TP:1; /* Trusted Protect */
12866  } B;
12867  } AIPS_OPACR72_79_32B_tag;
12868 
12869  typedef union { /* OPACR80_87 - Off-Platform Peripheral Access Control Registers */
12870  vuint32_t R;
12871  struct {
12872  vuint32_t OPACR80_BW:1; /* Buffer Writes */
12873  vuint32_t OPACR80_SP:1; /* Supervisor Protect */
12874  vuint32_t OPACR80_WP:1; /* Write Protect */
12875  vuint32_t OPACR80_TP:1; /* Trusted Protect */
12876  vuint32_t OPACR81_BW:1; /* Buffer Writes */
12877  vuint32_t OPACR81_SP:1; /* Supervisor Protect */
12878  vuint32_t OPACR81_WP:1; /* Write Protect */
12879  vuint32_t OPACR81_TP:1; /* Trusted Protect */
12880  vuint32_t OPACR82_BW:1; /* Buffer Writes */
12881  vuint32_t OPACR82_SP:1; /* Supervisor Protect */
12882  vuint32_t OPACR82_WP:1; /* Write Protect */
12883  vuint32_t OPACR82_TP:1; /* Trusted Protect */
12884  vuint32_t OPACR83_BW:1; /* Buffer Writes */
12885  vuint32_t OPACR83_SP:1; /* Supervisor Protect */
12886  vuint32_t OPACR83_WP:1; /* Write Protect */
12887  vuint32_t OPACR83_TP:1; /* Trusted Protect */
12888  vuint32_t OPACR84_BW:1; /* Buffer Writes */
12889  vuint32_t OPACR84_SP:1; /* Supervisor Protect */
12890  vuint32_t OPACR84_WP:1; /* Write Protect */
12891  vuint32_t OPACR84_TP:1; /* Trusted Protect */
12892  vuint32_t OPACR85_BW:1; /* Buffer Writes */
12893  vuint32_t OPACR85_SP:1; /* Supervisor Protect */
12894  vuint32_t OPACR85_WP:1; /* Write Protect */
12895  vuint32_t OPACR85_TP:1; /* Trusted Protect */
12896  vuint32_t OPACR86_BW:1; /* Buffer Writes */
12897  vuint32_t OPACR86_SP:1; /* Supervisor Protect */
12898  vuint32_t OPACR86_WP:1; /* Write Protect */
12899  vuint32_t OPACR86_TP:1; /* Trusted Protect */
12900  vuint32_t OPACR87_BW:1; /* Buffer Writes */
12901  vuint32_t OPACR87_SP:1; /* Supervisor Protect */
12902  vuint32_t OPACR87_WP:1; /* Write Protect */
12903  vuint32_t OPACR87_TP:1; /* Trusted Protect */
12904  } B;
12905  } AIPS_OPACR80_87_32B_tag;
12906 
12907  typedef union { /* OPACR88_95 - Off-Platform Peripheral Access Control Registers */
12908  vuint32_t R;
12909  struct {
12910  vuint32_t OPACR88_BW:1; /* Buffer Writes */
12911  vuint32_t OPACR88_SP:1; /* Supervisor Protect */
12912  vuint32_t OPACR88_WP:1; /* Write Protect */
12913  vuint32_t OPACR88_TP:1; /* Trusted Protect */
12914  vuint32_t OPACR89_BW:1; /* Buffer Writes */
12915  vuint32_t OPACR89_SP:1; /* Supervisor Protect */
12916  vuint32_t OPACR89_WP:1; /* Write Protect */
12917  vuint32_t OPACR89_TP:1; /* Trusted Protect */
12918  vuint32_t OPACR90_BW:1; /* Buffer Writes */
12919  vuint32_t OPACR90_SP:1; /* Supervisor Protect */
12920  vuint32_t OPACR90_WP:1; /* Write Protect */
12921  vuint32_t OPACR90_TP:1; /* Trusted Protect */
12922  vuint32_t OPACR91_BW:1; /* Buffer Writes */
12923  vuint32_t OPACR91_SP:1; /* Supervisor Protect */
12924  vuint32_t OPACR91_WP:1; /* Write Protect */
12925  vuint32_t OPACR91_TP:1; /* Trusted Protect */
12926  vuint32_t OPACR92_BW:1; /* Buffer Writes */
12927  vuint32_t OPACR92_SP:1; /* Supervisor Protect */
12928  vuint32_t OPACR92_WP:1; /* Write Protect */
12929  vuint32_t OPACR92_TP:1; /* Trusted Protect */
12930  vuint32_t OPACR93_BW:1; /* Buffer Writes */
12931  vuint32_t OPACR93_SP:1; /* Supervisor Protect */
12932  vuint32_t OPACR93_WP:1; /* Write Protect */
12933  vuint32_t OPACR93_TP:1; /* Trusted Protect */
12934  vuint32_t OPACR94_BW:1; /* Buffer Writes */
12935  vuint32_t OPACR94_SP:1; /* Supervisor Protect */
12936  vuint32_t OPACR94_WP:1; /* Write Protect */
12937  vuint32_t OPACR94_TP:1; /* Trusted Protect */
12938  vuint32_t OPACR95_BW:1; /* Buffer Writes */
12939  vuint32_t OPACR95_SP:1; /* Supervisor Protect */
12940  vuint32_t OPACR95_WP:1; /* Write Protect */
12941  vuint32_t OPACR95_TP:1; /* Trusted Protect */
12942  } B;
12943  } AIPS_OPACR88_95_32B_tag;
12944 
12945 
12946 
12947  typedef struct AIPS_struct_tag { /* start of AIPS_tag */
12948  /* MPROT - Master Privilege Registers */
12949  AIPS_MPROT_32B_tag MPROT; /* offset: 0x0000 size: 32 bit */
12950  int8_t AIPS_reserved_0004[28];
12951  /* PACR0_7 - Peripheral Access Control Registers */
12952  AIPS_PACR0_7_32B_tag PACR0_7; /* offset: 0x0020 size: 32 bit */
12953  /* PACR8_15 - Peripheral Access Control Registers */
12954  AIPS_PACR8_15_32B_tag PACR8_15; /* offset: 0x0024 size: 32 bit */
12955  /* PACR16_23 - Peripheral Access Control Registers */
12956  AIPS_PACR16_23_32B_tag PACR16_23; /* offset: 0x0028 size: 32 bit */
12957  /* PACR24_31 - Peripheral Access Control Registers */
12958  AIPS_PACR24_31_32B_tag PACR24_31; /* offset: 0x002C size: 32 bit */
12959  int8_t AIPS_reserved_0030[16];
12960  /* OPACR0_7 - Off-Platform Peripheral Access Control Registers */
12961  AIPS_OPACR0_7_32B_tag OPACR0_7; /* offset: 0x0040 size: 32 bit */
12962  /* OPACR8_15 - Off-Platform Peripheral Access Control Registers */
12963  AIPS_OPACR8_15_32B_tag OPACR8_15; /* offset: 0x0044 size: 32 bit */
12964  /* OPACR16_23 - Off-Platform Peripheral Access Control Registers */
12965  AIPS_OPACR16_23_32B_tag OPACR16_23; /* offset: 0x0048 size: 32 bit */
12966  /* OPACR24_31 - Off-Platform Peripheral Access Control Registers */
12967  AIPS_OPACR24_31_32B_tag OPACR24_31; /* offset: 0x004C size: 32 bit */
12968  /* OPACR32_39 - Off-Platform Peripheral Access Control Registers */
12969  AIPS_OPACR32_39_32B_tag OPACR32_39; /* offset: 0x0050 size: 32 bit */
12970  /* OPACR40_47 - Off-Platform Peripheral Access Control Registers */
12971  AIPS_OPACR40_47_32B_tag OPACR40_47; /* offset: 0x0054 size: 32 bit */
12972  /* OPACR48_55 - Off-Platform Peripheral Access Control Registers */
12973  AIPS_OPACR48_55_32B_tag OPACR48_55; /* offset: 0x0058 size: 32 bit */
12974  /* OPACR56_63 - Off-Platform Peripheral Access Control Registers */
12975  AIPS_OPACR56_63_32B_tag OPACR56_63; /* offset: 0x005C size: 32 bit */
12976  /* OPACR64_71 - Off-Platform Peripheral Access Control Registers */
12977  AIPS_OPACR64_71_32B_tag OPACR64_71; /* offset: 0x0060 size: 32 bit */
12978  /* OPACR72_79 - Off-Platform Peripheral Access Control Registers */
12979  AIPS_OPACR72_79_32B_tag OPACR72_79; /* offset: 0x0064 size: 32 bit */
12980  /* OPACR80_87 - Off-Platform Peripheral Access Control Registers */
12981  AIPS_OPACR80_87_32B_tag OPACR80_87; /* offset: 0x0068 size: 32 bit */
12982  /* OPACR88_95 - Off-Platform Peripheral Access Control Registers */
12983  AIPS_OPACR88_95_32B_tag OPACR88_95; /* offset: 0x006C size: 32 bit */
12984  } AIPS_tag;
12985 
12986 
12987 #define AIPS (*(volatile AIPS_tag *) 0xFFF00000UL)
12988 
12989 
12990 
12991 /****************************************************************/
12992 /* */
12993 /* Module: MAX */
12994 /* */
12995 /****************************************************************/
12996 
12997 
12998  /* Register layout for all registers MPR... */
12999 
13000  typedef union { /* Master Priority Register for slave port n */
13001  vuint32_t R;
13002  struct {
13003  vuint32_t:1;
13004  vuint32_t MSTR_7:3; /* Master 7 Priority */
13005  vuint32_t:1;
13006  vuint32_t MSTR_6:3; /* Master 6 Priority */
13007  vuint32_t:1;
13008  vuint32_t MSTR_5:3; /* Master 5 Priority */
13009  vuint32_t:1;
13010  vuint32_t MSTR_4:3; /* Master 4 Priority */
13011  vuint32_t:1;
13012  vuint32_t MSTR_3:3; /* Master 3 Priority */
13013  vuint32_t:1;
13014  vuint32_t MSTR_2:3; /* Master 2 Priority */
13015  vuint32_t:1;
13016  vuint32_t MSTR_1:3; /* Master 1 Priority */
13017  vuint32_t:1;
13018  vuint32_t MSTR_0:3; /* Master 0 Priority */
13019  } B;
13020  } MAX_MPR_32B_tag;
13021 
13022 
13023  /* Register layout for all registers AMPR matches xxx */
13024 
13025 
13026  /* Register layout for all registers SGPCR... */
13027 
13028  typedef union { /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
13029  vuint32_t R;
13030  struct {
13031  vuint32_t RO:1; /* Read Only */
13032  vuint32_t HLP:1; /* Halt Low Priority */
13033  vuint32_t:6;
13034  vuint32_t HPE7:1; /* High Priority Enable */
13035  vuint32_t HPE6:1; /* High Priority Enable */
13036  vuint32_t HPE5:1; /* High Priority Enable */
13037  vuint32_t HPE4:1; /* High Priority Enable */
13038  vuint32_t HPE3:1; /* High Priority Enable */
13039  vuint32_t HPE2:1; /* High Priority Enable */
13040  vuint32_t HPE1:1; /* High Priority Enable */
13041  vuint32_t HPE0:1; /* High Priority Enable */
13042  vuint32_t:6;
13043  vuint32_t ARB:2; /* Arbitration Mode */
13044  vuint32_t:2;
13045  vuint32_t PCTL:2; /* Parking Control */
13046  vuint32_t:1;
13047  vuint32_t PARK:3; /* Park */
13048  } B;
13049  } MAX_SGPCR_32B_tag;
13050 
13051 
13052  /* Register layout for all registers ASGPCR... */
13053 
13054  typedef union { /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
13055  vuint32_t R;
13056  struct {
13057  vuint32_t:1;
13058  vuint32_t HLP:1; /* Halt Low Priority */
13059  vuint32_t:6;
13060  vuint32_t HPE7:1; /* High Priority Enable */
13061  vuint32_t HPE6:1; /* High Priority Enable */
13062  vuint32_t HPE5:1; /* High Priority Enable */
13063  vuint32_t HPE4:1; /* High Priority Enable */
13064  vuint32_t HPE3:1; /* High Priority Enable */
13065  vuint32_t HPE2:1; /* High Priority Enable */
13066  vuint32_t HPE1:1; /* High Priority Enable */
13067  vuint32_t HPE0:1; /* High Priority Enable */
13068  vuint32_t:6;
13069  vuint32_t ARB:2; /* Arbitration Mode */
13070  vuint32_t:2;
13071  vuint32_t PCTL:2; /* Parking Control */
13072  vuint32_t:1;
13073  vuint32_t PARK:3; /* Park */
13074  } B;
13075  } MAX_ASGPCR_32B_tag;
13076 
13077 
13078  /* Register layout for all registers MGPCR... */
13079 
13080  typedef union { /* MAX_MGPCRn - Master General Purpose Control Register n */
13081  vuint32_t R;
13082  struct {
13083  vuint32_t:29;
13084  vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */
13085  } B;
13086  } MAX_MGPCR_32B_tag;
13087 
13088 
13089  typedef struct MAX_SLAVE_PORT_struct_tag {
13090 
13091  /* Master Priority Register for slave port n */
13092  MAX_MPR_32B_tag MPR; /* relative offset: 0x0000 */
13093  /* Alternate Master Priority Register for slave port n */
13094  MAX_MPR_32B_tag AMPR; /* relative offset: 0x0004 */
13095  int8_t MAX_SLAVE_PORT_reserved_0008[8];
13096  /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
13097  MAX_SGPCR_32B_tag SGPCR; /* relative offset: 0x0010 */
13098  /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
13099  MAX_ASGPCR_32B_tag ASGPCR; /* relative offset: 0x0014 */
13100  int8_t MAX_SLAVE_PORT_reserved_0018[232];
13101 
13102  } MAX_SLAVE_PORT_tag;
13103 
13104  typedef struct MAX_MASTER_PORT_struct_tag {
13105 
13106  /* MAX_MGPCRn - Master General Purpose Control Register n */
13107  MAX_MGPCR_32B_tag MGPCR; /* relative offset: 0x0000 */
13108  int8_t MAX_MASTER_PORT_reserved_0004[252];
13109 
13110  } MAX_MASTER_PORT_tag;
13111 
13112 
13113  typedef struct MAX_struct_tag { /* start of MAX_tag */
13114  union {
13115  /* Register set SLAVE_PORT */
13116  MAX_SLAVE_PORT_tag SLAVE_PORT[8]; /* offset: 0x0000 (0x0100 x 8) */
13117 
13118  struct {
13119  /* Master Priority Register for slave port n */
13120  MAX_MPR_32B_tag MPR0; /* offset: 0x0000 size: 32 bit */
13121  /* Alternate Master Priority Register for slave port n */
13122  MAX_MPR_32B_tag AMPR0; /* offset: 0x0004 size: 32 bit */
13123  int8_t MAX_reserved_0008_I1[8];
13124  /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
13125  MAX_SGPCR_32B_tag SGPCR0; /* offset: 0x0010 size: 32 bit */
13126  /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
13127  MAX_ASGPCR_32B_tag ASGPCR0; /* offset: 0x0014 size: 32 bit */
13128  int8_t MAX_reserved_0018_I1[232];
13129  /* Master Priority Register for slave port n */
13130  MAX_MPR_32B_tag MPR1; /* offset: 0x0100 size: 32 bit */
13131  /* Alternate Master Priority Register for slave port n */
13132  MAX_MPR_32B_tag AMPR1; /* offset: 0x0104 size: 32 bit */
13133  int8_t MAX_reserved_0108_I1[8];
13134  /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
13135  MAX_SGPCR_32B_tag SGPCR1; /* offset: 0x0110 size: 32 bit */
13136  /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
13137  MAX_ASGPCR_32B_tag ASGPCR1; /* offset: 0x0114 size: 32 bit */
13138  int8_t MAX_reserved_0118_I1[232];
13139  /* Master Priority Register for slave port n */
13140  MAX_MPR_32B_tag MPR2; /* offset: 0x0200 size: 32 bit */
13141  /* Alternate Master Priority Register for slave port n */
13142  MAX_MPR_32B_tag AMPR2; /* offset: 0x0204 size: 32 bit */
13143  int8_t MAX_reserved_0208_I1[8];
13144  /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
13145  MAX_SGPCR_32B_tag SGPCR2; /* offset: 0x0210 size: 32 bit */
13146  /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
13147  MAX_ASGPCR_32B_tag ASGPCR2; /* offset: 0x0214 size: 32 bit */
13148  int8_t MAX_reserved_0218_I1[232];
13149  /* Master Priority Register for slave port n */
13150  MAX_MPR_32B_tag MPR3; /* offset: 0x0300 size: 32 bit */
13151  /* Alternate Master Priority Register for slave port n */
13152  MAX_MPR_32B_tag AMPR3; /* offset: 0x0304 size: 32 bit */
13153  int8_t MAX_reserved_0308_I1[8];
13154  /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
13155  MAX_SGPCR_32B_tag SGPCR3; /* offset: 0x0310 size: 32 bit */
13156  /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
13157  MAX_ASGPCR_32B_tag ASGPCR3; /* offset: 0x0314 size: 32 bit */
13158  int8_t MAX_reserved_0318_I1[232];
13159  /* Master Priority Register for slave port n */
13160  MAX_MPR_32B_tag MPR4; /* offset: 0x0400 size: 32 bit */
13161  /* Alternate Master Priority Register for slave port n */
13162  MAX_MPR_32B_tag AMPR4; /* offset: 0x0404 size: 32 bit */
13163  int8_t MAX_reserved_0408_I1[8];
13164  /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
13165  MAX_SGPCR_32B_tag SGPCR4; /* offset: 0x0410 size: 32 bit */
13166  /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
13167  MAX_ASGPCR_32B_tag ASGPCR4; /* offset: 0x0414 size: 32 bit */
13168  int8_t MAX_reserved_0418_I1[232];
13169  /* Master Priority Register for slave port n */
13170  MAX_MPR_32B_tag MPR5; /* offset: 0x0500 size: 32 bit */
13171  /* Alternate Master Priority Register for slave port n */
13172  MAX_MPR_32B_tag AMPR5; /* offset: 0x0504 size: 32 bit */
13173  int8_t MAX_reserved_0508_I1[8];
13174  /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
13175  MAX_SGPCR_32B_tag SGPCR5; /* offset: 0x0510 size: 32 bit */
13176  /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
13177  MAX_ASGPCR_32B_tag ASGPCR5; /* offset: 0x0514 size: 32 bit */
13178  int8_t MAX_reserved_0518_I1[232];
13179  /* Master Priority Register for slave port n */
13180  MAX_MPR_32B_tag MPR6; /* offset: 0x0600 size: 32 bit */
13181  /* Alternate Master Priority Register for slave port n */
13182  MAX_MPR_32B_tag AMPR6; /* offset: 0x0604 size: 32 bit */
13183  int8_t MAX_reserved_0608_I1[8];
13184  /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
13185  MAX_SGPCR_32B_tag SGPCR6; /* offset: 0x0610 size: 32 bit */
13186  /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
13187  MAX_ASGPCR_32B_tag ASGPCR6; /* offset: 0x0614 size: 32 bit */
13188  int8_t MAX_reserved_0618_I1[232];
13189  /* Master Priority Register for slave port n */
13190  MAX_MPR_32B_tag MPR7; /* offset: 0x0700 size: 32 bit */
13191  /* Alternate Master Priority Register for slave port n */
13192  MAX_MPR_32B_tag AMPR7; /* offset: 0x0704 size: 32 bit */
13193  int8_t MAX_reserved_0708_I1[8];
13194  /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
13195  MAX_SGPCR_32B_tag SGPCR7; /* offset: 0x0710 size: 32 bit */
13196  /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
13197  MAX_ASGPCR_32B_tag ASGPCR7; /* offset: 0x0714 size: 32 bit */
13198  int8_t MAX_reserved_0718_E1[232];
13199  };
13200 
13201  };
13202  union {
13203  /* Register set MASTER_PORT */
13204  MAX_MASTER_PORT_tag MASTER_PORT[8]; /* offset: 0x0800 (0x0100 x 8) */
13205 
13206  struct {
13207  /* MAX_MGPCRn - Master General Purpose Control Register n */
13208  MAX_MGPCR_32B_tag MGPCR0; /* offset: 0x0800 size: 32 bit */
13209  int8_t MAX_reserved_0804_I1[252];
13210  MAX_MGPCR_32B_tag MGPCR1; /* offset: 0x0900 size: 32 bit */
13211  int8_t MAX_reserved_0904_I1[252];
13212  MAX_MGPCR_32B_tag MGPCR2; /* offset: 0x0A00 size: 32 bit */
13213  int8_t MAX_reserved_0A04_I1[252];
13214  MAX_MGPCR_32B_tag MGPCR3; /* offset: 0x0B00 size: 32 bit */
13215  int8_t MAX_reserved_0B04_I1[252];
13216  MAX_MGPCR_32B_tag MGPCR4; /* offset: 0x0C00 size: 32 bit */
13217  int8_t MAX_reserved_0C04_I1[252];
13218  MAX_MGPCR_32B_tag MGPCR5; /* offset: 0x0D00 size: 32 bit */
13219  int8_t MAX_reserved_0D04_I1[252];
13220  MAX_MGPCR_32B_tag MGPCR6; /* offset: 0x0E00 size: 32 bit */
13221  int8_t MAX_reserved_0E04_I1[252];
13222  MAX_MGPCR_32B_tag MGPCR7; /* offset: 0x0F00 size: 32 bit */
13223  int8_t MAX_reserved_0F04_E1[252];
13224  };
13225 
13226  };
13227  } MAX_tag;
13228 
13229 
13230 #define MAX (*(volatile MAX_tag *) 0xFFF04000UL)
13231 
13232 
13233 
13234 /****************************************************************/
13235 /* */
13236 /* Module: MPU */
13237 /* */
13238 /****************************************************************/
13239 
13240  typedef union { /* MPU_CESR - MPU Control/Error Status Register */
13241  vuint32_t R;
13242  struct {
13243  vuint32_t SPERR:8; /* Slave Port n Error */
13244  vuint32_t:4;
13245  vuint32_t HRL:4; /* Hardware Revision Level */
13246  vuint32_t NSP:4; /* Number of Slave Ports */
13247  vuint32_t NRGD:4; /* Number of Region Descriptors */
13248  vuint32_t:7;
13249  vuint32_t VLD:1; /* Valid bit */
13250  } B;
13251  } MPU_CESR_32B_tag;
13252 
13253 
13254  /* Register layout for all registers EAR... */
13255 
13256  typedef union { /* MPU_EARn - MPU Error Address Register, Slave Port n */
13257  vuint32_t R;
13258  struct {
13259  vuint32_t EADDR:32; /* Error Address */
13260  } B;
13261  } MPU_EAR_32B_tag;
13262 
13263 
13264  /* Register layout for all registers EDR... */
13265 
13266  typedef union { /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
13267  vuint32_t R;
13268  struct {
13269  vuint32_t EACD:16; /* Error Access Control Detail */
13270  vuint32_t EPID:8; /* Error Process Identification */
13271  vuint32_t EMN:4; /* Error Master Number */
13272  vuint32_t EATTR:3; /* Error Attributes */
13273  vuint32_t ERW:1; /* Error Read/Write */
13274  } B;
13275  } MPU_EDR_32B_tag;
13276 
13277 
13278  /* Register layout for all registers RGD_WORD0... */
13279 
13280  typedef union { /* MPU_RGDn_Word0 - MPU Region Descriptor */
13281  vuint32_t R;
13282  struct {
13283  vuint32_t SRTADDR:27; /* Start Address */
13284  vuint32_t:5;
13285  } B;
13286  } MPU_RGD_WORD0_32B_tag;
13287 
13288 
13289  /* Register layout for all registers RGD_WORD1... */
13290 
13291  typedef union { /* MPU_RGDn_Word1 - MPU Region Descriptor */
13292  vuint32_t R;
13293  struct {
13294  vuint32_t ENDADDR:27; /* End Address */
13295  vuint32_t:5;
13296  } B;
13297  } MPU_RGD_WORD1_32B_tag;
13298 
13299 
13300  /* Register layout for all registers RGD_WORD2... */
13301 
13302  typedef union { /* MPU_RGDn_Word2 - MPU Region Descriptor */
13303  vuint32_t R;
13304  struct {
13305  vuint32_t M7RE:1; /* Bus Master 7 Read Enable */
13306  vuint32_t M7WE:1; /* Bus Master 7 Write Enable */
13307  vuint32_t M6RE:1; /* Bus Master 6 Read Enable */
13308  vuint32_t M6WE:1; /* Bus Master 7 Write Enable */
13309  vuint32_t M5RE:1; /* Bus Master 5 Read Enable */
13310  vuint32_t M5WE:1; /* Bus Master 5 Write Enable */
13311  vuint32_t M4RE:1; /* Bus Master 4 Read Enable */
13312  vuint32_t M4WE:1; /* Bus Master 4 Write Enable */
13313  vuint32_t M3PE:1; /* Bus Master 3 Process Identifier Enable */
13314  vuint32_t M3SM:2; /* Bus Master 3 Supervisor Mode Access Control */
13315  vuint32_t M3UM:3; /* Bus Master 3 User Mode Access Control */
13316  vuint32_t M2PE:1; /* Bus Master 2 Process Identifier Enable */
13317  vuint32_t M2SM:2; /* Bus Master 2 Supervisor Mode Access Control */
13318  vuint32_t M2UM:3; /* Bus Master 2 User Mode Access Control */
13319  vuint32_t M1PE:1; /* Bus Master 1 Process Identifier Enable */
13320  vuint32_t M1SM:2; /* Bus Master 1 Supervisor Mode Access Control */
13321  vuint32_t M1UM:3; /* Bus Master 1 User Mode Access Control */
13322  vuint32_t M0PE:1; /* Bus Master 0 Process Identifier Enable */
13323  vuint32_t M0SM:2; /* Bus Master 0 Supervisor Mode Access Control */
13324  vuint32_t M0UM:3; /* Bus Master 0 User Mode Access Control */
13325  } B;
13326  } MPU_RGD_WORD2_32B_tag;
13327 
13328 
13329  /* Register layout for all registers RGD_WORD3... */
13330 
13331  typedef union { /* MPU_RGDn_Word3 - MPU Region Descriptor */
13332  vuint32_t R;
13333  struct {
13334  vuint32_t PID:8; /* Process Identifier */
13335  vuint32_t PIDMASK:8; /* Process Identifier Mask */
13336  vuint32_t:15;
13337  vuint32_t VLD:1; /* Valid */
13338  } B;
13339  } MPU_RGD_WORD3_32B_tag;
13340 
13341 
13342  /* Register layout for all registers RGDAAC... */
13343 
13344  typedef union { /* MPU_RGDAACn - MPU Region Descriptor Alternate Access Control */
13345  vuint32_t R;
13346  struct {
13347  vuint32_t M7RE:1; /* Bus Master 7 Read Enable */
13348  vuint32_t M7WE:1; /* Bus Master 7 Write Enable */
13349  vuint32_t M6RE:1; /* Bus Master 6 Read Enable */
13350  vuint32_t M6WE:1; /* Bus Master 7 Write Enable */
13351  vuint32_t M5RE:1; /* Bus Master 5 Read Enable */
13352  vuint32_t M5WE:1; /* Bus Master 5 Write Enable */
13353  vuint32_t M4RE:1; /* Bus Master 4 Read Enable */
13354  vuint32_t M4WE:1; /* Bus Master 4 Write Enable */
13355  vuint32_t M3PE:1; /* Bus Master 3 Process Identifier Enable */
13356  vuint32_t M3SM:2; /* Bus Master 3 Supervisor Mode Access Control */
13357  vuint32_t M3UM:3; /* Bus Master 3 User Mode Access Control */
13358  vuint32_t M2PE:1; /* Bus Master 2 Process Identifier Enable */
13359  vuint32_t M2SM:2; /* Bus Master 2 Supervisor Mode Access Control */
13360  vuint32_t M2UM:3; /* Bus Master 2 User Mode Access Control */
13361  vuint32_t M1PE:1; /* Bus Master 1 Process Identifier Enable */
13362  vuint32_t M1SM:2; /* Bus Master 1 Supervisor Mode Access Control */
13363  vuint32_t M1UM:3; /* Bus Master 1 User Mode Access Control */
13364  vuint32_t M0PE:1; /* Bus Master 0 Process Identifier Enable */
13365  vuint32_t M0SM:2; /* Bus Master 0 Supervisor Mode Access Control */
13366  vuint32_t M0UM:3; /* Bus Master 0 User Mode Access Control */
13367  } B;
13368  } MPU_RGDAAC_32B_tag;
13369 
13370 
13371  typedef struct MPU_SLAVE_PORT_struct_tag {
13372 
13373  /* MPU_EARn - MPU Error Address Register, Slave Port n */
13374  MPU_EAR_32B_tag EAR; /* relative offset: 0x0000 */
13375  /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
13376  MPU_EDR_32B_tag EDR; /* relative offset: 0x0004 */
13377 
13378  } MPU_SLAVE_PORT_tag;
13379 
13380  typedef struct MPU_REGION_struct_tag {
13381 
13382  /* MPU_RGDn_Word0 - MPU Region Descriptor */
13383  MPU_RGD_WORD0_32B_tag RGD_WORD0; /* relative offset: 0x0000 */
13384  /* MPU_RGDn_Word1 - MPU Region Descriptor */
13385  MPU_RGD_WORD1_32B_tag RGD_WORD1; /* relative offset: 0x0004 */
13386  /* MPU_RGDn_Word2 - MPU Region Descriptor */
13387  MPU_RGD_WORD2_32B_tag RGD_WORD2; /* relative offset: 0x0008 */
13388  /* MPU_RGDn_Word3 - MPU Region Descriptor */
13389  MPU_RGD_WORD3_32B_tag RGD_WORD3; /* relative offset: 0x000C */
13390 
13391  } MPU_REGION_tag;
13392 
13393 
13394  typedef struct MPU_struct_tag { /* start of MPU_tag */
13395  /* MPU_CESR - MPU Control/Error Status Register */
13396  MPU_CESR_32B_tag CESR; /* offset: 0x0000 size: 32 bit */
13397  int8_t MPU_reserved_0004_C[12];
13398  union {
13399  /* Register set SLAVE_PORT */
13400  MPU_SLAVE_PORT_tag SLAVE_PORT[4]; /* offset: 0x0010 (0x0008 x 4) */
13401 
13402  struct {
13403  /* MPU_EARn - MPU Error Address Register, Slave Port n */
13404  MPU_EAR_32B_tag EAR0; /* offset: 0x0010 size: 32 bit */
13405  /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
13406  MPU_EDR_32B_tag EDR0; /* offset: 0x0014 size: 32 bit */
13407  /* MPU_EARn - MPU Error Address Register, Slave Port n */
13408  MPU_EAR_32B_tag EAR1; /* offset: 0x0018 size: 32 bit */
13409  /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
13410  MPU_EDR_32B_tag EDR1; /* offset: 0x001C size: 32 bit */
13411  /* MPU_EARn - MPU Error Address Register, Slave Port n */
13412  MPU_EAR_32B_tag EAR2; /* offset: 0x0020 size: 32 bit */
13413  /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
13414  MPU_EDR_32B_tag EDR2; /* offset: 0x0024 size: 32 bit */
13415  /* MPU_EARn - MPU Error Address Register, Slave Port n */
13416  MPU_EAR_32B_tag EAR3; /* offset: 0x0028 size: 32 bit */
13417  /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
13418  MPU_EDR_32B_tag EDR3; /* offset: 0x002C size: 32 bit */
13419  };
13420 
13421  };
13422  int8_t MPU_reserved_0030_C[976];
13423  union {
13424  /* Register set REGION */
13425  MPU_REGION_tag REGION[16]; /* offset: 0x0400 (0x0010 x 16) */
13426 
13427  struct {
13428  /* MPU_RGDn_Word0 - MPU Region Descriptor */
13429  MPU_RGD_WORD0_32B_tag RGD0_WORD0; /* offset: 0x0400 size: 32 bit */
13430  /* MPU_RGDn_Word1 - MPU Region Descriptor */
13431  MPU_RGD_WORD1_32B_tag RGD0_WORD1; /* offset: 0x0404 size: 32 bit */
13432  /* MPU_RGDn_Word2 - MPU Region Descriptor */
13433  MPU_RGD_WORD2_32B_tag RGD0_WORD2; /* offset: 0x0408 size: 32 bit */
13434  /* MPU_RGDn_Word3 - MPU Region Descriptor */
13435  MPU_RGD_WORD3_32B_tag RGD0_WORD3; /* offset: 0x040C size: 32 bit */
13436  /* MPU_RGDn_Word0 - MPU Region Descriptor */
13437  MPU_RGD_WORD0_32B_tag RGD1_WORD0; /* offset: 0x0410 size: 32 bit */
13438  /* MPU_RGDn_Word1 - MPU Region Descriptor */
13439  MPU_RGD_WORD1_32B_tag RGD1_WORD1; /* offset: 0x0414 size: 32 bit */
13440  /* MPU_RGDn_Word2 - MPU Region Descriptor */
13441  MPU_RGD_WORD2_32B_tag RGD1_WORD2; /* offset: 0x0418 size: 32 bit */
13442  /* MPU_RGDn_Word3 - MPU Region Descriptor */
13443  MPU_RGD_WORD3_32B_tag RGD1_WORD3; /* offset: 0x041C size: 32 bit */
13444  /* MPU_RGDn_Word0 - MPU Region Descriptor */
13445  MPU_RGD_WORD0_32B_tag RGD2_WORD0; /* offset: 0x0420 size: 32 bit */
13446  /* MPU_RGDn_Word1 - MPU Region Descriptor */
13447  MPU_RGD_WORD1_32B_tag RGD2_WORD1; /* offset: 0x0424 size: 32 bit */
13448  /* MPU_RGDn_Word2 - MPU Region Descriptor */
13449  MPU_RGD_WORD2_32B_tag RGD2_WORD2; /* offset: 0x0428 size: 32 bit */
13450  /* MPU_RGDn_Word3 - MPU Region Descriptor */
13451  MPU_RGD_WORD3_32B_tag RGD2_WORD3; /* offset: 0x042C size: 32 bit */
13452  /* MPU_RGDn_Word0 - MPU Region Descriptor */
13453  MPU_RGD_WORD0_32B_tag RGD3_WORD0; /* offset: 0x0430 size: 32 bit */
13454  /* MPU_RGDn_Word1 - MPU Region Descriptor */
13455  MPU_RGD_WORD1_32B_tag RGD3_WORD1; /* offset: 0x0434 size: 32 bit */
13456  /* MPU_RGDn_Word2 - MPU Region Descriptor */
13457  MPU_RGD_WORD2_32B_tag RGD3_WORD2; /* offset: 0x0438 size: 32 bit */
13458  /* MPU_RGDn_Word3 - MPU Region Descriptor */
13459  MPU_RGD_WORD3_32B_tag RGD3_WORD3; /* offset: 0x043C size: 32 bit */
13460  /* MPU_RGDn_Word0 - MPU Region Descriptor */
13461  MPU_RGD_WORD0_32B_tag RGD4_WORD0; /* offset: 0x0440 size: 32 bit */
13462  /* MPU_RGDn_Word1 - MPU Region Descriptor */
13463  MPU_RGD_WORD1_32B_tag RGD4_WORD1; /* offset: 0x0444 size: 32 bit */
13464  /* MPU_RGDn_Word2 - MPU Region Descriptor */
13465  MPU_RGD_WORD2_32B_tag RGD4_WORD2; /* offset: 0x0448 size: 32 bit */
13466  /* MPU_RGDn_Word3 - MPU Region Descriptor */
13467  MPU_RGD_WORD3_32B_tag RGD4_WORD3; /* offset: 0x044C size: 32 bit */
13468  /* MPU_RGDn_Word0 - MPU Region Descriptor */
13469  MPU_RGD_WORD0_32B_tag RGD5_WORD0; /* offset: 0x0450 size: 32 bit */
13470  /* MPU_RGDn_Word1 - MPU Region Descriptor */
13471  MPU_RGD_WORD1_32B_tag RGD5_WORD1; /* offset: 0x0454 size: 32 bit */
13472  /* MPU_RGDn_Word2 - MPU Region Descriptor */
13473  MPU_RGD_WORD2_32B_tag RGD5_WORD2; /* offset: 0x0458 size: 32 bit */
13474  /* MPU_RGDn_Word3 - MPU Region Descriptor */
13475  MPU_RGD_WORD3_32B_tag RGD5_WORD3; /* offset: 0x045C size: 32 bit */
13476  /* MPU_RGDn_Word0 - MPU Region Descriptor */
13477  MPU_RGD_WORD0_32B_tag RGD6_WORD0; /* offset: 0x0460 size: 32 bit */
13478  /* MPU_RGDn_Word1 - MPU Region Descriptor */
13479  MPU_RGD_WORD1_32B_tag RGD6_WORD1; /* offset: 0x0464 size: 32 bit */
13480  /* MPU_RGDn_Word2 - MPU Region Descriptor */
13481  MPU_RGD_WORD2_32B_tag RGD6_WORD2; /* offset: 0x0468 size: 32 bit */
13482  /* MPU_RGDn_Word3 - MPU Region Descriptor */
13483  MPU_RGD_WORD3_32B_tag RGD6_WORD3; /* offset: 0x046C size: 32 bit */
13484  /* MPU_RGDn_Word0 - MPU Region Descriptor */
13485  MPU_RGD_WORD0_32B_tag RGD7_WORD0; /* offset: 0x0470 size: 32 bit */
13486  /* MPU_RGDn_Word1 - MPU Region Descriptor */
13487  MPU_RGD_WORD1_32B_tag RGD7_WORD1; /* offset: 0x0474 size: 32 bit */
13488  /* MPU_RGDn_Word2 - MPU Region Descriptor */
13489  MPU_RGD_WORD2_32B_tag RGD7_WORD2; /* offset: 0x0478 size: 32 bit */
13490  /* MPU_RGDn_Word3 - MPU Region Descriptor */
13491  MPU_RGD_WORD3_32B_tag RGD7_WORD3; /* offset: 0x047C size: 32 bit */
13492  /* MPU_RGDn_Word0 - MPU Region Descriptor */
13493  MPU_RGD_WORD0_32B_tag RGD8_WORD0; /* offset: 0x0480 size: 32 bit */
13494  /* MPU_RGDn_Word1 - MPU Region Descriptor */
13495  MPU_RGD_WORD1_32B_tag RGD8_WORD1; /* offset: 0x0484 size: 32 bit */
13496  /* MPU_RGDn_Word2 - MPU Region Descriptor */
13497  MPU_RGD_WORD2_32B_tag RGD8_WORD2; /* offset: 0x0488 size: 32 bit */
13498  /* MPU_RGDn_Word3 - MPU Region Descriptor */
13499  MPU_RGD_WORD3_32B_tag RGD8_WORD3; /* offset: 0x048C size: 32 bit */
13500  /* MPU_RGDn_Word0 - MPU Region Descriptor */
13501  MPU_RGD_WORD0_32B_tag RGD9_WORD0; /* offset: 0x0490 size: 32 bit */
13502  /* MPU_RGDn_Word1 - MPU Region Descriptor */
13503  MPU_RGD_WORD1_32B_tag RGD9_WORD1; /* offset: 0x0494 size: 32 bit */
13504  /* MPU_RGDn_Word2 - MPU Region Descriptor */
13505  MPU_RGD_WORD2_32B_tag RGD9_WORD2; /* offset: 0x0498 size: 32 bit */
13506  /* MPU_RGDn_Word3 - MPU Region Descriptor */
13507  MPU_RGD_WORD3_32B_tag RGD9_WORD3; /* offset: 0x049C size: 32 bit */
13508  /* MPU_RGDn_Word0 - MPU Region Descriptor */
13509  MPU_RGD_WORD0_32B_tag RGD10_WORD0; /* offset: 0x04A0 size: 32 bit */
13510  /* MPU_RGDn_Word1 - MPU Region Descriptor */
13511  MPU_RGD_WORD1_32B_tag RGD10_WORD1; /* offset: 0x04A4 size: 32 bit */
13512  /* MPU_RGDn_Word2 - MPU Region Descriptor */
13513  MPU_RGD_WORD2_32B_tag RGD10_WORD2; /* offset: 0x04A8 size: 32 bit */
13514  /* MPU_RGDn_Word3 - MPU Region Descriptor */
13515  MPU_RGD_WORD3_32B_tag RGD10_WORD3; /* offset: 0x04AC size: 32 bit */
13516  /* MPU_RGDn_Word0 - MPU Region Descriptor */
13517  MPU_RGD_WORD0_32B_tag RGD11_WORD0; /* offset: 0x04B0 size: 32 bit */
13518  /* MPU_RGDn_Word1 - MPU Region Descriptor */
13519  MPU_RGD_WORD1_32B_tag RGD11_WORD1; /* offset: 0x04B4 size: 32 bit */
13520  /* MPU_RGDn_Word2 - MPU Region Descriptor */
13521  MPU_RGD_WORD2_32B_tag RGD11_WORD2; /* offset: 0x04B8 size: 32 bit */
13522  /* MPU_RGDn_Word3 - MPU Region Descriptor */
13523  MPU_RGD_WORD3_32B_tag RGD11_WORD3; /* offset: 0x04BC size: 32 bit */
13524  /* MPU_RGDn_Word0 - MPU Region Descriptor */
13525  MPU_RGD_WORD0_32B_tag RGD12_WORD0; /* offset: 0x04C0 size: 32 bit */
13526  /* MPU_RGDn_Word1 - MPU Region Descriptor */
13527  MPU_RGD_WORD1_32B_tag RGD12_WORD1; /* offset: 0x04C4 size: 32 bit */
13528  /* MPU_RGDn_Word2 - MPU Region Descriptor */
13529  MPU_RGD_WORD2_32B_tag RGD12_WORD2; /* offset: 0x04C8 size: 32 bit */
13530  /* MPU_RGDn_Word3 - MPU Region Descriptor */
13531  MPU_RGD_WORD3_32B_tag RGD12_WORD3; /* offset: 0x04CC size: 32 bit */
13532  /* MPU_RGDn_Word0 - MPU Region Descriptor */
13533  MPU_RGD_WORD0_32B_tag RGD13_WORD0; /* offset: 0x04D0 size: 32 bit */
13534  /* MPU_RGDn_Word1 - MPU Region Descriptor */
13535  MPU_RGD_WORD1_32B_tag RGD13_WORD1; /* offset: 0x04D4 size: 32 bit */
13536  /* MPU_RGDn_Word2 - MPU Region Descriptor */
13537  MPU_RGD_WORD2_32B_tag RGD13_WORD2; /* offset: 0x04D8 size: 32 bit */
13538  /* MPU_RGDn_Word3 - MPU Region Descriptor */
13539  MPU_RGD_WORD3_32B_tag RGD13_WORD3; /* offset: 0x04DC size: 32 bit */
13540  /* MPU_RGDn_Word0 - MPU Region Descriptor */
13541  MPU_RGD_WORD0_32B_tag RGD14_WORD0; /* offset: 0x04E0 size: 32 bit */
13542  /* MPU_RGDn_Word1 - MPU Region Descriptor */
13543  MPU_RGD_WORD1_32B_tag RGD14_WORD1; /* offset: 0x04E4 size: 32 bit */
13544  /* MPU_RGDn_Word2 - MPU Region Descriptor */
13545  MPU_RGD_WORD2_32B_tag RGD14_WORD2; /* offset: 0x04E8 size: 32 bit */
13546  /* MPU_RGDn_Word3 - MPU Region Descriptor */
13547  MPU_RGD_WORD3_32B_tag RGD14_WORD3; /* offset: 0x04EC size: 32 bit */
13548  /* MPU_RGDn_Word0 - MPU Region Descriptor */
13549  MPU_RGD_WORD0_32B_tag RGD15_WORD0; /* offset: 0x04F0 size: 32 bit */
13550  /* MPU_RGDn_Word1 - MPU Region Descriptor */
13551  MPU_RGD_WORD1_32B_tag RGD15_WORD1; /* offset: 0x04F4 size: 32 bit */
13552  /* MPU_RGDn_Word2 - MPU Region Descriptor */
13553  MPU_RGD_WORD2_32B_tag RGD15_WORD2; /* offset: 0x04F8 size: 32 bit */
13554  /* MPU_RGDn_Word3 - MPU Region Descriptor */
13555  MPU_RGD_WORD3_32B_tag RGD15_WORD3; /* offset: 0x04FC size: 32 bit */
13556  };
13557 
13558  };
13559  int8_t MPU_reserved_0500_C[768];
13560  union {
13561  /* MPU_RGDAACn - MPU Region Descriptor Alternate Access Control */
13562  MPU_RGDAAC_32B_tag RGDAAC[16]; /* offset: 0x0800 (0x0004 x 16) */
13563 
13564  struct {
13565  /* MPU_RGDAACn - MPU Region Descriptor Alternate Access Control */
13566  MPU_RGDAAC_32B_tag RGDAAC0; /* offset: 0x0800 size: 32 bit */
13567  MPU_RGDAAC_32B_tag RGDAAC1; /* offset: 0x0804 size: 32 bit */
13568  MPU_RGDAAC_32B_tag RGDAAC2; /* offset: 0x0808 size: 32 bit */
13569  MPU_RGDAAC_32B_tag RGDAAC3; /* offset: 0x080C size: 32 bit */
13570  MPU_RGDAAC_32B_tag RGDAAC4; /* offset: 0x0810 size: 32 bit */
13571  MPU_RGDAAC_32B_tag RGDAAC5; /* offset: 0x0814 size: 32 bit */
13572  MPU_RGDAAC_32B_tag RGDAAC6; /* offset: 0x0818 size: 32 bit */
13573  MPU_RGDAAC_32B_tag RGDAAC7; /* offset: 0x081C size: 32 bit */
13574  MPU_RGDAAC_32B_tag RGDAAC8; /* offset: 0x0820 size: 32 bit */
13575  MPU_RGDAAC_32B_tag RGDAAC9; /* offset: 0x0824 size: 32 bit */
13576  MPU_RGDAAC_32B_tag RGDAAC10; /* offset: 0x0828 size: 32 bit */
13577  MPU_RGDAAC_32B_tag RGDAAC11; /* offset: 0x082C size: 32 bit */
13578  MPU_RGDAAC_32B_tag RGDAAC12; /* offset: 0x0830 size: 32 bit */
13579  MPU_RGDAAC_32B_tag RGDAAC13; /* offset: 0x0834 size: 32 bit */
13580  MPU_RGDAAC_32B_tag RGDAAC14; /* offset: 0x0838 size: 32 bit */
13581  MPU_RGDAAC_32B_tag RGDAAC15; /* offset: 0x083C size: 32 bit */
13582  };
13583 
13584  };
13585  } MPU_tag;
13586 
13587 
13588 #define MPU (*(volatile MPU_tag *) 0xFFF10000UL)
13589 
13590 
13591 
13592 /****************************************************************/
13593 /* */
13594 /* Module: SEMA4 */
13595 /* */
13596 /****************************************************************/
13597 
13598 
13599  /* Register layout for all registers GATE... */
13600 
13601  typedef union { /* SEMA4_GATEn - Semephores Gate Register */
13602  vuint8_t R;
13603  struct {
13604  vuint8_t:6;
13605  vuint8_t GTFSM:2; /* Gate Finite State machine */
13606  } B;
13607  } SEMA4_GATE_8B_tag;
13608 
13609  typedef union { /* SEMA4_CP0INE - Semaphores Processor IRQ Notification Enable */
13610  vuint16_t R;
13611  struct {
13612  vuint16_t INE:16; /* Interrupt Request Notification Enable */
13613  } B;
13614  } SEMA4_CP0INE_16B_tag;
13615 
13616  typedef union { /* SEMA4_CP1INE - Semaphores Processor IRQ Notification Enable */
13617  vuint16_t R;
13618  struct {
13619  vuint16_t INE:16; /* Interrupt Request Notification Enable */
13620  } B;
13621  } SEMA4_CP1INE_16B_tag;
13622 
13623  typedef union { /* SEMA4_CP0NTF - Semaphores Processor IRQ Notification */
13624  vuint16_t R;
13625  struct {
13626  vuint16_t GN:16; /* Gate 0 Notification */
13627  } B;
13628  } SEMA4_CP0NTF_16B_tag;
13629 
13630  typedef union { /* SEMA4_CP1NTF - Semaphores Processor IRQ Notification */
13631  vuint16_t R;
13632  struct {
13633  vuint16_t GN:16; /* Gate 1 Notification */
13634  } B;
13635  } SEMA4_CP1NTF_16B_tag;
13636 
13637  typedef union { /* SEMA4_RSTGT - Semaphores Reset Gate */
13638  vuint16_t R;
13639  struct {
13640  vuint16_t:2;
13641  vuint16_t RSTGSM:2; /* Reset Gate Finite State Machine */
13642  vuint16_t RSTGDP:7; /* Reset Gate Data Pattern */
13643  vuint16_t RSTGMS:3; /* Reset Gate Bus Master */
13644  vuint16_t RSTGTN:8; /* Reset Gate Number */
13645  } B;
13646  } SEMA4_RSTGT_16B_tag;
13647 
13648  typedef union { /* SEMA4_RSTNTF - Semaphores Reset Reset IRQ Notification */
13649  vuint16_t R;
13650  struct {
13651  vuint16_t:2;
13652  vuint16_t RSTNSM:2; /* Reset Gate Finite State Machine */
13653  vuint16_t RSTNDP:7; /* Reset Gate Data Pattern */
13654  vuint16_t RSTNMS:3; /* Reset Gate Bus Master */
13655  vuint16_t RSTNTN:8; /* Reset Gate Number */
13656  } B;
13657  } SEMA4_RSTNTF_16B_tag;
13658 
13659 
13660 
13661  typedef struct SEMA4_struct_tag { /* start of SEMA4_tag */
13662  union {
13663  /* SEMA4_GATEn - Semephores Gate Register */
13664  SEMA4_GATE_8B_tag GATE[16]; /* offset: 0x0000 (0x0001 x 16) */
13665 
13666  struct {
13667  /* SEMA4_GATEn - Semephores Gate Register */
13668  SEMA4_GATE_8B_tag GATE0; /* offset: 0x0000 size: 8 bit */
13669  SEMA4_GATE_8B_tag GATE1; /* offset: 0x0001 size: 8 bit */
13670  SEMA4_GATE_8B_tag GATE2; /* offset: 0x0002 size: 8 bit */
13671  SEMA4_GATE_8B_tag GATE3; /* offset: 0x0003 size: 8 bit */
13672  SEMA4_GATE_8B_tag GATE4; /* offset: 0x0004 size: 8 bit */
13673  SEMA4_GATE_8B_tag GATE5; /* offset: 0x0005 size: 8 bit */
13674  SEMA4_GATE_8B_tag GATE6; /* offset: 0x0006 size: 8 bit */
13675  SEMA4_GATE_8B_tag GATE7; /* offset: 0x0007 size: 8 bit */
13676  SEMA4_GATE_8B_tag GATE8; /* offset: 0x0008 size: 8 bit */
13677  SEMA4_GATE_8B_tag GATE9; /* offset: 0x0009 size: 8 bit */
13678  SEMA4_GATE_8B_tag GATE10; /* offset: 0x000A size: 8 bit */
13679  SEMA4_GATE_8B_tag GATE11; /* offset: 0x000B size: 8 bit */
13680  SEMA4_GATE_8B_tag GATE12; /* offset: 0x000C size: 8 bit */
13681  SEMA4_GATE_8B_tag GATE13; /* offset: 0x000D size: 8 bit */
13682  SEMA4_GATE_8B_tag GATE14; /* offset: 0x000E size: 8 bit */
13683  SEMA4_GATE_8B_tag GATE15; /* offset: 0x000F size: 8 bit */
13684  };
13685 
13686  };
13687  int8_t SEMA4_reserved_0010[48];
13688  /* SEMA4_CP0INE - Semaphores Processor IRQ Notification Enable */
13689  SEMA4_CP0INE_16B_tag CP0INE; /* offset: 0x0040 size: 16 bit */
13690  int8_t SEMA4_reserved_0042[6];
13691  /* SEMA4_CP1INE - Semaphores Processor IRQ Notification Enable */
13692  SEMA4_CP1INE_16B_tag CP1INE; /* offset: 0x0048 size: 16 bit */
13693  int8_t SEMA4_reserved_004A[54];
13694  /* SEMA4_CP0NTF - Semaphores Processor IRQ Notification */
13695  SEMA4_CP0NTF_16B_tag CP0NTF; /* offset: 0x0080 size: 16 bit */
13696  int8_t SEMA4_reserved_0082[6];
13697  /* SEMA4_CP1NTF - Semaphores Processor IRQ Notification */
13698  SEMA4_CP1NTF_16B_tag CP1NTF; /* offset: 0x0088 size: 16 bit */
13699  int8_t SEMA4_reserved_008A[118];
13700  /* SEMA4_RSTGT - Semaphores Reset Gate */
13701  SEMA4_RSTGT_16B_tag RSTGT; /* offset: 0x0100 size: 16 bit */
13702  int8_t SEMA4_reserved_0102[2];
13703  /* SEMA4_RSTNTF - Semaphores Reset Reset IRQ Notification */
13704  SEMA4_RSTNTF_16B_tag RSTNTF; /* offset: 0x0104 size: 16 bit */
13705  } SEMA4_tag;
13706 
13707 
13708 #define SEMA4 (*(volatile SEMA4_tag *) 0xFFF24000UL)
13709 
13710 
13711 
13712 /****************************************************************/
13713 /* */
13714 /* Module: SWT */
13715 /* */
13716 /****************************************************************/
13717 
13718  typedef union { /* SWT_CR - Control Register */
13719  vuint32_t R;
13720  struct {
13721  vuint32_t MAP0:1; /* Master Acces Protection for Master 0 */
13722  vuint32_t MAP1:1; /* Master Acces Protection for Master 1 */
13723  vuint32_t MAP2:1; /* Master Acces Protection for Master 2 */
13724  vuint32_t MAP3:1; /* Master Acces Protection for Master 3 */
13725  vuint32_t MAP4:1; /* Master Acces Protection for Master 4 */
13726  vuint32_t MAP5:1; /* Master Acces Protection for Master 5 */
13727  vuint32_t MAP6:1; /* Master Acces Protection for Master 6 */
13728  vuint32_t MAP7:1; /* Master Acces Protection for Master 7 */
13729  vuint32_t:14;
13730  vuint32_t KEY:1; /* Keyed Service Mode */
13731  vuint32_t RIA:1; /* Reset on Invalid Access */
13732  vuint32_t WND:1; /* Window Mode */
13733  vuint32_t ITR:1; /* Interrupt Then Reset */
13734  vuint32_t HLK:1; /* Hard Lock */
13735  vuint32_t SLK:1; /* Soft Lock */
13736  vuint32_t CSL:1; /* Clock Selection */
13737  vuint32_t STP:1; /* Stop Mode Control */
13738  vuint32_t FRZ:1; /* Debug Mode Control */
13739  vuint32_t WEN:1; /* Watchdog Enabled */
13740  } B;
13741  } SWT_CR_32B_tag;
13742 
13743  typedef union { /* SWT_IR - SWT Interrupt Register */
13744  vuint32_t R;
13745  struct {
13746  vuint32_t:31;
13747  vuint32_t TIF:1; /* Time Out Interrupt Flag */
13748  } B;
13749  } SWT_IR_32B_tag;
13750 
13751  typedef union { /* SWT_TO - SWT Time-Out Register */
13752  vuint32_t R;
13753  struct {
13754  vuint32_t WTO:32; /* Watchdog Time Out Period */
13755  } B;
13756  } SWT_TO_32B_tag;
13757 
13758  typedef union { /* SWT_WN - SWT Window Register */
13759  vuint32_t R;
13760  struct {
13761  vuint32_t WST:32; /* Watchdog Time Out Period */
13762  } B;
13763  } SWT_WN_32B_tag;
13764 
13765  typedef union { /* SWT_SR - SWT Service Register */
13766  vuint32_t R;
13767  struct {
13768  vuint32_t:16;
13769  vuint32_t WSC:16; /* Watchdog Service Code */
13770  } B;
13771  } SWT_SR_32B_tag;
13772 
13773  typedef union { /* SWT_CO - SWT Counter Output Register */
13774  vuint32_t R;
13775  struct {
13776  vuint32_t CNT:32; /* Watchdog Count */
13777  } B;
13778  } SWT_CO_32B_tag;
13779 
13780  typedef union { /* SWT_SK - SWT Service Key Register */
13781  vuint32_t R;
13782  struct {
13783  vuint32_t:16;
13784  vuint32_t SERVICEKEY:16; /* Service Key */
13785  } B;
13786  } SWT_SK_32B_tag;
13787 
13788 
13789 
13790  typedef struct SWT_struct_tag { /* start of SWT_tag */
13791  /* SWT_CR - Control Register */
13792  SWT_CR_32B_tag CR; /* offset: 0x0000 size: 32 bit */
13793  /* SWT_IR - SWT Interrupt Register */
13794  SWT_IR_32B_tag IR; /* offset: 0x0004 size: 32 bit */
13795  /* SWT_TO - SWT Time-Out Register */
13796  SWT_TO_32B_tag TO; /* offset: 0x0008 size: 32 bit */
13797  /* SWT_WN - SWT Window Register */
13798  SWT_WN_32B_tag WN; /* offset: 0x000C size: 32 bit */
13799  /* SWT_SR - SWT Service Register */
13800  SWT_SR_32B_tag SR; /* offset: 0x0010 size: 32 bit */
13801  /* SWT_CO - SWT Counter Output Register */
13802  SWT_CO_32B_tag CO; /* offset: 0x0014 size: 32 bit */
13803  /* SWT_SK - SWT Service Key Register */
13804  SWT_SK_32B_tag SK; /* offset: 0x0018 size: 32 bit */
13805  } SWT_tag;
13806 
13807 
13808 #define SWT (*(volatile SWT_tag *) 0xFFF38000UL)
13809 
13810 
13811 
13812 /****************************************************************/
13813 /* */
13814 /* Module: STM */
13815 /* */
13816 /****************************************************************/
13817 
13818  typedef union { /* STM_CR - Control Register */
13819  vuint32_t R;
13820  struct {
13821  vuint32_t:16;
13822  vuint32_t CPS:8; /* Counter Prescaler */
13823  vuint32_t:6;
13824  vuint32_t FRZ:1; /* Freeze Control */
13825  vuint32_t TEN:1; /* Timer Counter Enabled */
13826  } B;
13827  } STM_CR_32B_tag;
13828 
13829  typedef union { /* STM_CNT - STM Count Register */
13830  vuint32_t R;
13831  } STM_CNT_32B_tag;
13832 
13833 
13834  /* Register layout for all registers CCR... */
13835 
13836  typedef union { /* STM_CCRn - STM Channel Control Register */
13837  vuint32_t R;
13838  struct {
13839  vuint32_t:31;
13840  vuint32_t CEN:1; /* Channel Enable */
13841  } B;
13842  } STM_CCR_32B_tag;
13843 
13844 
13845  /* Register layout for all registers CIR... */
13846 
13847  typedef union { /* STM_CIRn - STM Channel Interrupt Register */
13848  vuint32_t R;
13849  struct {
13850  vuint32_t:31;
13851  vuint32_t CIF:1; /* Channel Interrupt Flag */
13852  } B;
13853  } STM_CIR_32B_tag;
13854 
13855 
13856  /* Register layout for all registers CMP... */
13857 
13858  typedef union { /* STM_CMPn - STM Channel Compare Register */
13859  vuint32_t R;
13860  } STM_CMP_32B_tag;
13861 
13862 
13863  typedef struct STM_CHANNEL_struct_tag {
13864 
13865  /* STM_CCRn - STM Channel Control Register */
13866  STM_CCR_32B_tag CCR; /* relative offset: 0x0000 */
13867  /* STM_CIRn - STM Channel Interrupt Register */
13868  STM_CIR_32B_tag CIR; /* relative offset: 0x0004 */
13869  /* STM_CMPn - STM Channel Compare Register */
13870  STM_CMP_32B_tag CMP; /* relative offset: 0x0008 */
13871  int8_t STM_CHANNEL_reserved_000C[4];
13872 
13873  } STM_CHANNEL_tag;
13874 
13875 
13876  typedef struct STM_struct_tag { /* start of STM_tag */
13877  union {
13878  STM_CR_32B_tag CR0; /* deprecated - please avoid */
13879 
13880  /* STM_CR - Control Register */
13881  STM_CR_32B_tag CR; /* offset: 0x0000 size: 32 bit */
13882 
13883  };
13884  union {
13885  STM_CNT_32B_tag CNT0; /* deprecated - please avoid */
13886 
13887  /* STM_CNT - STM Count Register */
13888  STM_CNT_32B_tag CNT; /* offset: 0x0004 size: 32 bit */
13889 
13890  };
13891  int8_t STM_reserved_0008_C[8];
13892  union {
13893  /* Register set CHANNEL */
13894  STM_CHANNEL_tag CHANNEL[4]; /* offset: 0x0010 (0x0010 x 4) */
13895 
13896  struct {
13897  /* STM_CCRn - STM Channel Control Register */
13898  STM_CCR_32B_tag CCR0; /* offset: 0x0010 size: 32 bit */
13899  /* STM_CIRn - STM Channel Interrupt Register */
13900  STM_CIR_32B_tag CIR0; /* offset: 0x0014 size: 32 bit */
13901  /* STM_CMPn - STM Channel Compare Register */
13902  STM_CMP_32B_tag CMP0; /* offset: 0x0018 size: 32 bit */
13903  int8_t STM_reserved_001C_I1[4];
13904  /* STM_CCRn - STM Channel Control Register */
13905  STM_CCR_32B_tag CCR1; /* offset: 0x0020 size: 32 bit */
13906  /* STM_CIRn - STM Channel Interrupt Register */
13907  STM_CIR_32B_tag CIR1; /* offset: 0x0024 size: 32 bit */
13908  /* STM_CMPn - STM Channel Compare Register */
13909  STM_CMP_32B_tag CMP1; /* offset: 0x0028 size: 32 bit */
13910  int8_t STM_reserved_002C_I1[4];
13911  /* STM_CCRn - STM Channel Control Register */
13912  STM_CCR_32B_tag CCR2; /* offset: 0x0030 size: 32 bit */
13913  /* STM_CIRn - STM Channel Interrupt Register */
13914  STM_CIR_32B_tag CIR2; /* offset: 0x0034 size: 32 bit */
13915  /* STM_CMPn - STM Channel Compare Register */
13916  STM_CMP_32B_tag CMP2; /* offset: 0x0038 size: 32 bit */
13917  int8_t STM_reserved_003C_I1[4];
13918  /* STM_CCRn - STM Channel Control Register */
13919  STM_CCR_32B_tag CCR3; /* offset: 0x0040 size: 32 bit */
13920  /* STM_CIRn - STM Channel Interrupt Register */
13921  STM_CIR_32B_tag CIR3; /* offset: 0x0044 size: 32 bit */
13922  /* STM_CMPn - STM Channel Compare Register */
13923  STM_CMP_32B_tag CMP3; /* offset: 0x0048 size: 32 bit */
13924  int8_t STM_reserved_004C_E1[4];
13925  };
13926 
13927  };
13928  } STM_tag;
13929 
13930 
13931 #define STM (*(volatile STM_tag *) 0xFFF3C000UL)
13932 
13933 
13934 
13935 /****************************************************************/
13936 /* */
13937 /* Module: SPP_MCM */
13938 /* */
13939 /****************************************************************/
13940 
13941  typedef union { /* SPP_MCM_PCT - Processor Core Type */
13942  vuint16_t R;
13943  struct {
13944  vuint16_t PCTYPE:16; /* Processor Core Type */
13945  } B;
13946  } SPP_MCM_PCT_16B_tag;
13947 
13948  typedef union { /* SPP_MCM_PLREV - SOC-Defined Platform Revision */
13949  vuint16_t R;
13950  struct {
13951  vuint16_t PLREVISION:16; /* Platform Revision */
13952  } B;
13953  } SPP_MCM_PLREV_16B_tag;
13954 
13955  typedef union { /* SPP_MCM_IOPMC - IPS On-Platform Module Configuration */
13956  vuint32_t R;
13957  struct {
13958  vuint32_t PMC:32; /* IPS Module Configuration */
13959  } B;
13960  } SPP_MCM_IOPMC_32B_tag;
13961 
13962  typedef union { /* SPP_MCM_MRSR - Miscellaneous Reset Status Register */
13963  vuint8_t R;
13964  struct {
13965  vuint8_t POR:1; /* Power on Reset */
13966 #ifndef USE_FIELD_ALIASES_SPP_MCM
13967  vuint8_t OFPLR:1; /* Off-Platform Reset */
13968 #else
13969  vuint8_t DIR:1; /* deprecated name - please avoid */
13970 #endif
13971  vuint8_t:6;
13972  } B;
13973  } SPP_MCM_MRSR_8B_tag;
13974 
13975  typedef union { /* SPP_MCM_MWCR - Miscellaneous Wakeup Control Register */
13976  vuint8_t R;
13977  struct {
13978  vuint8_t ENBWCR:1; /* Enable WCR */
13979  vuint8_t:3;
13980  vuint8_t PRILVL:4; /* Interrupt Priority Level */
13981  } B;
13982  } SPP_MCM_MWCR_8B_tag;
13983 
13984  typedef union { /* SPP_MCM_MIR - Miscellaneous Interrupt Register */
13985  vuint8_t R;
13986  struct {
13987  vuint8_t FB0AI:1; /* Flash Bank 0 Abort Interrupt */
13988  vuint8_t FB0SI:1; /* Flash Bank 0 Stall Interrupt */
13989  vuint8_t FB1AI:1; /* Flash Bank 1 Abort Interrupt */
13990  vuint8_t FB1SI:1; /* Flash Bank 1 Stall Interrupt */
13991  vuint8_t FB2AI:1; /* Flash Bank 2 Abort Interrupt */
13992  vuint8_t FB2SI:1; /* Flash Bank 2 Stall Interrupt */
13993  vuint8_t:2;
13994  } B;
13995  } SPP_MCM_MIR_8B_tag;
13996 
13997  typedef union { /* SPP_MCM_MUDCR - Miscellaneous User Defined Control Register */
13998  vuint32_t R;
13999  struct {
14000  vuint32_t MUSERDCR:32; /* User Defined Control Register */
14001  } B;
14002  } SPP_MCM_MUDCR_32B_tag;
14003 
14004  typedef union { /* SPP_MCM_ECR - ECC Configuration Register */
14005  vuint8_t R;
14006  struct {
14007  vuint8_t:2;
14008 #ifndef USE_FIELD_ALIASES_SPP_MCM
14009  vuint8_t EPR1BR:1; /* Enable Platform RAM 1-bit Reporting */
14010 #else
14011  vuint8_t ER1BR:1; /* deprecated name - please avoid */
14012 #endif
14013 #ifndef USE_FIELD_ALIASES_SPP_MCM
14014  vuint8_t EPF1BR:1; /* Enable Platform FLASH 1-bit Reporting */
14015 #else
14016  vuint8_t EF1BR:1; /* deprecated name - please avoid */
14017 #endif
14018  vuint8_t:2;
14019 #ifndef USE_FIELD_ALIASES_SPP_MCM
14020  vuint8_t EPRNCR:1; /* Enable Platform RAM Non-Correctable Reporting */
14021 #else
14022  vuint8_t ERNCR:1; /* deprecated name - please avoid */
14023 #endif
14024 #ifndef USE_FIELD_ALIASES_SPP_MCM
14025  vuint8_t EPFNCR:1; /* Enable Platform FLASH Non-Correctable Reporting */
14026 #else
14027  vuint8_t EFNCR:1; /* deprecated name - please avoid */
14028 #endif
14029  } B;
14030  } SPP_MCM_ECR_8B_tag;
14031 
14032  typedef union { /* SPP_MCM_ESR - ECC Status Register */
14033  vuint8_t R;
14034  struct {
14035  vuint8_t:2;
14036 #ifndef USE_FIELD_ALIASES_SPP_MCM
14037  vuint8_t PR1BC:1; /* Platform RAM 1-bit Correction */
14038 #else
14039  vuint8_t R1BC:1; /* deprecated name - please avoid */
14040 #endif
14041 #ifndef USE_FIELD_ALIASES_SPP_MCM
14042  vuint8_t PF1BC:1; /* Platform FLASH 1-bit Correction */
14043 #else
14044  vuint8_t F1BC:1; /* deprecated name - please avoid */
14045 #endif
14046  vuint8_t:2;
14047 #ifndef USE_FIELD_ALIASES_SPP_MCM
14048  vuint8_t PRNCE:1; /* Platform RAM Non-Correctable Error */
14049 #else
14050  vuint8_t RNCE:1; /* deprecated name - please avoid */
14051 #endif
14052 #ifndef USE_FIELD_ALIASES_SPP_MCM
14053  vuint8_t PFNCE:1; /* Platform FLASH Non-Correctable Error */
14054 #else
14055  vuint8_t FNCE:1; /* deprecated name - please avoid */
14056 #endif
14057  } B;
14058  } SPP_MCM_ESR_8B_tag;
14059 
14060  typedef union { /* SPP_MCM_EEGR - ECC Error Generation Register */
14061  vuint16_t R;
14062  struct {
14063  vuint16_t FRCAP:1; /* Force Platform RAM Error Injection Access Protection */
14064  vuint16_t:1;
14065  vuint16_t FRC1BI:1; /* Force Platform RAM Continuous 1-Bit Data Inversions */
14066  vuint16_t FR11BI:1; /* Force Platform RAM One 1-Bit Data Inversion */
14067  vuint16_t:2;
14068  vuint16_t FRCNCI:1; /* Force Platform RAM Continuous Noncorrectable Data Inversions */
14069  vuint16_t FR1NCI:1; /* Force Platform RAM One Noncorrectable Data Inversions */
14070  vuint16_t:1;
14071  vuint16_t ERRBIT:7; /* Error Bit Position */
14072  } B;
14073  } SPP_MCM_EEGR_16B_tag;
14074 
14075  typedef union { /* SPP_MCM_PFEAR - Platform Flash ECC Error Address Register */
14076  vuint32_t R;
14077  } SPP_MCM_PFEAR_32B_tag;
14078 
14079  typedef union { /* SPP_MCM_PFEMR - Platform Flash ECC Master Number Register */
14080  vuint8_t R;
14081  } SPP_MCM_PFEMR_8B_tag;
14082 
14083  typedef union { /* SPP_MCM_PFEAT - Platform Flash ECC Attributes Register */
14084  vuint8_t R;
14085  struct {
14086 #ifndef USE_FIELD_ALIASES_SPP_MCM
14087  vuint8_t F_WRITE:1; /* AMBA-AHBH Write */
14088 #else
14089  vuint8_t WRITE:1; /* deprecated name - please avoid */
14090 #endif
14091 #ifndef USE_FIELD_ALIASES_SPP_MCM
14092  vuint8_t F_SIZE:3; /* AMBA-AHBH Size */
14093 #else
14094  vuint8_t SIZE:3; /* deprecated name - please avoid */
14095 #endif
14096 #ifndef USE_FIELD_ALIASES_SPP_MCM
14097  vuint8_t F_PROTECT:4; /* AMBA-AHBH PROT */
14098 #else
14099  vuint8_t PROTECTION:4; /* deprecated name - please avoid */
14100 #endif
14101  } B;
14102  } SPP_MCM_PFEAT_8B_tag;
14103 
14104  typedef union { /* SPP_MCM_PFEDRH - Platform Flash ECC Data Register High Word */
14105  vuint32_t R;
14106  } SPP_MCM_PFEDRH_32B_tag;
14107 
14108  typedef union { /* SPP_MCM_PFEDR - Platform Flash ECC Data Register */
14109  vuint32_t R;
14110  } SPP_MCM_PFEDR_32B_tag;
14111 
14112  typedef union { /* SPP_MCM_PREAR - Platform RAM ECC Address Register */
14113  vuint32_t R;
14114  } SPP_MCM_PREAR_32B_tag;
14115 
14116  typedef union { /* SPP_MCM_PRESR - Platform RAM ECC Syndrome Register */
14117  vuint8_t R;
14118  } SPP_MCM_PRESR_8B_tag;
14119 
14120  typedef union { /* SPP_MCM_PREMR - Platform RAM ECC Master Number Register */
14121  vuint8_t R;
14122  struct {
14123  vuint8_t:4;
14124 #ifndef USE_FIELD_ALIASES_SPP_MCM
14125  vuint8_t PR_EMR:4; /* Platform RAM ECC Master Number */
14126 #else
14127  vuint8_t REMR:4; /* deprecated name - please avoid */
14128 #endif
14129  } B;
14130  } SPP_MCM_PREMR_8B_tag;
14131 
14132  typedef union { /* SPP_MCM_PREAT - Platform RAM ECC Attributes Register */
14133  vuint8_t R;
14134  struct {
14135 #ifndef USE_FIELD_ALIASES_SPP_MCM
14136  vuint8_t R_WRITE:1; /* AMBA-AHBH Write */
14137 #else
14138  vuint8_t WRITE:1; /* deprecated name - please avoid */
14139 #endif
14140 #ifndef USE_FIELD_ALIASES_SPP_MCM
14141  vuint8_t R_SIZE:3; /* AMBA-AHBH Size */
14142 #else
14143  vuint8_t SIZE:3; /* deprecated name - please avoid */
14144 #endif
14145 #ifndef USE_FIELD_ALIASES_SPP_MCM
14146  vuint8_t R_PROTECT:4; /* AMBA-AHBH PROT */
14147 #else
14148  vuint8_t PROTECTION:4; /* deprecated name - please avoid */
14149 #endif
14150  } B;
14151  } SPP_MCM_PREAT_8B_tag;
14152 
14153  typedef union { /* SPP_MCM_PREDR - Platform RAM ECC Data Register High Word */
14154  vuint32_t R;
14155  } SPP_MCM_PREDRH_32B_tag;
14156 
14157  typedef union { /* SPP_MCM_PREDR - Platform RAM ECC Data Register */
14158  vuint32_t R;
14159  } SPP_MCM_PREDR_32B_tag;
14160 
14161 
14162 
14163  typedef struct SPP_MCM_struct_tag { /* start of SPP_MCM_tag */
14164  /* SPP_MCM_PCT - Processor Core Type */
14165  SPP_MCM_PCT_16B_tag PCT; /* offset: 0x0000 size: 16 bit */
14166  union {
14167  SPP_MCM_PLREV_16B_tag REV; /* deprecated - please avoid */
14168 
14169  /* SPP_MCM_PLREV - SOC-Defined Platform Revision */
14170  SPP_MCM_PLREV_16B_tag PLREV; /* offset: 0x0002 size: 16 bit */
14171 
14172  };
14173  int8_t SPP_MCM_reserved_0004_C[4];
14174  union {
14175  SPP_MCM_IOPMC_32B_tag MC; /* deprecated - please avoid */
14176 
14177  /* SPP_MCM_IOPMC - IPS On-Platform Module Configuration */
14178  SPP_MCM_IOPMC_32B_tag IOPMC; /* offset: 0x0008 size: 32 bit */
14179 
14180  };
14181  int8_t SPP_MCM_reserved_000C[3];
14182  /* SPP_MCM_MRSR - Miscellaneous Reset Status Register */
14183  SPP_MCM_MRSR_8B_tag MRSR; /* offset: 0x000F size: 8 bit */
14184  int8_t SPP_MCM_reserved_0010[3];
14185  /* SPP_MCM_MWCR - Miscellaneous Wakeup Control Register */
14186  SPP_MCM_MWCR_8B_tag MWCR; /* offset: 0x0013 size: 8 bit */
14187  int8_t SPP_MCM_reserved_0014[11];
14188  /* SPP_MCM_MIR - Miscellaneous Interrupt Register */
14189  SPP_MCM_MIR_8B_tag MIR; /* offset: 0x001F size: 8 bit */
14190  int8_t SPP_MCM_reserved_0020[4];
14191  /* SPP_MCM_MUDCR - Miscellaneous User Defined Control Register */
14192  SPP_MCM_MUDCR_32B_tag MUDCR; /* offset: 0x0024 size: 32 bit */
14193  int8_t SPP_MCM_reserved_0028[27];
14194  /* SPP_MCM_ECR - ECC Configuration Register */
14195  SPP_MCM_ECR_8B_tag ECR; /* offset: 0x0043 size: 8 bit */
14196  int8_t SPP_MCM_reserved_0044[3];
14197  /* SPP_MCM_ESR - ECC Status Register */
14198  SPP_MCM_ESR_8B_tag ESR; /* offset: 0x0047 size: 8 bit */
14199  int8_t SPP_MCM_reserved_0048[2];
14200  /* SPP_MCM_EEGR - ECC Error Generation Register */
14201  SPP_MCM_EEGR_16B_tag EEGR; /* offset: 0x004A size: 16 bit */
14202  int8_t SPP_MCM_reserved_004C_C[4];
14203  union {
14204  /* SPP_MCM_PFEAR - Platform Flash ECC Error Address Register */
14205  SPP_MCM_PFEAR_32B_tag PFEAR; /* offset: 0x0050 size: 32 bit */
14206 
14207  SPP_MCM_PFEAR_32B_tag FEAR; /* deprecated - please avoid */
14208 
14209  };
14210  int8_t SPP_MCM_reserved_0054_C[2];
14211  union {
14212  /* SPP_MCM_PFEMR - Platform Flash ECC Master Number Register */
14213  SPP_MCM_PFEMR_8B_tag PFEMR; /* offset: 0x0056 size: 8 bit */
14214 
14215  SPP_MCM_PFEMR_8B_tag FEMR; /* deprecated - please avoid */
14216 
14217  };
14218  union {
14219  /* SPP_MCM_PFEAT - Platform Flash ECC Attributes Register */
14220  SPP_MCM_PFEAT_8B_tag PFEAT; /* offset: 0x0057 size: 8 bit */
14221 
14222  SPP_MCM_PFEAT_8B_tag FEAT; /* deprecated - please avoid */
14223 
14224  };
14225  /* SPP_MCM_PFEDRH - Platform Flash ECC Data Register High Word */
14226  SPP_MCM_PFEDRH_32B_tag PFEDRH; /* offset: 0x0058 size: 32 bit */
14227  union {
14228  /* SPP_MCM_PFEDR - Platform Flash ECC Data Register */
14229  SPP_MCM_PFEDR_32B_tag PFEDR; /* offset: 0x005C size: 32 bit */
14230 
14231  SPP_MCM_PFEDR_32B_tag FEDR; /* deprecated - please avoid */
14232 
14233  };
14234  union {
14235  SPP_MCM_PREAR_32B_tag REAR; /* deprecated - please avoid */
14236 
14237  /* SPP_MCM_PREAR - Platform RAM ECC Address Register */
14238  SPP_MCM_PREAR_32B_tag PREAR; /* offset: 0x0060 size: 32 bit */
14239 
14240  };
14241  int8_t SPP_MCM_reserved_0064_C;
14242  union {
14243  SPP_MCM_PRESR_8B_tag RESR; /* deprecated - please avoid */
14244 
14245  /* SPP_MCM_PRESR - Platform RAM ECC Syndrome Register */
14246  SPP_MCM_PRESR_8B_tag PRESR; /* offset: 0x0065 size: 8 bit */
14247 
14248  };
14249  union {
14250  SPP_MCM_PREMR_8B_tag REMR; /* deprecated - please avoid */
14251 
14252  /* SPP_MCM_PREMR - Platform RAM ECC Master Number Register */
14253  SPP_MCM_PREMR_8B_tag PREMR; /* offset: 0x0066 size: 8 bit */
14254 
14255  };
14256  union {
14257  SPP_MCM_PREAT_8B_tag REAT; /* deprecated - please avoid */
14258 
14259  /* SPP_MCM_PREAT - Platform RAM ECC Attributes Register */
14260  SPP_MCM_PREAT_8B_tag PREAT; /* offset: 0x0067 size: 8 bit */
14261 
14262  };
14263  /* SPP_MCM_PREDR - Platform RAM ECC Data Register High Word */
14264  SPP_MCM_PREDRH_32B_tag PREDRH; /* offset: 0x0068 size: 32 bit */
14265  union {
14266  SPP_MCM_PREDR_32B_tag REDR; /* deprecated - please avoid */
14267 
14268  /* SPP_MCM_PREDR - Platform RAM ECC Data Register */
14269  SPP_MCM_PREDR_32B_tag PREDR; /* offset: 0x006C size: 32 bit */
14270 
14271  };
14272  } SPP_MCM_tag;
14273 
14274 
14275 #define SPP_MCM (*(volatile SPP_MCM_tag *) 0xFFF40000UL)
14276 
14277 
14278 
14279 /****************************************************************/
14280 /* */
14281 /* Module: SPP_DMA2 */
14282 /* */
14283 /****************************************************************/
14284 
14285  typedef union { /* SPP_DMA2_DMACR - DMA Control Register */
14286  vuint32_t R;
14287  struct {
14288  vuint32_t:14;
14289  vuint32_t CX:1; /* Cancel Transfer */
14290  vuint32_t ECX:1; /* Error Cancel Transfer */
14291  vuint32_t GRP3PRI:2; /* Channel Group 3 Priority */
14292  vuint32_t GRP2PRI:2; /* Channel Group 2 Priority */
14293  vuint32_t GRP1PRI:2; /* Channel Group 1 Priority */
14294  vuint32_t GRP0PRI:2; /* Channel Group 0 Priority */
14295  vuint32_t EMLM:1; /* Enable Minor Loop Mapping */
14296  vuint32_t CLM:1; /* Continuous Link Mode */
14297  vuint32_t HALT:1; /* Halt DMA Operations */
14298  vuint32_t HOE:1; /* Halt on Error */
14299  vuint32_t ERGA:1; /* Enable Round Robin Group Arbitration */
14300  vuint32_t ERCA:1; /* Enable Round Robin Channel Arbitration */
14301  vuint32_t EDBG:1; /* Enable Debug */
14302  vuint32_t EBW:1; /* Enable Buffered Writes */
14303  } B;
14304  } SPP_DMA2_DMACR_32B_tag;
14305 
14306  typedef union { /* SPP_DMA2_DMAES - DMA Error Status Register */
14307  vuint32_t R;
14308  struct {
14309  vuint32_t VLD:1; /* Logical OR of DMAERRH and DMAERRL status bits */
14310  vuint32_t:14;
14311  vuint32_t ECX:1; /* Transfer Cancelled */
14312  vuint32_t GPE:1; /* Group Priority Error */
14313  vuint32_t CPE:1; /* Channel Priority Error */
14314  vuint32_t ERRCHN:6; /* Error Channel Number or Cancelled Channel Number */
14315  vuint32_t SAE:1; /* Source Address Error */
14316  vuint32_t SOE:1; /* Source Offset Error */
14317  vuint32_t DAE:1; /* Destination Address Error */
14318  vuint32_t DOE:1; /* Destination Offset Error */
14319  vuint32_t NCE:1; /* Nbytes/Citer Configuration Error */
14320  vuint32_t SGE:1; /* Scatter/Gather Configuration Error */
14321  vuint32_t SBE:1; /* Source Bus Error */
14322  vuint32_t DBE:1; /* Destination Bus Error */
14323  } B;
14324  } SPP_DMA2_DMAES_32B_tag;
14325 
14326  typedef union { /* SPP_DMA2_DMAERQH - DMA Enable Request Register */
14327  vuint32_t R;
14328  struct {
14329  vuint32_t ERQ:32; /* DMA Enable Request */
14330  } B;
14331  } SPP_DMA2_DMAERQH_32B_tag;
14332 
14333  typedef union { /* SPP_DMA2_DMAERQL - DMA Enable Request Register */
14334  vuint32_t R;
14335  struct {
14336  vuint32_t ERQ:32; /* DMA Enable Request */
14337  } B;
14338  } SPP_DMA2_DMAERQL_32B_tag;
14339 
14340  typedef union { /* SPP_DMA2_DMAEEIH - DMA Enable Error Interrupt Register */
14341  vuint32_t R;
14342  struct {
14343  vuint32_t EEI:32; /* DMA Enable Error Interrupt */
14344  } B;
14345  } SPP_DMA2_DMAEEIH_32B_tag;
14346 
14347  typedef union { /* SPP_DMA2_DMAEEIL - DMA Enable Error Interrupt Register */
14348  vuint32_t R;
14349  struct {
14350  vuint32_t EEI:32; /* DMA Enable Error Interrupt */
14351  } B;
14352  } SPP_DMA2_DMAEEIL_32B_tag;
14353 
14354  typedef union { /* SPP_DMA2_DMASERQ - DMA Set Enable Request Register */
14355  vuint8_t R;
14356  struct {
14357  vuint8_t:1;
14358  vuint8_t SERQ:7; /* Set Enable Request */
14359  } B;
14360  } SPP_DMA2_DMASERQ_8B_tag;
14361 
14362  typedef union { /* SPP_DMA2_DMACERQ - DMA Clear Enable Request Register */
14363  vuint8_t R;
14364  struct {
14365  vuint8_t:1;
14366  vuint8_t CERQ:7; /* Clear Enable Request */
14367  } B;
14368  } SPP_DMA2_DMACERQ_8B_tag;
14369 
14370  typedef union { /* SPP_DMA2_DMASEEI - DMA Set Enable Error Interrupt Register */
14371  vuint8_t R;
14372  struct {
14373  vuint8_t:1;
14374  vuint8_t SEEI:7; /* Set Enable Error Interrupt */
14375  } B;
14376  } SPP_DMA2_DMASEEI_8B_tag;
14377 
14378  typedef union { /* SPP_DMA2_DMACEEI - DMA Clear Enable Error Interrupt Register */
14379  vuint8_t R;
14380  struct {
14381  vuint8_t:1;
14382  vuint8_t CEEI:7; /* Clear Enable Error Interrupt */
14383  } B;
14384  } SPP_DMA2_DMACEEI_8B_tag;
14385 
14386  typedef union { /* SPP_DMA2_DMACINT - DMA Clear Interrupt Request */
14387  vuint8_t R;
14388  struct {
14389  vuint8_t:1;
14390  vuint8_t CINT:7; /* Clear Interrupt Request */
14391  } B;
14392  } SPP_DMA2_DMACINT_8B_tag;
14393 
14394  typedef union { /* SPP_DMA2_DMACERR - DMA Clear Error */
14395  vuint8_t R;
14396  struct {
14397  vuint8_t:1;
14398  vuint8_t CERR:7; /* Clear Error Indicator */
14399  } B;
14400  } SPP_DMA2_DMACERR_8B_tag;
14401 
14402  typedef union { /* SPP_DMA2_DMASSRT - DMA Set START Bit */
14403  vuint8_t R;
14404  struct {
14405  vuint8_t:1;
14406  vuint8_t SSRT:7; /* Set START Bit */
14407  } B;
14408  } SPP_DMA2_DMASSRT_8B_tag;
14409 
14410  typedef union { /* SPP_DMA2_DMACDNE - DMA Clear DONE Status */
14411  vuint8_t R;
14412  struct {
14413  vuint8_t:1;
14414  vuint8_t CDNE:7; /* Clear DONE Status Bit */
14415  } B;
14416  } SPP_DMA2_DMACDNE_8B_tag;
14417 
14418  typedef union { /* SPP_DMA2_DMAINTH - DMA Interrupt Request Register */
14419  vuint32_t R;
14420  struct {
14421  vuint32_t INT:32; /* DMA Interrupt Request */
14422  } B;
14423  } SPP_DMA2_DMAINTH_32B_tag;
14424 
14425  typedef union { /* SPP_DMA2_DMAINTL - DMA Interrupt Request Register */
14426  vuint32_t R;
14427  struct {
14428  vuint32_t INT:32; /* DMA Interrupt Request */
14429  } B;
14430  } SPP_DMA2_DMAINTL_32B_tag;
14431 
14432  typedef union { /* SPP_DMA2_DMAERRH - DMA Error Register */
14433  vuint32_t R;
14434  struct {
14435  vuint32_t ERR:32; /* DMA Error n */
14436  } B;
14437  } SPP_DMA2_DMAERRH_32B_tag;
14438 
14439  typedef union { /* SPP_DMA2_DMAERRL - DMA Error Register */
14440  vuint32_t R;
14441  struct {
14442  vuint32_t ERR:32; /* DMA Error n */
14443  } B;
14444  } SPP_DMA2_DMAERRL_32B_tag;
14445 
14446  typedef union { /* SPP_DMA2_DMAHRSH - DMA Hardware Request Status Register */
14447  vuint32_t R;
14448  struct {
14449  vuint32_t HRS:32; /* DMA Hardware Request Status */
14450  } B;
14451  } SPP_DMA2_DMAHRSH_32B_tag;
14452 
14453  typedef union { /* SPP_DMA2_DMAHRSL - DMA Hardware Request Status Register */
14454  vuint32_t R;
14455  struct {
14456  vuint32_t HRS:32; /* DMA Hardware Request Status */
14457  } B;
14458  } SPP_DMA2_DMAHRSL_32B_tag;
14459 
14460  typedef union { /* SPP_DMA2_DMAGPOR - DMA General Purpose Output Register */
14461  vuint32_t R;
14462  struct {
14463  vuint32_t GPOR:32; /* DMA General Purpose Output */
14464  } B;
14465  } SPP_DMA2_DMAGPOR_32B_tag;
14466 
14467 
14468  /* Register layout for all registers DCHPRI... */
14469 
14470  typedef union { /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */
14471  vuint8_t R;
14472  struct {
14473  vuint8_t ECP:1; /* Enable Channel Preemption */
14474  vuint8_t DPA:1; /* Disable Preempt Ability */
14475  vuint8_t GRPPRI:2; /* Channel n Current Group Priority */
14476  vuint8_t CHPRI:4; /* Channel n Arbitration Priority */
14477  } B;
14478  } SPP_DMA2_DCHPRI_8B_tag;
14479 
14480 
14481  /* Register layout for all registers TCDWORD0_... */
14482 
14483  typedef union { /* SPP_DMA2_TCDn Word0 - Source Address */
14484  vuint32_t R;
14485  struct {
14486  vuint32_t SADDR:32; /* Source Address */
14487  } B;
14488  } SPP_DMA2_TCDWORD0__32B_tag;
14489 
14490 
14491  /* Register layout for all registers TCDWORD4_... */
14492 
14493  typedef union { /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14494  vuint32_t R;
14495  struct {
14496  vuint32_t SMOD:5; /* Source Address Modulo */
14497  vuint32_t SSIZE:3; /* Source Data Transfer Size */
14498  vuint32_t DMOD:5; /* Destination Address Module */
14499  vuint32_t DSIZE:3; /* Destination Data Transfer Size */
14500  vuint32_t SOFF:16; /* Source Address Signed Offset */
14501  } B;
14502  } SPP_DMA2_TCDWORD4__32B_tag;
14503 
14504 
14505  /* Register layout for all registers TCDWORD8_... */
14506 
14507  typedef union { /* SPP_DMA2_TCDn Word2 - nbytes */
14508  vuint32_t R;
14509  struct {
14510  vuint32_t SMLOE:1; /* Source Minor Loop Offset Enable */
14511  vuint32_t DMLOE:1; /* Destination Minor Loop Offset Enable */
14512  vuint32_t MLOFF:20; /* Minor Loop Offset */
14513  vuint32_t NBYTES:10; /* Inner Minor byte transfer Count */
14514  } B;
14515  } SPP_DMA2_TCDWORD8__32B_tag;
14516 
14517 
14518  /* Register layout for all registers TCDWORD12_... */
14519 
14520  typedef union { /* SPP_DMA2_TCDn Word3 - slast */
14521  vuint32_t R;
14522  struct {
14523  vuint32_t SLAST:32; /* Last Source Address Adjustment */
14524  } B;
14525  } SPP_DMA2_TCDWORD12__32B_tag;
14526 
14527 
14528  /* Register layout for all registers TCDWORD16_... */
14529 
14530  typedef union { /* SPP_DMA2_TCDn Word4 - daddr */
14531  vuint32_t R;
14532  struct {
14533  vuint32_t DADDR:32; /* Destination Address */
14534  } B;
14535  } SPP_DMA2_TCDWORD16__32B_tag;
14536 
14537 
14538  /* Register layout for all registers TCDWORD20_... */
14539 
14540  typedef union { /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14541  vuint32_t R;
14542  struct {
14543  vuint32_t CITER_E_LINK:1; /* Enable Channel to channel linking on minor loop complete */
14544  vuint32_t CITER_LINKCH:6; /* Link Channel Number */
14545  vuint32_t CITER:9; /* Current Major Iteration Count */
14546  vuint32_t DOFF:16; /* Destination Address Signed Offset */
14547  } B;
14548  } SPP_DMA2_TCDWORD20__32B_tag;
14549 
14550 
14551  /* Register layout for all registers TCDWORD24_... */
14552 
14553  typedef union { /* SPP_DMA2_TCDn Word6 - dlast_sga */
14554  vuint32_t R;
14555  struct {
14556  vuint32_t DLAST_SGA:32; /* Last destination address adjustment */
14557  } B;
14558  } SPP_DMA2_TCDWORD24__32B_tag;
14559 
14560 
14561  /* Register layout for all registers TCDWORD28_... */
14562 
14563  typedef union { /* SPP_DMA2_TCDn Word7 - biter, etc. */
14564  vuint32_t R;
14565  struct {
14566  vuint32_t BITER:16; /* Enable Channel to Channel linking on minor loop complete */
14567  vuint32_t BWC:2; /* Bandwidth Control */
14568  vuint32_t MAJOR_LINKCH:6; /* Link Channel Number */
14569  vuint32_t DONE:1; /* channel done */
14570  vuint32_t ACTIVE:1; /* Channel Active */
14571  vuint32_t MAJOR_E_LINK:1; /* Enable Channel to Channel Linking on major loop complete */
14572  vuint32_t E_SG:1; /* Enable Scatter/Gather Processing */
14573  vuint32_t D_REQ:1; /* Disable Request */
14574  vuint32_t INT_HALF:1; /* Enable an Interrupt when Major Counter is half complete */
14575  vuint32_t INT_MAJ:1; /* Enable an Interrupt when Major Iteration count completes */
14576  vuint32_t START:1; /* Channel Start */
14577  } B;
14578  } SPP_DMA2_TCDWORD28__32B_tag;
14579 
14580 
14581  typedef struct SPP_DMA2_CHANNEL_struct_tag {
14582 
14583  /* SPP_DMA2_TCDn Word0 - Source Address */
14584  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_; /* relative offset: 0x0000 */
14585  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14586  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_; /* relative offset: 0x0004 */
14587  /* SPP_DMA2_TCDn Word2 - nbytes */
14588  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_; /* relative offset: 0x0008 */
14589  /* SPP_DMA2_TCDn Word3 - slast */
14590  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_; /* relative offset: 0x000C */
14591  /* SPP_DMA2_TCDn Word4 - daddr */
14592  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_; /* relative offset: 0x0010 */
14593  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14594  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_; /* relative offset: 0x0014 */
14595  /* SPP_DMA2_TCDn Word6 - dlast_sga */
14596  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_; /* relative offset: 0x0018 */
14597  /* SPP_DMA2_TCDn Word7 - biter, etc. */
14598  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_; /* relative offset: 0x001C */
14599 
14600  } SPP_DMA2_CHANNEL_tag;
14601 
14602 
14603  typedef struct SPP_DMA2_struct_tag { /* start of SPP_DMA2_tag */
14604  /* SPP_DMA2_DMACR - DMA Control Register */
14605  SPP_DMA2_DMACR_32B_tag DMACR; /* offset: 0x0000 size: 32 bit */
14606  /* SPP_DMA2_DMAES - DMA Error Status Register */
14607  SPP_DMA2_DMAES_32B_tag DMAES; /* offset: 0x0004 size: 32 bit */
14608  /* SPP_DMA2_DMAERQH - DMA Enable Request Register */
14609  SPP_DMA2_DMAERQH_32B_tag DMAERQH; /* offset: 0x0008 size: 32 bit */
14610  /* SPP_DMA2_DMAERQL - DMA Enable Request Register */
14611  SPP_DMA2_DMAERQL_32B_tag DMAERQL; /* offset: 0x000C size: 32 bit */
14612  /* SPP_DMA2_DMAEEIH - DMA Enable Error Interrupt Register */
14613  SPP_DMA2_DMAEEIH_32B_tag DMAEEIH; /* offset: 0x0010 size: 32 bit */
14614  /* SPP_DMA2_DMAEEIL - DMA Enable Error Interrupt Register */
14615  SPP_DMA2_DMAEEIL_32B_tag DMAEEIL; /* offset: 0x0014 size: 32 bit */
14616  /* SPP_DMA2_DMASERQ - DMA Set Enable Request Register */
14617  SPP_DMA2_DMASERQ_8B_tag DMASERQ; /* offset: 0x0018 size: 8 bit */
14618  /* SPP_DMA2_DMACERQ - DMA Clear Enable Request Register */
14619  SPP_DMA2_DMACERQ_8B_tag DMACERQ; /* offset: 0x0019 size: 8 bit */
14620  /* SPP_DMA2_DMASEEI - DMA Set Enable Error Interrupt Register */
14621  SPP_DMA2_DMASEEI_8B_tag DMASEEI; /* offset: 0x001A size: 8 bit */
14622  /* SPP_DMA2_DMACEEI - DMA Clear Enable Error Interrupt Register */
14623  SPP_DMA2_DMACEEI_8B_tag DMACEEI; /* offset: 0x001B size: 8 bit */
14624  /* SPP_DMA2_DMACINT - DMA Clear Interrupt Request */
14625  SPP_DMA2_DMACINT_8B_tag DMACINT; /* offset: 0x001C size: 8 bit */
14626  /* SPP_DMA2_DMACERR - DMA Clear Error */
14627  SPP_DMA2_DMACERR_8B_tag DMACERR; /* offset: 0x001D size: 8 bit */
14628  /* SPP_DMA2_DMASSRT - DMA Set START Bit */
14629  SPP_DMA2_DMASSRT_8B_tag DMASSRT; /* offset: 0x001E size: 8 bit */
14630  /* SPP_DMA2_DMACDNE - DMA Clear DONE Status */
14631  SPP_DMA2_DMACDNE_8B_tag DMACDNE; /* offset: 0x001F size: 8 bit */
14632  /* SPP_DMA2_DMAINTH - DMA Interrupt Request Register */
14633  SPP_DMA2_DMAINTH_32B_tag DMAINTH; /* offset: 0x0020 size: 32 bit */
14634  /* SPP_DMA2_DMAINTL - DMA Interrupt Request Register */
14635  SPP_DMA2_DMAINTL_32B_tag DMAINTL; /* offset: 0x0024 size: 32 bit */
14636  /* SPP_DMA2_DMAERRH - DMA Error Register */
14637  SPP_DMA2_DMAERRH_32B_tag DMAERRH; /* offset: 0x0028 size: 32 bit */
14638  /* SPP_DMA2_DMAERRL - DMA Error Register */
14639  SPP_DMA2_DMAERRL_32B_tag DMAERRL; /* offset: 0x002C size: 32 bit */
14640  /* SPP_DMA2_DMAHRSH - DMA Hardware Request Status Register */
14641  SPP_DMA2_DMAHRSH_32B_tag DMAHRSH; /* offset: 0x0030 size: 32 bit */
14642  /* SPP_DMA2_DMAHRSL - DMA Hardware Request Status Register */
14643  SPP_DMA2_DMAHRSL_32B_tag DMAHRSL; /* offset: 0x0034 size: 32 bit */
14644  /* SPP_DMA2_DMAGPOR - DMA General Purpose Output Register */
14645  SPP_DMA2_DMAGPOR_32B_tag DMAGPOR; /* offset: 0x0038 size: 32 bit */
14646  int8_t SPP_DMA2_reserved_003C_C[196];
14647  union {
14648  /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */
14649  SPP_DMA2_DCHPRI_8B_tag DCHPRI[64]; /* offset: 0x0100 (0x0001 x 64) */
14650 
14651  struct {
14652  /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */
14653  SPP_DMA2_DCHPRI_8B_tag DCHPRI0; /* offset: 0x0100 size: 8 bit */
14654  SPP_DMA2_DCHPRI_8B_tag DCHPRI1; /* offset: 0x0101 size: 8 bit */
14655  SPP_DMA2_DCHPRI_8B_tag DCHPRI2; /* offset: 0x0102 size: 8 bit */
14656  SPP_DMA2_DCHPRI_8B_tag DCHPRI3; /* offset: 0x0103 size: 8 bit */
14657  SPP_DMA2_DCHPRI_8B_tag DCHPRI4; /* offset: 0x0104 size: 8 bit */
14658  SPP_DMA2_DCHPRI_8B_tag DCHPRI5; /* offset: 0x0105 size: 8 bit */
14659  SPP_DMA2_DCHPRI_8B_tag DCHPRI6; /* offset: 0x0106 size: 8 bit */
14660  SPP_DMA2_DCHPRI_8B_tag DCHPRI7; /* offset: 0x0107 size: 8 bit */
14661  SPP_DMA2_DCHPRI_8B_tag DCHPRI8; /* offset: 0x0108 size: 8 bit */
14662  SPP_DMA2_DCHPRI_8B_tag DCHPRI9; /* offset: 0x0109 size: 8 bit */
14663  SPP_DMA2_DCHPRI_8B_tag DCHPRI10; /* offset: 0x010A size: 8 bit */
14664  SPP_DMA2_DCHPRI_8B_tag DCHPRI11; /* offset: 0x010B size: 8 bit */
14665  SPP_DMA2_DCHPRI_8B_tag DCHPRI12; /* offset: 0x010C size: 8 bit */
14666  SPP_DMA2_DCHPRI_8B_tag DCHPRI13; /* offset: 0x010D size: 8 bit */
14667  SPP_DMA2_DCHPRI_8B_tag DCHPRI14; /* offset: 0x010E size: 8 bit */
14668  SPP_DMA2_DCHPRI_8B_tag DCHPRI15; /* offset: 0x010F size: 8 bit */
14669  SPP_DMA2_DCHPRI_8B_tag DCHPRI16; /* offset: 0x0110 size: 8 bit */
14670  SPP_DMA2_DCHPRI_8B_tag DCHPRI17; /* offset: 0x0111 size: 8 bit */
14671  SPP_DMA2_DCHPRI_8B_tag DCHPRI18; /* offset: 0x0112 size: 8 bit */
14672  SPP_DMA2_DCHPRI_8B_tag DCHPRI19; /* offset: 0x0113 size: 8 bit */
14673  SPP_DMA2_DCHPRI_8B_tag DCHPRI20; /* offset: 0x0114 size: 8 bit */
14674  SPP_DMA2_DCHPRI_8B_tag DCHPRI21; /* offset: 0x0115 size: 8 bit */
14675  SPP_DMA2_DCHPRI_8B_tag DCHPRI22; /* offset: 0x0116 size: 8 bit */
14676  SPP_DMA2_DCHPRI_8B_tag DCHPRI23; /* offset: 0x0117 size: 8 bit */
14677  SPP_DMA2_DCHPRI_8B_tag DCHPRI24; /* offset: 0x0118 size: 8 bit */
14678  SPP_DMA2_DCHPRI_8B_tag DCHPRI25; /* offset: 0x0119 size: 8 bit */
14679  SPP_DMA2_DCHPRI_8B_tag DCHPRI26; /* offset: 0x011A size: 8 bit */
14680  SPP_DMA2_DCHPRI_8B_tag DCHPRI27; /* offset: 0x011B size: 8 bit */
14681  SPP_DMA2_DCHPRI_8B_tag DCHPRI28; /* offset: 0x011C size: 8 bit */
14682  SPP_DMA2_DCHPRI_8B_tag DCHPRI29; /* offset: 0x011D size: 8 bit */
14683  SPP_DMA2_DCHPRI_8B_tag DCHPRI30; /* offset: 0x011E size: 8 bit */
14684  SPP_DMA2_DCHPRI_8B_tag DCHPRI31; /* offset: 0x011F size: 8 bit */
14685  SPP_DMA2_DCHPRI_8B_tag DCHPRI32; /* offset: 0x0120 size: 8 bit */
14686  SPP_DMA2_DCHPRI_8B_tag DCHPRI33; /* offset: 0x0121 size: 8 bit */
14687  SPP_DMA2_DCHPRI_8B_tag DCHPRI34; /* offset: 0x0122 size: 8 bit */
14688  SPP_DMA2_DCHPRI_8B_tag DCHPRI35; /* offset: 0x0123 size: 8 bit */
14689  SPP_DMA2_DCHPRI_8B_tag DCHPRI36; /* offset: 0x0124 size: 8 bit */
14690  SPP_DMA2_DCHPRI_8B_tag DCHPRI37; /* offset: 0x0125 size: 8 bit */
14691  SPP_DMA2_DCHPRI_8B_tag DCHPRI38; /* offset: 0x0126 size: 8 bit */
14692  SPP_DMA2_DCHPRI_8B_tag DCHPRI39; /* offset: 0x0127 size: 8 bit */
14693  SPP_DMA2_DCHPRI_8B_tag DCHPRI40; /* offset: 0x0128 size: 8 bit */
14694  SPP_DMA2_DCHPRI_8B_tag DCHPRI41; /* offset: 0x0129 size: 8 bit */
14695  SPP_DMA2_DCHPRI_8B_tag DCHPRI42; /* offset: 0x012A size: 8 bit */
14696  SPP_DMA2_DCHPRI_8B_tag DCHPRI43; /* offset: 0x012B size: 8 bit */
14697  SPP_DMA2_DCHPRI_8B_tag DCHPRI44; /* offset: 0x012C size: 8 bit */
14698  SPP_DMA2_DCHPRI_8B_tag DCHPRI45; /* offset: 0x012D size: 8 bit */
14699  SPP_DMA2_DCHPRI_8B_tag DCHPRI46; /* offset: 0x012E size: 8 bit */
14700  SPP_DMA2_DCHPRI_8B_tag DCHPRI47; /* offset: 0x012F size: 8 bit */
14701  SPP_DMA2_DCHPRI_8B_tag DCHPRI48; /* offset: 0x0130 size: 8 bit */
14702  SPP_DMA2_DCHPRI_8B_tag DCHPRI49; /* offset: 0x0131 size: 8 bit */
14703  SPP_DMA2_DCHPRI_8B_tag DCHPRI50; /* offset: 0x0132 size: 8 bit */
14704  SPP_DMA2_DCHPRI_8B_tag DCHPRI51; /* offset: 0x0133 size: 8 bit */
14705  SPP_DMA2_DCHPRI_8B_tag DCHPRI52; /* offset: 0x0134 size: 8 bit */
14706  SPP_DMA2_DCHPRI_8B_tag DCHPRI53; /* offset: 0x0135 size: 8 bit */
14707  SPP_DMA2_DCHPRI_8B_tag DCHPRI54; /* offset: 0x0136 size: 8 bit */
14708  SPP_DMA2_DCHPRI_8B_tag DCHPRI55; /* offset: 0x0137 size: 8 bit */
14709  SPP_DMA2_DCHPRI_8B_tag DCHPRI56; /* offset: 0x0138 size: 8 bit */
14710  SPP_DMA2_DCHPRI_8B_tag DCHPRI57; /* offset: 0x0139 size: 8 bit */
14711  SPP_DMA2_DCHPRI_8B_tag DCHPRI58; /* offset: 0x013A size: 8 bit */
14712  SPP_DMA2_DCHPRI_8B_tag DCHPRI59; /* offset: 0x013B size: 8 bit */
14713  SPP_DMA2_DCHPRI_8B_tag DCHPRI60; /* offset: 0x013C size: 8 bit */
14714  SPP_DMA2_DCHPRI_8B_tag DCHPRI61; /* offset: 0x013D size: 8 bit */
14715  SPP_DMA2_DCHPRI_8B_tag DCHPRI62; /* offset: 0x013E size: 8 bit */
14716  SPP_DMA2_DCHPRI_8B_tag DCHPRI63; /* offset: 0x013F size: 8 bit */
14717  };
14718 
14719  };
14720  int8_t SPP_DMA2_reserved_0140_C[3776];
14721  union {
14722  /* Register set CHANNEL */
14723  SPP_DMA2_CHANNEL_tag CHANNEL[64]; /* offset: 0x1000 (0x0020 x 64) */
14724 
14725  struct {
14726  /* SPP_DMA2_TCDn Word0 - Source Address */
14727  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_0; /* offset: 0x1000 size: 32 bit */
14728  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14729  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_0; /* offset: 0x1004 size: 32 bit */
14730  /* SPP_DMA2_TCDn Word2 - nbytes */
14731  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_0; /* offset: 0x1008 size: 32 bit */
14732  /* SPP_DMA2_TCDn Word3 - slast */
14733  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_0; /* offset: 0x100C size: 32 bit */
14734  /* SPP_DMA2_TCDn Word4 - daddr */
14735  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_0; /* offset: 0x1010 size: 32 bit */
14736  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14737  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_0; /* offset: 0x1014 size: 32 bit */
14738  /* SPP_DMA2_TCDn Word6 - dlast_sga */
14739  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_0; /* offset: 0x1018 size: 32 bit */
14740  /* SPP_DMA2_TCDn Word7 - biter, etc. */
14741  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_0; /* offset: 0x101C size: 32 bit */
14742  /* SPP_DMA2_TCDn Word0 - Source Address */
14743  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_1; /* offset: 0x1020 size: 32 bit */
14744  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14745  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_1; /* offset: 0x1024 size: 32 bit */
14746  /* SPP_DMA2_TCDn Word2 - nbytes */
14747  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_1; /* offset: 0x1028 size: 32 bit */
14748  /* SPP_DMA2_TCDn Word3 - slast */
14749  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_1; /* offset: 0x102C size: 32 bit */
14750  /* SPP_DMA2_TCDn Word4 - daddr */
14751  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_1; /* offset: 0x1030 size: 32 bit */
14752  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14753  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_1; /* offset: 0x1034 size: 32 bit */
14754  /* SPP_DMA2_TCDn Word6 - dlast_sga */
14755  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_1; /* offset: 0x1038 size: 32 bit */
14756  /* SPP_DMA2_TCDn Word7 - biter, etc. */
14757  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_1; /* offset: 0x103C size: 32 bit */
14758  /* SPP_DMA2_TCDn Word0 - Source Address */
14759  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_2; /* offset: 0x1040 size: 32 bit */
14760  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14761  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_2; /* offset: 0x1044 size: 32 bit */
14762  /* SPP_DMA2_TCDn Word2 - nbytes */
14763  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_2; /* offset: 0x1048 size: 32 bit */
14764  /* SPP_DMA2_TCDn Word3 - slast */
14765  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_2; /* offset: 0x104C size: 32 bit */
14766  /* SPP_DMA2_TCDn Word4 - daddr */
14767  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_2; /* offset: 0x1050 size: 32 bit */
14768  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14769  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_2; /* offset: 0x1054 size: 32 bit */
14770  /* SPP_DMA2_TCDn Word6 - dlast_sga */
14771  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_2; /* offset: 0x1058 size: 32 bit */
14772  /* SPP_DMA2_TCDn Word7 - biter, etc. */
14773  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_2; /* offset: 0x105C size: 32 bit */
14774  /* SPP_DMA2_TCDn Word0 - Source Address */
14775  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_3; /* offset: 0x1060 size: 32 bit */
14776  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14777  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_3; /* offset: 0x1064 size: 32 bit */
14778  /* SPP_DMA2_TCDn Word2 - nbytes */
14779  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_3; /* offset: 0x1068 size: 32 bit */
14780  /* SPP_DMA2_TCDn Word3 - slast */
14781  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_3; /* offset: 0x106C size: 32 bit */
14782  /* SPP_DMA2_TCDn Word4 - daddr */
14783  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_3; /* offset: 0x1070 size: 32 bit */
14784  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14785  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_3; /* offset: 0x1074 size: 32 bit */
14786  /* SPP_DMA2_TCDn Word6 - dlast_sga */
14787  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_3; /* offset: 0x1078 size: 32 bit */
14788  /* SPP_DMA2_TCDn Word7 - biter, etc. */
14789  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_3; /* offset: 0x107C size: 32 bit */
14790  /* SPP_DMA2_TCDn Word0 - Source Address */
14791  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_4; /* offset: 0x1080 size: 32 bit */
14792  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14793  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_4; /* offset: 0x1084 size: 32 bit */
14794  /* SPP_DMA2_TCDn Word2 - nbytes */
14795  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_4; /* offset: 0x1088 size: 32 bit */
14796  /* SPP_DMA2_TCDn Word3 - slast */
14797  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_4; /* offset: 0x108C size: 32 bit */
14798  /* SPP_DMA2_TCDn Word4 - daddr */
14799  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_4; /* offset: 0x1090 size: 32 bit */
14800  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14801  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_4; /* offset: 0x1094 size: 32 bit */
14802  /* SPP_DMA2_TCDn Word6 - dlast_sga */
14803  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_4; /* offset: 0x1098 size: 32 bit */
14804  /* SPP_DMA2_TCDn Word7 - biter, etc. */
14805  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_4; /* offset: 0x109C size: 32 bit */
14806  /* SPP_DMA2_TCDn Word0 - Source Address */
14807  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_5; /* offset: 0x10A0 size: 32 bit */
14808  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14809  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_5; /* offset: 0x10A4 size: 32 bit */
14810  /* SPP_DMA2_TCDn Word2 - nbytes */
14811  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_5; /* offset: 0x10A8 size: 32 bit */
14812  /* SPP_DMA2_TCDn Word3 - slast */
14813  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_5; /* offset: 0x10AC size: 32 bit */
14814  /* SPP_DMA2_TCDn Word4 - daddr */
14815  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_5; /* offset: 0x10B0 size: 32 bit */
14816  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14817  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_5; /* offset: 0x10B4 size: 32 bit */
14818  /* SPP_DMA2_TCDn Word6 - dlast_sga */
14819  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_5; /* offset: 0x10B8 size: 32 bit */
14820  /* SPP_DMA2_TCDn Word7 - biter, etc. */
14821  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_5; /* offset: 0x10BC size: 32 bit */
14822  /* SPP_DMA2_TCDn Word0 - Source Address */
14823  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_6; /* offset: 0x10C0 size: 32 bit */
14824  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14825  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_6; /* offset: 0x10C4 size: 32 bit */
14826  /* SPP_DMA2_TCDn Word2 - nbytes */
14827  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_6; /* offset: 0x10C8 size: 32 bit */
14828  /* SPP_DMA2_TCDn Word3 - slast */
14829  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_6; /* offset: 0x10CC size: 32 bit */
14830  /* SPP_DMA2_TCDn Word4 - daddr */
14831  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_6; /* offset: 0x10D0 size: 32 bit */
14832  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14833  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_6; /* offset: 0x10D4 size: 32 bit */
14834  /* SPP_DMA2_TCDn Word6 - dlast_sga */
14835  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_6; /* offset: 0x10D8 size: 32 bit */
14836  /* SPP_DMA2_TCDn Word7 - biter, etc. */
14837  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_6; /* offset: 0x10DC size: 32 bit */
14838  /* SPP_DMA2_TCDn Word0 - Source Address */
14839  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_7; /* offset: 0x10E0 size: 32 bit */
14840  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14841  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_7; /* offset: 0x10E4 size: 32 bit */
14842  /* SPP_DMA2_TCDn Word2 - nbytes */
14843  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_7; /* offset: 0x10E8 size: 32 bit */
14844  /* SPP_DMA2_TCDn Word3 - slast */
14845  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_7; /* offset: 0x10EC size: 32 bit */
14846  /* SPP_DMA2_TCDn Word4 - daddr */
14847  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_7; /* offset: 0x10F0 size: 32 bit */
14848  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14849  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_7; /* offset: 0x10F4 size: 32 bit */
14850  /* SPP_DMA2_TCDn Word6 - dlast_sga */
14851  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_7; /* offset: 0x10F8 size: 32 bit */
14852  /* SPP_DMA2_TCDn Word7 - biter, etc. */
14853  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_7; /* offset: 0x10FC size: 32 bit */
14854  /* SPP_DMA2_TCDn Word0 - Source Address */
14855  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_8; /* offset: 0x1100 size: 32 bit */
14856  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14857  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_8; /* offset: 0x1104 size: 32 bit */
14858  /* SPP_DMA2_TCDn Word2 - nbytes */
14859  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_8; /* offset: 0x1108 size: 32 bit */
14860  /* SPP_DMA2_TCDn Word3 - slast */
14861  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_8; /* offset: 0x110C size: 32 bit */
14862  /* SPP_DMA2_TCDn Word4 - daddr */
14863  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_8; /* offset: 0x1110 size: 32 bit */
14864  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14865  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_8; /* offset: 0x1114 size: 32 bit */
14866  /* SPP_DMA2_TCDn Word6 - dlast_sga */
14867  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_8; /* offset: 0x1118 size: 32 bit */
14868  /* SPP_DMA2_TCDn Word7 - biter, etc. */
14869  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_8; /* offset: 0x111C size: 32 bit */
14870  /* SPP_DMA2_TCDn Word0 - Source Address */
14871  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_9; /* offset: 0x1120 size: 32 bit */
14872  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14873  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_9; /* offset: 0x1124 size: 32 bit */
14874  /* SPP_DMA2_TCDn Word2 - nbytes */
14875  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_9; /* offset: 0x1128 size: 32 bit */
14876  /* SPP_DMA2_TCDn Word3 - slast */
14877  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_9; /* offset: 0x112C size: 32 bit */
14878  /* SPP_DMA2_TCDn Word4 - daddr */
14879  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_9; /* offset: 0x1130 size: 32 bit */
14880  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14881  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_9; /* offset: 0x1134 size: 32 bit */
14882  /* SPP_DMA2_TCDn Word6 - dlast_sga */
14883  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_9; /* offset: 0x1138 size: 32 bit */
14884  /* SPP_DMA2_TCDn Word7 - biter, etc. */
14885  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_9; /* offset: 0x113C size: 32 bit */
14886  /* SPP_DMA2_TCDn Word0 - Source Address */
14887  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_10; /* offset: 0x1140 size: 32 bit */
14888  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14889  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_10; /* offset: 0x1144 size: 32 bit */
14890  /* SPP_DMA2_TCDn Word2 - nbytes */
14891  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_10; /* offset: 0x1148 size: 32 bit */
14892  /* SPP_DMA2_TCDn Word3 - slast */
14893  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_10; /* offset: 0x114C size: 32 bit */
14894  /* SPP_DMA2_TCDn Word4 - daddr */
14895  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_10; /* offset: 0x1150 size: 32 bit */
14896  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14897  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_10; /* offset: 0x1154 size: 32 bit */
14898  /* SPP_DMA2_TCDn Word6 - dlast_sga */
14899  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_10; /* offset: 0x1158 size: 32 bit */
14900  /* SPP_DMA2_TCDn Word7 - biter, etc. */
14901  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_10; /* offset: 0x115C size: 32 bit */
14902  /* SPP_DMA2_TCDn Word0 - Source Address */
14903  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_11; /* offset: 0x1160 size: 32 bit */
14904  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14905  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_11; /* offset: 0x1164 size: 32 bit */
14906  /* SPP_DMA2_TCDn Word2 - nbytes */
14907  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_11; /* offset: 0x1168 size: 32 bit */
14908  /* SPP_DMA2_TCDn Word3 - slast */
14909  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_11; /* offset: 0x116C size: 32 bit */
14910  /* SPP_DMA2_TCDn Word4 - daddr */
14911  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_11; /* offset: 0x1170 size: 32 bit */
14912  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14913  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_11; /* offset: 0x1174 size: 32 bit */
14914  /* SPP_DMA2_TCDn Word6 - dlast_sga */
14915  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_11; /* offset: 0x1178 size: 32 bit */
14916  /* SPP_DMA2_TCDn Word7 - biter, etc. */
14917  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_11; /* offset: 0x117C size: 32 bit */
14918  /* SPP_DMA2_TCDn Word0 - Source Address */
14919  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_12; /* offset: 0x1180 size: 32 bit */
14920  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14921  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_12; /* offset: 0x1184 size: 32 bit */
14922  /* SPP_DMA2_TCDn Word2 - nbytes */
14923  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_12; /* offset: 0x1188 size: 32 bit */
14924  /* SPP_DMA2_TCDn Word3 - slast */
14925  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_12; /* offset: 0x118C size: 32 bit */
14926  /* SPP_DMA2_TCDn Word4 - daddr */
14927  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_12; /* offset: 0x1190 size: 32 bit */
14928  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14929  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_12; /* offset: 0x1194 size: 32 bit */
14930  /* SPP_DMA2_TCDn Word6 - dlast_sga */
14931  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_12; /* offset: 0x1198 size: 32 bit */
14932  /* SPP_DMA2_TCDn Word7 - biter, etc. */
14933  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_12; /* offset: 0x119C size: 32 bit */
14934  /* SPP_DMA2_TCDn Word0 - Source Address */
14935  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_13; /* offset: 0x11A0 size: 32 bit */
14936  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14937  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_13; /* offset: 0x11A4 size: 32 bit */
14938  /* SPP_DMA2_TCDn Word2 - nbytes */
14939  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_13; /* offset: 0x11A8 size: 32 bit */
14940  /* SPP_DMA2_TCDn Word3 - slast */
14941  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_13; /* offset: 0x11AC size: 32 bit */
14942  /* SPP_DMA2_TCDn Word4 - daddr */
14943  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_13; /* offset: 0x11B0 size: 32 bit */
14944  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14945  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_13; /* offset: 0x11B4 size: 32 bit */
14946  /* SPP_DMA2_TCDn Word6 - dlast_sga */
14947  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_13; /* offset: 0x11B8 size: 32 bit */
14948  /* SPP_DMA2_TCDn Word7 - biter, etc. */
14949  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_13; /* offset: 0x11BC size: 32 bit */
14950  /* SPP_DMA2_TCDn Word0 - Source Address */
14951  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_14; /* offset: 0x11C0 size: 32 bit */
14952  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14953  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_14; /* offset: 0x11C4 size: 32 bit */
14954  /* SPP_DMA2_TCDn Word2 - nbytes */
14955  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_14; /* offset: 0x11C8 size: 32 bit */
14956  /* SPP_DMA2_TCDn Word3 - slast */
14957  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_14; /* offset: 0x11CC size: 32 bit */
14958  /* SPP_DMA2_TCDn Word4 - daddr */
14959  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_14; /* offset: 0x11D0 size: 32 bit */
14960  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14961  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_14; /* offset: 0x11D4 size: 32 bit */
14962  /* SPP_DMA2_TCDn Word6 - dlast_sga */
14963  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_14; /* offset: 0x11D8 size: 32 bit */
14964  /* SPP_DMA2_TCDn Word7 - biter, etc. */
14965  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_14; /* offset: 0x11DC size: 32 bit */
14966  /* SPP_DMA2_TCDn Word0 - Source Address */
14967  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_15; /* offset: 0x11E0 size: 32 bit */
14968  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14969  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_15; /* offset: 0x11E4 size: 32 bit */
14970  /* SPP_DMA2_TCDn Word2 - nbytes */
14971  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_15; /* offset: 0x11E8 size: 32 bit */
14972  /* SPP_DMA2_TCDn Word3 - slast */
14973  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_15; /* offset: 0x11EC size: 32 bit */
14974  /* SPP_DMA2_TCDn Word4 - daddr */
14975  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_15; /* offset: 0x11F0 size: 32 bit */
14976  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14977  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_15; /* offset: 0x11F4 size: 32 bit */
14978  /* SPP_DMA2_TCDn Word6 - dlast_sga */
14979  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_15; /* offset: 0x11F8 size: 32 bit */
14980  /* SPP_DMA2_TCDn Word7 - biter, etc. */
14981  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_15; /* offset: 0x11FC size: 32 bit */
14982  /* SPP_DMA2_TCDn Word0 - Source Address */
14983  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_16; /* offset: 0x1200 size: 32 bit */
14984  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
14985  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_16; /* offset: 0x1204 size: 32 bit */
14986  /* SPP_DMA2_TCDn Word2 - nbytes */
14987  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_16; /* offset: 0x1208 size: 32 bit */
14988  /* SPP_DMA2_TCDn Word3 - slast */
14989  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_16; /* offset: 0x120C size: 32 bit */
14990  /* SPP_DMA2_TCDn Word4 - daddr */
14991  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_16; /* offset: 0x1210 size: 32 bit */
14992  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
14993  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_16; /* offset: 0x1214 size: 32 bit */
14994  /* SPP_DMA2_TCDn Word6 - dlast_sga */
14995  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_16; /* offset: 0x1218 size: 32 bit */
14996  /* SPP_DMA2_TCDn Word7 - biter, etc. */
14997  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_16; /* offset: 0x121C size: 32 bit */
14998  /* SPP_DMA2_TCDn Word0 - Source Address */
14999  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_17; /* offset: 0x1220 size: 32 bit */
15000  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15001  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_17; /* offset: 0x1224 size: 32 bit */
15002  /* SPP_DMA2_TCDn Word2 - nbytes */
15003  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_17; /* offset: 0x1228 size: 32 bit */
15004  /* SPP_DMA2_TCDn Word3 - slast */
15005  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_17; /* offset: 0x122C size: 32 bit */
15006  /* SPP_DMA2_TCDn Word4 - daddr */
15007  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_17; /* offset: 0x1230 size: 32 bit */
15008  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15009  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_17; /* offset: 0x1234 size: 32 bit */
15010  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15011  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_17; /* offset: 0x1238 size: 32 bit */
15012  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15013  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_17; /* offset: 0x123C size: 32 bit */
15014  /* SPP_DMA2_TCDn Word0 - Source Address */
15015  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_18; /* offset: 0x1240 size: 32 bit */
15016  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15017  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_18; /* offset: 0x1244 size: 32 bit */
15018  /* SPP_DMA2_TCDn Word2 - nbytes */
15019  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_18; /* offset: 0x1248 size: 32 bit */
15020  /* SPP_DMA2_TCDn Word3 - slast */
15021  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_18; /* offset: 0x124C size: 32 bit */
15022  /* SPP_DMA2_TCDn Word4 - daddr */
15023  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_18; /* offset: 0x1250 size: 32 bit */
15024  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15025  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_18; /* offset: 0x1254 size: 32 bit */
15026  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15027  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_18; /* offset: 0x1258 size: 32 bit */
15028  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15029  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_18; /* offset: 0x125C size: 32 bit */
15030  /* SPP_DMA2_TCDn Word0 - Source Address */
15031  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_19; /* offset: 0x1260 size: 32 bit */
15032  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15033  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_19; /* offset: 0x1264 size: 32 bit */
15034  /* SPP_DMA2_TCDn Word2 - nbytes */
15035  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_19; /* offset: 0x1268 size: 32 bit */
15036  /* SPP_DMA2_TCDn Word3 - slast */
15037  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_19; /* offset: 0x126C size: 32 bit */
15038  /* SPP_DMA2_TCDn Word4 - daddr */
15039  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_19; /* offset: 0x1270 size: 32 bit */
15040  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15041  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_19; /* offset: 0x1274 size: 32 bit */
15042  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15043  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_19; /* offset: 0x1278 size: 32 bit */
15044  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15045  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_19; /* offset: 0x127C size: 32 bit */
15046  /* SPP_DMA2_TCDn Word0 - Source Address */
15047  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_20; /* offset: 0x1280 size: 32 bit */
15048  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15049  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_20; /* offset: 0x1284 size: 32 bit */
15050  /* SPP_DMA2_TCDn Word2 - nbytes */
15051  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_20; /* offset: 0x1288 size: 32 bit */
15052  /* SPP_DMA2_TCDn Word3 - slast */
15053  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_20; /* offset: 0x128C size: 32 bit */
15054  /* SPP_DMA2_TCDn Word4 - daddr */
15055  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_20; /* offset: 0x1290 size: 32 bit */
15056  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15057  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_20; /* offset: 0x1294 size: 32 bit */
15058  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15059  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_20; /* offset: 0x1298 size: 32 bit */
15060  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15061  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_20; /* offset: 0x129C size: 32 bit */
15062  /* SPP_DMA2_TCDn Word0 - Source Address */
15063  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_21; /* offset: 0x12A0 size: 32 bit */
15064  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15065  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_21; /* offset: 0x12A4 size: 32 bit */
15066  /* SPP_DMA2_TCDn Word2 - nbytes */
15067  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_21; /* offset: 0x12A8 size: 32 bit */
15068  /* SPP_DMA2_TCDn Word3 - slast */
15069  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_21; /* offset: 0x12AC size: 32 bit */
15070  /* SPP_DMA2_TCDn Word4 - daddr */
15071  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_21; /* offset: 0x12B0 size: 32 bit */
15072  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15073  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_21; /* offset: 0x12B4 size: 32 bit */
15074  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15075  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_21; /* offset: 0x12B8 size: 32 bit */
15076  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15077  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_21; /* offset: 0x12BC size: 32 bit */
15078  /* SPP_DMA2_TCDn Word0 - Source Address */
15079  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_22; /* offset: 0x12C0 size: 32 bit */
15080  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15081  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_22; /* offset: 0x12C4 size: 32 bit */
15082  /* SPP_DMA2_TCDn Word2 - nbytes */
15083  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_22; /* offset: 0x12C8 size: 32 bit */
15084  /* SPP_DMA2_TCDn Word3 - slast */
15085  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_22; /* offset: 0x12CC size: 32 bit */
15086  /* SPP_DMA2_TCDn Word4 - daddr */
15087  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_22; /* offset: 0x12D0 size: 32 bit */
15088  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15089  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_22; /* offset: 0x12D4 size: 32 bit */
15090  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15091  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_22; /* offset: 0x12D8 size: 32 bit */
15092  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15093  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_22; /* offset: 0x12DC size: 32 bit */
15094  /* SPP_DMA2_TCDn Word0 - Source Address */
15095  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_23; /* offset: 0x12E0 size: 32 bit */
15096  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15097  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_23; /* offset: 0x12E4 size: 32 bit */
15098  /* SPP_DMA2_TCDn Word2 - nbytes */
15099  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_23; /* offset: 0x12E8 size: 32 bit */
15100  /* SPP_DMA2_TCDn Word3 - slast */
15101  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_23; /* offset: 0x12EC size: 32 bit */
15102  /* SPP_DMA2_TCDn Word4 - daddr */
15103  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_23; /* offset: 0x12F0 size: 32 bit */
15104  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15105  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_23; /* offset: 0x12F4 size: 32 bit */
15106  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15107  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_23; /* offset: 0x12F8 size: 32 bit */
15108  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15109  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_23; /* offset: 0x12FC size: 32 bit */
15110  /* SPP_DMA2_TCDn Word0 - Source Address */
15111  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_24; /* offset: 0x1300 size: 32 bit */
15112  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15113  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_24; /* offset: 0x1304 size: 32 bit */
15114  /* SPP_DMA2_TCDn Word2 - nbytes */
15115  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_24; /* offset: 0x1308 size: 32 bit */
15116  /* SPP_DMA2_TCDn Word3 - slast */
15117  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_24; /* offset: 0x130C size: 32 bit */
15118  /* SPP_DMA2_TCDn Word4 - daddr */
15119  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_24; /* offset: 0x1310 size: 32 bit */
15120  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15121  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_24; /* offset: 0x1314 size: 32 bit */
15122  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15123  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_24; /* offset: 0x1318 size: 32 bit */
15124  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15125  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_24; /* offset: 0x131C size: 32 bit */
15126  /* SPP_DMA2_TCDn Word0 - Source Address */
15127  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_25; /* offset: 0x1320 size: 32 bit */
15128  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15129  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_25; /* offset: 0x1324 size: 32 bit */
15130  /* SPP_DMA2_TCDn Word2 - nbytes */
15131  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_25; /* offset: 0x1328 size: 32 bit */
15132  /* SPP_DMA2_TCDn Word3 - slast */
15133  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_25; /* offset: 0x132C size: 32 bit */
15134  /* SPP_DMA2_TCDn Word4 - daddr */
15135  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_25; /* offset: 0x1330 size: 32 bit */
15136  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15137  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_25; /* offset: 0x1334 size: 32 bit */
15138  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15139  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_25; /* offset: 0x1338 size: 32 bit */
15140  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15141  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_25; /* offset: 0x133C size: 32 bit */
15142  /* SPP_DMA2_TCDn Word0 - Source Address */
15143  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_26; /* offset: 0x1340 size: 32 bit */
15144  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15145  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_26; /* offset: 0x1344 size: 32 bit */
15146  /* SPP_DMA2_TCDn Word2 - nbytes */
15147  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_26; /* offset: 0x1348 size: 32 bit */
15148  /* SPP_DMA2_TCDn Word3 - slast */
15149  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_26; /* offset: 0x134C size: 32 bit */
15150  /* SPP_DMA2_TCDn Word4 - daddr */
15151  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_26; /* offset: 0x1350 size: 32 bit */
15152  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15153  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_26; /* offset: 0x1354 size: 32 bit */
15154  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15155  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_26; /* offset: 0x1358 size: 32 bit */
15156  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15157  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_26; /* offset: 0x135C size: 32 bit */
15158  /* SPP_DMA2_TCDn Word0 - Source Address */
15159  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_27; /* offset: 0x1360 size: 32 bit */
15160  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15161  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_27; /* offset: 0x1364 size: 32 bit */
15162  /* SPP_DMA2_TCDn Word2 - nbytes */
15163  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_27; /* offset: 0x1368 size: 32 bit */
15164  /* SPP_DMA2_TCDn Word3 - slast */
15165  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_27; /* offset: 0x136C size: 32 bit */
15166  /* SPP_DMA2_TCDn Word4 - daddr */
15167  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_27; /* offset: 0x1370 size: 32 bit */
15168  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15169  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_27; /* offset: 0x1374 size: 32 bit */
15170  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15171  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_27; /* offset: 0x1378 size: 32 bit */
15172  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15173  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_27; /* offset: 0x137C size: 32 bit */
15174  /* SPP_DMA2_TCDn Word0 - Source Address */
15175  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_28; /* offset: 0x1380 size: 32 bit */
15176  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15177  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_28; /* offset: 0x1384 size: 32 bit */
15178  /* SPP_DMA2_TCDn Word2 - nbytes */
15179  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_28; /* offset: 0x1388 size: 32 bit */
15180  /* SPP_DMA2_TCDn Word3 - slast */
15181  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_28; /* offset: 0x138C size: 32 bit */
15182  /* SPP_DMA2_TCDn Word4 - daddr */
15183  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_28; /* offset: 0x1390 size: 32 bit */
15184  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15185  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_28; /* offset: 0x1394 size: 32 bit */
15186  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15187  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_28; /* offset: 0x1398 size: 32 bit */
15188  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15189  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_28; /* offset: 0x139C size: 32 bit */
15190  /* SPP_DMA2_TCDn Word0 - Source Address */
15191  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_29; /* offset: 0x13A0 size: 32 bit */
15192  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15193  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_29; /* offset: 0x13A4 size: 32 bit */
15194  /* SPP_DMA2_TCDn Word2 - nbytes */
15195  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_29; /* offset: 0x13A8 size: 32 bit */
15196  /* SPP_DMA2_TCDn Word3 - slast */
15197  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_29; /* offset: 0x13AC size: 32 bit */
15198  /* SPP_DMA2_TCDn Word4 - daddr */
15199  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_29; /* offset: 0x13B0 size: 32 bit */
15200  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15201  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_29; /* offset: 0x13B4 size: 32 bit */
15202  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15203  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_29; /* offset: 0x13B8 size: 32 bit */
15204  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15205  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_29; /* offset: 0x13BC size: 32 bit */
15206  /* SPP_DMA2_TCDn Word0 - Source Address */
15207  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_30; /* offset: 0x13C0 size: 32 bit */
15208  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15209  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_30; /* offset: 0x13C4 size: 32 bit */
15210  /* SPP_DMA2_TCDn Word2 - nbytes */
15211  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_30; /* offset: 0x13C8 size: 32 bit */
15212  /* SPP_DMA2_TCDn Word3 - slast */
15213  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_30; /* offset: 0x13CC size: 32 bit */
15214  /* SPP_DMA2_TCDn Word4 - daddr */
15215  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_30; /* offset: 0x13D0 size: 32 bit */
15216  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15217  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_30; /* offset: 0x13D4 size: 32 bit */
15218  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15219  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_30; /* offset: 0x13D8 size: 32 bit */
15220  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15221  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_30; /* offset: 0x13DC size: 32 bit */
15222  /* SPP_DMA2_TCDn Word0 - Source Address */
15223  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_31; /* offset: 0x13E0 size: 32 bit */
15224  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15225  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_31; /* offset: 0x13E4 size: 32 bit */
15226  /* SPP_DMA2_TCDn Word2 - nbytes */
15227  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_31; /* offset: 0x13E8 size: 32 bit */
15228  /* SPP_DMA2_TCDn Word3 - slast */
15229  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_31; /* offset: 0x13EC size: 32 bit */
15230  /* SPP_DMA2_TCDn Word4 - daddr */
15231  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_31; /* offset: 0x13F0 size: 32 bit */
15232  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15233  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_31; /* offset: 0x13F4 size: 32 bit */
15234  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15235  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_31; /* offset: 0x13F8 size: 32 bit */
15236  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15237  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_31; /* offset: 0x13FC size: 32 bit */
15238  /* SPP_DMA2_TCDn Word0 - Source Address */
15239  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_32; /* offset: 0x1400 size: 32 bit */
15240  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15241  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_32; /* offset: 0x1404 size: 32 bit */
15242  /* SPP_DMA2_TCDn Word2 - nbytes */
15243  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_32; /* offset: 0x1408 size: 32 bit */
15244  /* SPP_DMA2_TCDn Word3 - slast */
15245  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_32; /* offset: 0x140C size: 32 bit */
15246  /* SPP_DMA2_TCDn Word4 - daddr */
15247  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_32; /* offset: 0x1410 size: 32 bit */
15248  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15249  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_32; /* offset: 0x1414 size: 32 bit */
15250  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15251  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_32; /* offset: 0x1418 size: 32 bit */
15252  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15253  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_32; /* offset: 0x141C size: 32 bit */
15254  /* SPP_DMA2_TCDn Word0 - Source Address */
15255  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_33; /* offset: 0x1420 size: 32 bit */
15256  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15257  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_33; /* offset: 0x1424 size: 32 bit */
15258  /* SPP_DMA2_TCDn Word2 - nbytes */
15259  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_33; /* offset: 0x1428 size: 32 bit */
15260  /* SPP_DMA2_TCDn Word3 - slast */
15261  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_33; /* offset: 0x142C size: 32 bit */
15262  /* SPP_DMA2_TCDn Word4 - daddr */
15263  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_33; /* offset: 0x1430 size: 32 bit */
15264  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15265  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_33; /* offset: 0x1434 size: 32 bit */
15266  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15267  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_33; /* offset: 0x1438 size: 32 bit */
15268  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15269  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_33; /* offset: 0x143C size: 32 bit */
15270  /* SPP_DMA2_TCDn Word0 - Source Address */
15271  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_34; /* offset: 0x1440 size: 32 bit */
15272  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15273  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_34; /* offset: 0x1444 size: 32 bit */
15274  /* SPP_DMA2_TCDn Word2 - nbytes */
15275  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_34; /* offset: 0x1448 size: 32 bit */
15276  /* SPP_DMA2_TCDn Word3 - slast */
15277  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_34; /* offset: 0x144C size: 32 bit */
15278  /* SPP_DMA2_TCDn Word4 - daddr */
15279  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_34; /* offset: 0x1450 size: 32 bit */
15280  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15281  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_34; /* offset: 0x1454 size: 32 bit */
15282  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15283  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_34; /* offset: 0x1458 size: 32 bit */
15284  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15285  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_34; /* offset: 0x145C size: 32 bit */
15286  /* SPP_DMA2_TCDn Word0 - Source Address */
15287  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_35; /* offset: 0x1460 size: 32 bit */
15288  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15289  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_35; /* offset: 0x1464 size: 32 bit */
15290  /* SPP_DMA2_TCDn Word2 - nbytes */
15291  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_35; /* offset: 0x1468 size: 32 bit */
15292  /* SPP_DMA2_TCDn Word3 - slast */
15293  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_35; /* offset: 0x146C size: 32 bit */
15294  /* SPP_DMA2_TCDn Word4 - daddr */
15295  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_35; /* offset: 0x1470 size: 32 bit */
15296  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15297  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_35; /* offset: 0x1474 size: 32 bit */
15298  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15299  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_35; /* offset: 0x1478 size: 32 bit */
15300  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15301  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_35; /* offset: 0x147C size: 32 bit */
15302  /* SPP_DMA2_TCDn Word0 - Source Address */
15303  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_36; /* offset: 0x1480 size: 32 bit */
15304  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15305  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_36; /* offset: 0x1484 size: 32 bit */
15306  /* SPP_DMA2_TCDn Word2 - nbytes */
15307  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_36; /* offset: 0x1488 size: 32 bit */
15308  /* SPP_DMA2_TCDn Word3 - slast */
15309  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_36; /* offset: 0x148C size: 32 bit */
15310  /* SPP_DMA2_TCDn Word4 - daddr */
15311  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_36; /* offset: 0x1490 size: 32 bit */
15312  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15313  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_36; /* offset: 0x1494 size: 32 bit */
15314  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15315  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_36; /* offset: 0x1498 size: 32 bit */
15316  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15317  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_36; /* offset: 0x149C size: 32 bit */
15318  /* SPP_DMA2_TCDn Word0 - Source Address */
15319  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_37; /* offset: 0x14A0 size: 32 bit */
15320  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15321  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_37; /* offset: 0x14A4 size: 32 bit */
15322  /* SPP_DMA2_TCDn Word2 - nbytes */
15323  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_37; /* offset: 0x14A8 size: 32 bit */
15324  /* SPP_DMA2_TCDn Word3 - slast */
15325  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_37; /* offset: 0x14AC size: 32 bit */
15326  /* SPP_DMA2_TCDn Word4 - daddr */
15327  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_37; /* offset: 0x14B0 size: 32 bit */
15328  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15329  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_37; /* offset: 0x14B4 size: 32 bit */
15330  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15331  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_37; /* offset: 0x14B8 size: 32 bit */
15332  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15333  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_37; /* offset: 0x14BC size: 32 bit */
15334  /* SPP_DMA2_TCDn Word0 - Source Address */
15335  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_38; /* offset: 0x14C0 size: 32 bit */
15336  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15337  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_38; /* offset: 0x14C4 size: 32 bit */
15338  /* SPP_DMA2_TCDn Word2 - nbytes */
15339  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_38; /* offset: 0x14C8 size: 32 bit */
15340  /* SPP_DMA2_TCDn Word3 - slast */
15341  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_38; /* offset: 0x14CC size: 32 bit */
15342  /* SPP_DMA2_TCDn Word4 - daddr */
15343  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_38; /* offset: 0x14D0 size: 32 bit */
15344  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15345  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_38; /* offset: 0x14D4 size: 32 bit */
15346  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15347  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_38; /* offset: 0x14D8 size: 32 bit */
15348  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15349  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_38; /* offset: 0x14DC size: 32 bit */
15350  /* SPP_DMA2_TCDn Word0 - Source Address */
15351  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_39; /* offset: 0x14E0 size: 32 bit */
15352  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15353  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_39; /* offset: 0x14E4 size: 32 bit */
15354  /* SPP_DMA2_TCDn Word2 - nbytes */
15355  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_39; /* offset: 0x14E8 size: 32 bit */
15356  /* SPP_DMA2_TCDn Word3 - slast */
15357  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_39; /* offset: 0x14EC size: 32 bit */
15358  /* SPP_DMA2_TCDn Word4 - daddr */
15359  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_39; /* offset: 0x14F0 size: 32 bit */
15360  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15361  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_39; /* offset: 0x14F4 size: 32 bit */
15362  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15363  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_39; /* offset: 0x14F8 size: 32 bit */
15364  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15365  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_39; /* offset: 0x14FC size: 32 bit */
15366  /* SPP_DMA2_TCDn Word0 - Source Address */
15367  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_40; /* offset: 0x1500 size: 32 bit */
15368  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15369  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_40; /* offset: 0x1504 size: 32 bit */
15370  /* SPP_DMA2_TCDn Word2 - nbytes */
15371  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_40; /* offset: 0x1508 size: 32 bit */
15372  /* SPP_DMA2_TCDn Word3 - slast */
15373  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_40; /* offset: 0x150C size: 32 bit */
15374  /* SPP_DMA2_TCDn Word4 - daddr */
15375  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_40; /* offset: 0x1510 size: 32 bit */
15376  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15377  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_40; /* offset: 0x1514 size: 32 bit */
15378  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15379  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_40; /* offset: 0x1518 size: 32 bit */
15380  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15381  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_40; /* offset: 0x151C size: 32 bit */
15382  /* SPP_DMA2_TCDn Word0 - Source Address */
15383  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_41; /* offset: 0x1520 size: 32 bit */
15384  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15385  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_41; /* offset: 0x1524 size: 32 bit */
15386  /* SPP_DMA2_TCDn Word2 - nbytes */
15387  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_41; /* offset: 0x1528 size: 32 bit */
15388  /* SPP_DMA2_TCDn Word3 - slast */
15389  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_41; /* offset: 0x152C size: 32 bit */
15390  /* SPP_DMA2_TCDn Word4 - daddr */
15391  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_41; /* offset: 0x1530 size: 32 bit */
15392  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15393  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_41; /* offset: 0x1534 size: 32 bit */
15394  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15395  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_41; /* offset: 0x1538 size: 32 bit */
15396  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15397  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_41; /* offset: 0x153C size: 32 bit */
15398  /* SPP_DMA2_TCDn Word0 - Source Address */
15399  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_42; /* offset: 0x1540 size: 32 bit */
15400  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15401  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_42; /* offset: 0x1544 size: 32 bit */
15402  /* SPP_DMA2_TCDn Word2 - nbytes */
15403  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_42; /* offset: 0x1548 size: 32 bit */
15404  /* SPP_DMA2_TCDn Word3 - slast */
15405  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_42; /* offset: 0x154C size: 32 bit */
15406  /* SPP_DMA2_TCDn Word4 - daddr */
15407  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_42; /* offset: 0x1550 size: 32 bit */
15408  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15409  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_42; /* offset: 0x1554 size: 32 bit */
15410  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15411  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_42; /* offset: 0x1558 size: 32 bit */
15412  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15413  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_42; /* offset: 0x155C size: 32 bit */
15414  /* SPP_DMA2_TCDn Word0 - Source Address */
15415  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_43; /* offset: 0x1560 size: 32 bit */
15416  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15417  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_43; /* offset: 0x1564 size: 32 bit */
15418  /* SPP_DMA2_TCDn Word2 - nbytes */
15419  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_43; /* offset: 0x1568 size: 32 bit */
15420  /* SPP_DMA2_TCDn Word3 - slast */
15421  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_43; /* offset: 0x156C size: 32 bit */
15422  /* SPP_DMA2_TCDn Word4 - daddr */
15423  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_43; /* offset: 0x1570 size: 32 bit */
15424  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15425  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_43; /* offset: 0x1574 size: 32 bit */
15426  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15427  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_43; /* offset: 0x1578 size: 32 bit */
15428  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15429  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_43; /* offset: 0x157C size: 32 bit */
15430  /* SPP_DMA2_TCDn Word0 - Source Address */
15431  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_44; /* offset: 0x1580 size: 32 bit */
15432  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15433  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_44; /* offset: 0x1584 size: 32 bit */
15434  /* SPP_DMA2_TCDn Word2 - nbytes */
15435  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_44; /* offset: 0x1588 size: 32 bit */
15436  /* SPP_DMA2_TCDn Word3 - slast */
15437  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_44; /* offset: 0x158C size: 32 bit */
15438  /* SPP_DMA2_TCDn Word4 - daddr */
15439  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_44; /* offset: 0x1590 size: 32 bit */
15440  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15441  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_44; /* offset: 0x1594 size: 32 bit */
15442  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15443  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_44; /* offset: 0x1598 size: 32 bit */
15444  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15445  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_44; /* offset: 0x159C size: 32 bit */
15446  /* SPP_DMA2_TCDn Word0 - Source Address */
15447  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_45; /* offset: 0x15A0 size: 32 bit */
15448  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15449  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_45; /* offset: 0x15A4 size: 32 bit */
15450  /* SPP_DMA2_TCDn Word2 - nbytes */
15451  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_45; /* offset: 0x15A8 size: 32 bit */
15452  /* SPP_DMA2_TCDn Word3 - slast */
15453  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_45; /* offset: 0x15AC size: 32 bit */
15454  /* SPP_DMA2_TCDn Word4 - daddr */
15455  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_45; /* offset: 0x15B0 size: 32 bit */
15456  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15457  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_45; /* offset: 0x15B4 size: 32 bit */
15458  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15459  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_45; /* offset: 0x15B8 size: 32 bit */
15460  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15461  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_45; /* offset: 0x15BC size: 32 bit */
15462  /* SPP_DMA2_TCDn Word0 - Source Address */
15463  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_46; /* offset: 0x15C0 size: 32 bit */
15464  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15465  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_46; /* offset: 0x15C4 size: 32 bit */
15466  /* SPP_DMA2_TCDn Word2 - nbytes */
15467  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_46; /* offset: 0x15C8 size: 32 bit */
15468  /* SPP_DMA2_TCDn Word3 - slast */
15469  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_46; /* offset: 0x15CC size: 32 bit */
15470  /* SPP_DMA2_TCDn Word4 - daddr */
15471  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_46; /* offset: 0x15D0 size: 32 bit */
15472  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15473  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_46; /* offset: 0x15D4 size: 32 bit */
15474  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15475  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_46; /* offset: 0x15D8 size: 32 bit */
15476  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15477  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_46; /* offset: 0x15DC size: 32 bit */
15478  /* SPP_DMA2_TCDn Word0 - Source Address */
15479  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_47; /* offset: 0x15E0 size: 32 bit */
15480  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15481  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_47; /* offset: 0x15E4 size: 32 bit */
15482  /* SPP_DMA2_TCDn Word2 - nbytes */
15483  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_47; /* offset: 0x15E8 size: 32 bit */
15484  /* SPP_DMA2_TCDn Word3 - slast */
15485  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_47; /* offset: 0x15EC size: 32 bit */
15486  /* SPP_DMA2_TCDn Word4 - daddr */
15487  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_47; /* offset: 0x15F0 size: 32 bit */
15488  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15489  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_47; /* offset: 0x15F4 size: 32 bit */
15490  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15491  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_47; /* offset: 0x15F8 size: 32 bit */
15492  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15493  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_47; /* offset: 0x15FC size: 32 bit */
15494  /* SPP_DMA2_TCDn Word0 - Source Address */
15495  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_48; /* offset: 0x1600 size: 32 bit */
15496  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15497  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_48; /* offset: 0x1604 size: 32 bit */
15498  /* SPP_DMA2_TCDn Word2 - nbytes */
15499  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_48; /* offset: 0x1608 size: 32 bit */
15500  /* SPP_DMA2_TCDn Word3 - slast */
15501  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_48; /* offset: 0x160C size: 32 bit */
15502  /* SPP_DMA2_TCDn Word4 - daddr */
15503  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_48; /* offset: 0x1610 size: 32 bit */
15504  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15505  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_48; /* offset: 0x1614 size: 32 bit */
15506  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15507  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_48; /* offset: 0x1618 size: 32 bit */
15508  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15509  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_48; /* offset: 0x161C size: 32 bit */
15510  /* SPP_DMA2_TCDn Word0 - Source Address */
15511  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_49; /* offset: 0x1620 size: 32 bit */
15512  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15513  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_49; /* offset: 0x1624 size: 32 bit */
15514  /* SPP_DMA2_TCDn Word2 - nbytes */
15515  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_49; /* offset: 0x1628 size: 32 bit */
15516  /* SPP_DMA2_TCDn Word3 - slast */
15517  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_49; /* offset: 0x162C size: 32 bit */
15518  /* SPP_DMA2_TCDn Word4 - daddr */
15519  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_49; /* offset: 0x1630 size: 32 bit */
15520  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15521  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_49; /* offset: 0x1634 size: 32 bit */
15522  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15523  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_49; /* offset: 0x1638 size: 32 bit */
15524  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15525  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_49; /* offset: 0x163C size: 32 bit */
15526  /* SPP_DMA2_TCDn Word0 - Source Address */
15527  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_50; /* offset: 0x1640 size: 32 bit */
15528  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15529  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_50; /* offset: 0x1644 size: 32 bit */
15530  /* SPP_DMA2_TCDn Word2 - nbytes */
15531  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_50; /* offset: 0x1648 size: 32 bit */
15532  /* SPP_DMA2_TCDn Word3 - slast */
15533  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_50; /* offset: 0x164C size: 32 bit */
15534  /* SPP_DMA2_TCDn Word4 - daddr */
15535  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_50; /* offset: 0x1650 size: 32 bit */
15536  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15537  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_50; /* offset: 0x1654 size: 32 bit */
15538  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15539  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_50; /* offset: 0x1658 size: 32 bit */
15540  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15541  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_50; /* offset: 0x165C size: 32 bit */
15542  /* SPP_DMA2_TCDn Word0 - Source Address */
15543  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_51; /* offset: 0x1660 size: 32 bit */
15544  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15545  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_51; /* offset: 0x1664 size: 32 bit */
15546  /* SPP_DMA2_TCDn Word2 - nbytes */
15547  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_51; /* offset: 0x1668 size: 32 bit */
15548  /* SPP_DMA2_TCDn Word3 - slast */
15549  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_51; /* offset: 0x166C size: 32 bit */
15550  /* SPP_DMA2_TCDn Word4 - daddr */
15551  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_51; /* offset: 0x1670 size: 32 bit */
15552  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15553  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_51; /* offset: 0x1674 size: 32 bit */
15554  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15555  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_51; /* offset: 0x1678 size: 32 bit */
15556  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15557  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_51; /* offset: 0x167C size: 32 bit */
15558  /* SPP_DMA2_TCDn Word0 - Source Address */
15559  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_52; /* offset: 0x1680 size: 32 bit */
15560  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15561  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_52; /* offset: 0x1684 size: 32 bit */
15562  /* SPP_DMA2_TCDn Word2 - nbytes */
15563  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_52; /* offset: 0x1688 size: 32 bit */
15564  /* SPP_DMA2_TCDn Word3 - slast */
15565  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_52; /* offset: 0x168C size: 32 bit */
15566  /* SPP_DMA2_TCDn Word4 - daddr */
15567  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_52; /* offset: 0x1690 size: 32 bit */
15568  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15569  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_52; /* offset: 0x1694 size: 32 bit */
15570  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15571  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_52; /* offset: 0x1698 size: 32 bit */
15572  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15573  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_52; /* offset: 0x169C size: 32 bit */
15574  /* SPP_DMA2_TCDn Word0 - Source Address */
15575  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_53; /* offset: 0x16A0 size: 32 bit */
15576  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15577  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_53; /* offset: 0x16A4 size: 32 bit */
15578  /* SPP_DMA2_TCDn Word2 - nbytes */
15579  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_53; /* offset: 0x16A8 size: 32 bit */
15580  /* SPP_DMA2_TCDn Word3 - slast */
15581  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_53; /* offset: 0x16AC size: 32 bit */
15582  /* SPP_DMA2_TCDn Word4 - daddr */
15583  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_53; /* offset: 0x16B0 size: 32 bit */
15584  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15585  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_53; /* offset: 0x16B4 size: 32 bit */
15586  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15587  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_53; /* offset: 0x16B8 size: 32 bit */
15588  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15589  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_53; /* offset: 0x16BC size: 32 bit */
15590  /* SPP_DMA2_TCDn Word0 - Source Address */
15591  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_54; /* offset: 0x16C0 size: 32 bit */
15592  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15593  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_54; /* offset: 0x16C4 size: 32 bit */
15594  /* SPP_DMA2_TCDn Word2 - nbytes */
15595  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_54; /* offset: 0x16C8 size: 32 bit */
15596  /* SPP_DMA2_TCDn Word3 - slast */
15597  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_54; /* offset: 0x16CC size: 32 bit */
15598  /* SPP_DMA2_TCDn Word4 - daddr */
15599  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_54; /* offset: 0x16D0 size: 32 bit */
15600  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15601  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_54; /* offset: 0x16D4 size: 32 bit */
15602  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15603  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_54; /* offset: 0x16D8 size: 32 bit */
15604  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15605  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_54; /* offset: 0x16DC size: 32 bit */
15606  /* SPP_DMA2_TCDn Word0 - Source Address */
15607  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_55; /* offset: 0x16E0 size: 32 bit */
15608  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15609  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_55; /* offset: 0x16E4 size: 32 bit */
15610  /* SPP_DMA2_TCDn Word2 - nbytes */
15611  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_55; /* offset: 0x16E8 size: 32 bit */
15612  /* SPP_DMA2_TCDn Word3 - slast */
15613  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_55; /* offset: 0x16EC size: 32 bit */
15614  /* SPP_DMA2_TCDn Word4 - daddr */
15615  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_55; /* offset: 0x16F0 size: 32 bit */
15616  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15617  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_55; /* offset: 0x16F4 size: 32 bit */
15618  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15619  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_55; /* offset: 0x16F8 size: 32 bit */
15620  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15621  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_55; /* offset: 0x16FC size: 32 bit */
15622  /* SPP_DMA2_TCDn Word0 - Source Address */
15623  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_56; /* offset: 0x1700 size: 32 bit */
15624  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15625  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_56; /* offset: 0x1704 size: 32 bit */
15626  /* SPP_DMA2_TCDn Word2 - nbytes */
15627  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_56; /* offset: 0x1708 size: 32 bit */
15628  /* SPP_DMA2_TCDn Word3 - slast */
15629  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_56; /* offset: 0x170C size: 32 bit */
15630  /* SPP_DMA2_TCDn Word4 - daddr */
15631  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_56; /* offset: 0x1710 size: 32 bit */
15632  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15633  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_56; /* offset: 0x1714 size: 32 bit */
15634  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15635  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_56; /* offset: 0x1718 size: 32 bit */
15636  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15637  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_56; /* offset: 0x171C size: 32 bit */
15638  /* SPP_DMA2_TCDn Word0 - Source Address */
15639  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_57; /* offset: 0x1720 size: 32 bit */
15640  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15641  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_57; /* offset: 0x1724 size: 32 bit */
15642  /* SPP_DMA2_TCDn Word2 - nbytes */
15643  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_57; /* offset: 0x1728 size: 32 bit */
15644  /* SPP_DMA2_TCDn Word3 - slast */
15645  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_57; /* offset: 0x172C size: 32 bit */
15646  /* SPP_DMA2_TCDn Word4 - daddr */
15647  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_57; /* offset: 0x1730 size: 32 bit */
15648  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15649  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_57; /* offset: 0x1734 size: 32 bit */
15650  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15651  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_57; /* offset: 0x1738 size: 32 bit */
15652  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15653  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_57; /* offset: 0x173C size: 32 bit */
15654  /* SPP_DMA2_TCDn Word0 - Source Address */
15655  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_58; /* offset: 0x1740 size: 32 bit */
15656  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15657  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_58; /* offset: 0x1744 size: 32 bit */
15658  /* SPP_DMA2_TCDn Word2 - nbytes */
15659  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_58; /* offset: 0x1748 size: 32 bit */
15660  /* SPP_DMA2_TCDn Word3 - slast */
15661  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_58; /* offset: 0x174C size: 32 bit */
15662  /* SPP_DMA2_TCDn Word4 - daddr */
15663  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_58; /* offset: 0x1750 size: 32 bit */
15664  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15665  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_58; /* offset: 0x1754 size: 32 bit */
15666  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15667  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_58; /* offset: 0x1758 size: 32 bit */
15668  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15669  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_58; /* offset: 0x175C size: 32 bit */
15670  /* SPP_DMA2_TCDn Word0 - Source Address */
15671  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_59; /* offset: 0x1760 size: 32 bit */
15672  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15673  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_59; /* offset: 0x1764 size: 32 bit */
15674  /* SPP_DMA2_TCDn Word2 - nbytes */
15675  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_59; /* offset: 0x1768 size: 32 bit */
15676  /* SPP_DMA2_TCDn Word3 - slast */
15677  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_59; /* offset: 0x176C size: 32 bit */
15678  /* SPP_DMA2_TCDn Word4 - daddr */
15679  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_59; /* offset: 0x1770 size: 32 bit */
15680  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15681  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_59; /* offset: 0x1774 size: 32 bit */
15682  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15683  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_59; /* offset: 0x1778 size: 32 bit */
15684  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15685  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_59; /* offset: 0x177C size: 32 bit */
15686  /* SPP_DMA2_TCDn Word0 - Source Address */
15687  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_60; /* offset: 0x1780 size: 32 bit */
15688  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15689  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_60; /* offset: 0x1784 size: 32 bit */
15690  /* SPP_DMA2_TCDn Word2 - nbytes */
15691  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_60; /* offset: 0x1788 size: 32 bit */
15692  /* SPP_DMA2_TCDn Word3 - slast */
15693  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_60; /* offset: 0x178C size: 32 bit */
15694  /* SPP_DMA2_TCDn Word4 - daddr */
15695  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_60; /* offset: 0x1790 size: 32 bit */
15696  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15697  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_60; /* offset: 0x1794 size: 32 bit */
15698  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15699  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_60; /* offset: 0x1798 size: 32 bit */
15700  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15701  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_60; /* offset: 0x179C size: 32 bit */
15702  /* SPP_DMA2_TCDn Word0 - Source Address */
15703  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_61; /* offset: 0x17A0 size: 32 bit */
15704  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15705  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_61; /* offset: 0x17A4 size: 32 bit */
15706  /* SPP_DMA2_TCDn Word2 - nbytes */
15707  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_61; /* offset: 0x17A8 size: 32 bit */
15708  /* SPP_DMA2_TCDn Word3 - slast */
15709  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_61; /* offset: 0x17AC size: 32 bit */
15710  /* SPP_DMA2_TCDn Word4 - daddr */
15711  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_61; /* offset: 0x17B0 size: 32 bit */
15712  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15713  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_61; /* offset: 0x17B4 size: 32 bit */
15714  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15715  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_61; /* offset: 0x17B8 size: 32 bit */
15716  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15717  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_61; /* offset: 0x17BC size: 32 bit */
15718  /* SPP_DMA2_TCDn Word0 - Source Address */
15719  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_62; /* offset: 0x17C0 size: 32 bit */
15720  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15721  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_62; /* offset: 0x17C4 size: 32 bit */
15722  /* SPP_DMA2_TCDn Word2 - nbytes */
15723  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_62; /* offset: 0x17C8 size: 32 bit */
15724  /* SPP_DMA2_TCDn Word3 - slast */
15725  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_62; /* offset: 0x17CC size: 32 bit */
15726  /* SPP_DMA2_TCDn Word4 - daddr */
15727  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_62; /* offset: 0x17D0 size: 32 bit */
15728  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15729  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_62; /* offset: 0x17D4 size: 32 bit */
15730  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15731  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_62; /* offset: 0x17D8 size: 32 bit */
15732  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15733  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_62; /* offset: 0x17DC size: 32 bit */
15734  /* SPP_DMA2_TCDn Word0 - Source Address */
15735  SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_63; /* offset: 0x17E0 size: 32 bit */
15736  /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
15737  SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_63; /* offset: 0x17E4 size: 32 bit */
15738  /* SPP_DMA2_TCDn Word2 - nbytes */
15739  SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_63; /* offset: 0x17E8 size: 32 bit */
15740  /* SPP_DMA2_TCDn Word3 - slast */
15741  SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_63; /* offset: 0x17EC size: 32 bit */
15742  /* SPP_DMA2_TCDn Word4 - daddr */
15743  SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_63; /* offset: 0x17F0 size: 32 bit */
15744  /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
15745  SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_63; /* offset: 0x17F4 size: 32 bit */
15746  /* SPP_DMA2_TCDn Word6 - dlast_sga */
15747  SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_63; /* offset: 0x17F8 size: 32 bit */
15748  /* SPP_DMA2_TCDn Word7 - biter, etc. */
15749  SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_63; /* offset: 0x17FC size: 32 bit */
15750  };
15751 
15752  };
15753  } SPP_DMA2_tag;
15754 
15755 
15756 #define SPP_DMA2 (*(volatile SPP_DMA2_tag *) 0xFFF44000UL)
15757 
15758 
15759 
15760 /****************************************************************/
15761 /* */
15762 /* Module: INTC */
15763 /* */
15764 /****************************************************************/
15765 
15766  typedef union { /* BCR - Block Configuration Register */
15767  vuint32_t R;
15768  struct {
15769  vuint32_t:18;
15770  vuint32_t VTES_PRC1:1; /* Vector Table Entry Size - Processor 1 */
15771  vuint32_t:4;
15772  vuint32_t HVEN_PRC1:1; /* Hardware Vector Enable - Processor 1 */
15773  vuint32_t:2;
15774 #ifndef USE_FIELD_ALIASES_INTC
15775  vuint32_t VTES_PRC0:1; /* Vector Table Entry Size - Processor 0 */
15776 #else
15777  vuint32_t VTES:1; /* deprecated name - please avoid */
15778 #endif
15779  vuint32_t:4;
15780 #ifndef USE_FIELD_ALIASES_INTC
15781  vuint32_t HVEN_PRC0:1; /* Hardware Vector Enable - Processor 0 */
15782 #else
15783  vuint32_t HVEN:1; /* deprecated name - please avoid */
15784 #endif
15785  } B;
15786  } INTC_BCR_32B_tag;
15787 
15788  typedef union { /* CPR - Current Priority Register - Processor 0 */
15789  vuint32_t R;
15790  struct {
15791  vuint32_t:28;
15792  vuint32_t PRI:4; /* Priority Bits */
15793  } B;
15794  } INTC_CPR_PRC0_32B_tag;
15795 
15796  typedef union { /* CPR - Current Priority Register - Processor 1 */
15797  vuint32_t R;
15798  struct {
15799  vuint32_t:28;
15800  vuint32_t PRI:4; /* Priority Bits */
15801  } B;
15802  } INTC_CPR_PRC1_32B_tag;
15803 
15804  typedef union { /* IACKR- Interrupt Acknowledge Register - Processor 0 */
15805  vuint32_t R;
15806  struct {
15807 #ifndef USE_FIELD_ALIASES_INTC
15808  vuint32_t VTBA_PRC0:21; /* Vector Table Base Address - Processor 0 */
15809 #else
15810  vuint32_t VTBA:21; /* deprecated name - please avoid */
15811 #endif
15812 #ifndef USE_FIELD_ALIASES_INTC
15813  vuint32_t INTEC_PRC0:9; /* Interrupt Vector - Processor 0 */
15814 #else
15815  vuint32_t INTVEC:9; /* deprecated name - please avoid */
15816 #endif
15817  vuint32_t:2;
15818  } B;
15819  } INTC_IACKR_PRC0_32B_tag;
15820 
15821  typedef union { /* IACKR- Interrupt Acknowledge Register - Processor 1 */
15822  vuint32_t R;
15823  struct {
15824  vuint32_t VTBA_PRC1:21; /* Vector Table Base Address - Processor 1 */
15825  vuint32_t INTEC_PRC1:9; /* Interrupt Vector - Processor 1 */
15826  vuint32_t:2;
15827  } B;
15828  } INTC_IACKR_PRC1_32B_tag;
15829 
15830  typedef union { /* EOIR- End of Interrupt Register - Processor 0 */
15831  vuint32_t R;
15832  } INTC_EOIR_PRC0_32B_tag;
15833 
15834  typedef union { /* EOIR- End of Interrupt Register - Processor 1 */
15835  vuint32_t R;
15836  } INTC_EOIR_PRC1_32B_tag;
15837 
15838 
15839  /* Register layout for all registers SSCIR... */
15840 
15841  typedef union { /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */
15842  vuint8_t R;
15843  struct {
15844  vuint8_t:6;
15845  vuint8_t SET:1; /* Set Flag bit */
15846  vuint8_t CLR:1; /* Clear Flag bit */
15847  } B;
15848  } INTC_SSCIR_8B_tag;
15849 
15850  typedef union { /* SSCIR0_3 - Software Set/Clear Interrupt Registers */
15851  vuint32_t R;
15852  struct {
15853  vuint32_t:6;
15854  vuint32_t SET0:1; /* Set Flag 0 bit */
15855  vuint32_t CLR0:1; /* Clear Flag 0 bit */
15856  vuint32_t:6;
15857  vuint32_t SET1:1; /* Set Flag 1 bit */
15858  vuint32_t CLR1:1; /* Clear Flag 1 bit */
15859  vuint32_t:6;
15860  vuint32_t SET2:1; /* Set Flag 2 bit */
15861  vuint32_t CLR2:1; /* Clear Flag 2 bit */
15862  vuint32_t:6;
15863  vuint32_t SET3:1; /* Set Flag 3 bit */
15864  vuint32_t CLR3:1; /* Clear Flag 3 bit */
15865  } B;
15866  } INTC_SSCIR0_3_32B_tag;
15867 
15868  typedef union { /* SSCIR4_7 - Software Set/Clear Interrupt Registers */
15869  vuint32_t R;
15870  struct {
15871  vuint32_t:6;
15872  vuint32_t SET4:1; /* Set Flag 4 bit */
15873  vuint32_t CLR4:1; /* Clear Flag 4 bit */
15874  vuint32_t:6;
15875  vuint32_t SET5:1; /* Set Flag 5 bit */
15876  vuint32_t CLR5:1; /* Clear Flag 5 bit */
15877  vuint32_t:6;
15878  vuint32_t SET6:1; /* Set Flag 6 bit */
15879  vuint32_t CLR6:1; /* Clear Flag 6 bit */
15880  vuint32_t:6;
15881  vuint32_t SET7:1; /* Set Flag 7 bit */
15882  vuint32_t CLR7:1; /* Clear Flag 7 bit */
15883  } B;
15884  } INTC_SSCIR4_7_32B_tag;
15885 
15886 
15887  /* Register layout for all registers PSR... */
15888 
15889  typedef union { /* PSR0-511 - Priority Select Registers */
15890  vuint8_t R;
15891  struct {
15892  vuint8_t PRC_SEL:2; /* Processor Select */
15893  vuint8_t:2;
15894  vuint8_t PRI:4; /* Priority Select */
15895  } B;
15896  } INTC_PSR_8B_tag;
15897 
15898 
15899  /* Register layout for all registers PSR... */
15900 
15901  typedef union { /* PSR0_3 - 508_511 - Priority Select Registers */
15902  vuint32_t R;
15903  struct {
15904  vuint32_t PRC_SEL0:2; /* Processor Select - Entry 0 */
15905  vuint32_t:2;
15906  vuint32_t PRI0:4; /* Priority Select - Entry 0 */
15907  vuint32_t PRC_SEL1:2; /* Processor Select - Entry 1 */
15908  vuint32_t:2;
15909  vuint32_t PRI1:4; /* Priority Select - Entry 1 */
15910  vuint32_t PRC_SEL2:2; /* Processor Select - Entry 2 */
15911  vuint32_t:2;
15912  vuint32_t PRI2:4; /* Priority Select - Entry 2 */
15913  vuint32_t PRC_SEL3:2; /* Processor Select - Entry 3 */
15914  vuint32_t:2;
15915  vuint32_t PRI3:4; /* Priority Select - Entry 3 */
15916  } B;
15917  } INTC_PSR_32B_tag;
15918 
15919 
15920 
15921  typedef struct INTC_struct_tag { /* start of INTC_tag */
15922  union {
15923  INTC_BCR_32B_tag MCR; /* deprecated - please avoid */
15924 
15925  /* BCR - Block Configuration Register */
15926  INTC_BCR_32B_tag BCR; /* offset: 0x0000 size: 32 bit */
15927 
15928  };
15929  int8_t INTC_reserved_0004_C[4];
15930  union {
15931  /* CPR - Current Priority Register - Processor 0 */
15932  INTC_CPR_PRC0_32B_tag CPR_PRC0; /* offset: 0x0008 size: 32 bit */
15933 
15934  INTC_CPR_PRC0_32B_tag CPR; /* deprecated - please avoid */
15935 
15936  };
15937  /* CPR - Current Priority Register - Processor 1 */
15938  INTC_CPR_PRC1_32B_tag CPR_PRC1; /* offset: 0x000C size: 32 bit */
15939  union {
15940  /* IACKR- Interrupt Acknowledge Register - Processor 0 */
15941  INTC_IACKR_PRC0_32B_tag IACKR_PRC0; /* offset: 0x0010 size: 32 bit */
15942 
15943  INTC_IACKR_PRC0_32B_tag IACKR; /* deprecated - please avoid */
15944 
15945  };
15946  /* IACKR- Interrupt Acknowledge Register - Processor 1 */
15947  INTC_IACKR_PRC1_32B_tag IACKR_PRC1; /* offset: 0x0014 size: 32 bit */
15948  union {
15949  /* EOIR- End of Interrupt Register - Processor 0 */
15950  INTC_EOIR_PRC0_32B_tag EOIR_PRC0; /* offset: 0x0018 size: 32 bit */
15951 
15952  INTC_EOIR_PRC0_32B_tag EOIR; /* deprecated - please avoid */
15953 
15954  };
15955  /* EOIR- End of Interrupt Register - Processor 1 */
15956  INTC_EOIR_PRC1_32B_tag EOIR_PRC1; /* offset: 0x001C size: 32 bit */
15957  union {
15958  /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */
15959  INTC_SSCIR_8B_tag SSCIR[8]; /* offset: 0x0020 (0x0001 x 8) */
15960 
15961  struct {
15962  /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */
15963  INTC_SSCIR_8B_tag SSCIR0; /* offset: 0x0020 size: 8 bit */
15964  INTC_SSCIR_8B_tag SSCIR1; /* offset: 0x0021 size: 8 bit */
15965  INTC_SSCIR_8B_tag SSCIR2; /* offset: 0x0022 size: 8 bit */
15966  INTC_SSCIR_8B_tag SSCIR3; /* offset: 0x0023 size: 8 bit */
15967  INTC_SSCIR_8B_tag SSCIR4; /* offset: 0x0024 size: 8 bit */
15968  INTC_SSCIR_8B_tag SSCIR5; /* offset: 0x0025 size: 8 bit */
15969  INTC_SSCIR_8B_tag SSCIR6; /* offset: 0x0026 size: 8 bit */
15970  INTC_SSCIR_8B_tag SSCIR7; /* offset: 0x0027 size: 8 bit */
15971  };
15972 
15973  struct {
15974  /* SSCIR0_3 - Software Set/Clear Interrupt Registers */
15975  INTC_SSCIR0_3_32B_tag SSCIR0_3; /* offset: 0x0020 size: 32 bit */
15976  /* SSCIR4_7 - Software Set/Clear Interrupt Registers */
15977  INTC_SSCIR4_7_32B_tag SSCIR4_7; /* offset: 0x0024 size: 32 bit */
15978  };
15979 
15980  };
15981  int8_t INTC_reserved_0028_C[24];
15982  union {
15983  /* PSR0_3 - 508_511 - Priority Select Registers */
15984  INTC_PSR_32B_tag PSR_32B[128]; /* offset: 0x0040 (0x0004 x 128) */
15985 
15986  /* PSR0-511 - Priority Select Registers */
15987  INTC_PSR_8B_tag PSR[512]; /* offset: 0x0040 (0x0001 x 512) */
15988 
15989  struct {
15990  /* PSR0_3 - 508_511 - Priority Select Registers */
15991  INTC_PSR_32B_tag PSR0_3; /* offset: 0x0040 size: 32 bit */
15992  INTC_PSR_32B_tag PSR4_7; /* offset: 0x0044 size: 32 bit */
15993  INTC_PSR_32B_tag PSR8_11; /* offset: 0x0048 size: 32 bit */
15994  INTC_PSR_32B_tag PSR12_15; /* offset: 0x004C size: 32 bit */
15995  INTC_PSR_32B_tag PSR16_19; /* offset: 0x0050 size: 32 bit */
15996  INTC_PSR_32B_tag PSR20_23; /* offset: 0x0054 size: 32 bit */
15997  INTC_PSR_32B_tag PSR24_27; /* offset: 0x0058 size: 32 bit */
15998  INTC_PSR_32B_tag PSR28_31; /* offset: 0x005C size: 32 bit */
15999  INTC_PSR_32B_tag PSR32_35; /* offset: 0x0060 size: 32 bit */
16000  INTC_PSR_32B_tag PSR36_39; /* offset: 0x0064 size: 32 bit */
16001  INTC_PSR_32B_tag PSR40_43; /* offset: 0x0068 size: 32 bit */
16002  INTC_PSR_32B_tag PSR44_47; /* offset: 0x006C size: 32 bit */
16003  INTC_PSR_32B_tag PSR48_51; /* offset: 0x0070 size: 32 bit */
16004  INTC_PSR_32B_tag PSR52_55; /* offset: 0x0074 size: 32 bit */
16005  INTC_PSR_32B_tag PSR56_59; /* offset: 0x0078 size: 32 bit */
16006  INTC_PSR_32B_tag PSR60_63; /* offset: 0x007C size: 32 bit */
16007  INTC_PSR_32B_tag PSR64_67; /* offset: 0x0080 size: 32 bit */
16008  INTC_PSR_32B_tag PSR68_71; /* offset: 0x0084 size: 32 bit */
16009  INTC_PSR_32B_tag PSR72_75; /* offset: 0x0088 size: 32 bit */
16010  INTC_PSR_32B_tag PSR76_79; /* offset: 0x008C size: 32 bit */
16011  INTC_PSR_32B_tag PSR80_83; /* offset: 0x0090 size: 32 bit */
16012  INTC_PSR_32B_tag PSR84_87; /* offset: 0x0094 size: 32 bit */
16013  INTC_PSR_32B_tag PSR88_91; /* offset: 0x0098 size: 32 bit */
16014  INTC_PSR_32B_tag PSR92_95; /* offset: 0x009C size: 32 bit */
16015  INTC_PSR_32B_tag PSR96_99; /* offset: 0x00A0 size: 32 bit */
16016  INTC_PSR_32B_tag PSR100_103; /* offset: 0x00A4 size: 32 bit */
16017  INTC_PSR_32B_tag PSR104_107; /* offset: 0x00A8 size: 32 bit */
16018  INTC_PSR_32B_tag PSR108_111; /* offset: 0x00AC size: 32 bit */
16019  INTC_PSR_32B_tag PSR112_115; /* offset: 0x00B0 size: 32 bit */
16020  INTC_PSR_32B_tag PSR116_119; /* offset: 0x00B4 size: 32 bit */
16021  INTC_PSR_32B_tag PSR120_123; /* offset: 0x00B8 size: 32 bit */
16022  INTC_PSR_32B_tag PSR124_127; /* offset: 0x00BC size: 32 bit */
16023  INTC_PSR_32B_tag PSR128_131; /* offset: 0x00C0 size: 32 bit */
16024  INTC_PSR_32B_tag PSR132_135; /* offset: 0x00C4 size: 32 bit */
16025  INTC_PSR_32B_tag PSR136_139; /* offset: 0x00C8 size: 32 bit */
16026  INTC_PSR_32B_tag PSR140_143; /* offset: 0x00CC size: 32 bit */
16027  INTC_PSR_32B_tag PSR144_147; /* offset: 0x00D0 size: 32 bit */
16028  INTC_PSR_32B_tag PSR148_151; /* offset: 0x00D4 size: 32 bit */
16029  INTC_PSR_32B_tag PSR152_155; /* offset: 0x00D8 size: 32 bit */
16030  INTC_PSR_32B_tag PSR156_159; /* offset: 0x00DC size: 32 bit */
16031  INTC_PSR_32B_tag PSR160_163; /* offset: 0x00E0 size: 32 bit */
16032  INTC_PSR_32B_tag PSR164_167; /* offset: 0x00E4 size: 32 bit */
16033  INTC_PSR_32B_tag PSR168_171; /* offset: 0x00E8 size: 32 bit */
16034  INTC_PSR_32B_tag PSR172_175; /* offset: 0x00EC size: 32 bit */
16035  INTC_PSR_32B_tag PSR176_179; /* offset: 0x00F0 size: 32 bit */
16036  INTC_PSR_32B_tag PSR180_183; /* offset: 0x00F4 size: 32 bit */
16037  INTC_PSR_32B_tag PSR184_187; /* offset: 0x00F8 size: 32 bit */
16038  INTC_PSR_32B_tag PSR188_191; /* offset: 0x00FC size: 32 bit */
16039  INTC_PSR_32B_tag PSR192_195; /* offset: 0x0100 size: 32 bit */
16040  INTC_PSR_32B_tag PSR196_199; /* offset: 0x0104 size: 32 bit */
16041  INTC_PSR_32B_tag PSR200_203; /* offset: 0x0108 size: 32 bit */
16042  INTC_PSR_32B_tag PSR204_207; /* offset: 0x010C size: 32 bit */
16043  INTC_PSR_32B_tag PSR208_211; /* offset: 0x0110 size: 32 bit */
16044  INTC_PSR_32B_tag PSR212_215; /* offset: 0x0114 size: 32 bit */
16045  INTC_PSR_32B_tag PSR216_219; /* offset: 0x0118 size: 32 bit */
16046  INTC_PSR_32B_tag PSR220_223; /* offset: 0x011C size: 32 bit */
16047  INTC_PSR_32B_tag PSR224_227; /* offset: 0x0120 size: 32 bit */
16048  INTC_PSR_32B_tag PSR228_231; /* offset: 0x0124 size: 32 bit */
16049  INTC_PSR_32B_tag PSR232_235; /* offset: 0x0128 size: 32 bit */
16050  INTC_PSR_32B_tag PSR236_239; /* offset: 0x012C size: 32 bit */
16051  INTC_PSR_32B_tag PSR240_243; /* offset: 0x0130 size: 32 bit */
16052  INTC_PSR_32B_tag PSR244_247; /* offset: 0x0134 size: 32 bit */
16053  INTC_PSR_32B_tag PSR248_251; /* offset: 0x0138 size: 32 bit */
16054  INTC_PSR_32B_tag PSR252_255; /* offset: 0x013C size: 32 bit */
16055  INTC_PSR_32B_tag PSR256_259; /* offset: 0x0140 size: 32 bit */
16056  INTC_PSR_32B_tag PSR260_263; /* offset: 0x0144 size: 32 bit */
16057  INTC_PSR_32B_tag PSR264_267; /* offset: 0x0148 size: 32 bit */
16058  INTC_PSR_32B_tag PSR268_271; /* offset: 0x014C size: 32 bit */
16059  INTC_PSR_32B_tag PSR272_275; /* offset: 0x0150 size: 32 bit */
16060  INTC_PSR_32B_tag PSR276_279; /* offset: 0x0154 size: 32 bit */
16061  INTC_PSR_32B_tag PSR280_283; /* offset: 0x0158 size: 32 bit */
16062  INTC_PSR_32B_tag PSR284_287; /* offset: 0x015C size: 32 bit */
16063  INTC_PSR_32B_tag PSR288_291; /* offset: 0x0160 size: 32 bit */
16064  INTC_PSR_32B_tag PSR292_295; /* offset: 0x0164 size: 32 bit */
16065  INTC_PSR_32B_tag PSR296_299; /* offset: 0x0168 size: 32 bit */
16066  INTC_PSR_32B_tag PSR300_303; /* offset: 0x016C size: 32 bit */
16067  INTC_PSR_32B_tag PSR304_307; /* offset: 0x0170 size: 32 bit */
16068  INTC_PSR_32B_tag PSR308_311; /* offset: 0x0174 size: 32 bit */
16069  INTC_PSR_32B_tag PSR312_315; /* offset: 0x0178 size: 32 bit */
16070  INTC_PSR_32B_tag PSR316_319; /* offset: 0x017C size: 32 bit */
16071  INTC_PSR_32B_tag PSR320_323; /* offset: 0x0180 size: 32 bit */
16072  INTC_PSR_32B_tag PSR324_327; /* offset: 0x0184 size: 32 bit */
16073  INTC_PSR_32B_tag PSR328_331; /* offset: 0x0188 size: 32 bit */
16074  INTC_PSR_32B_tag PSR332_335; /* offset: 0x018C size: 32 bit */
16075  INTC_PSR_32B_tag PSR336_339; /* offset: 0x0190 size: 32 bit */
16076  INTC_PSR_32B_tag PSR340_343; /* offset: 0x0194 size: 32 bit */
16077  INTC_PSR_32B_tag PSR344_347; /* offset: 0x0198 size: 32 bit */
16078  INTC_PSR_32B_tag PSR348_351; /* offset: 0x019C size: 32 bit */
16079  INTC_PSR_32B_tag PSR352_355; /* offset: 0x01A0 size: 32 bit */
16080  INTC_PSR_32B_tag PSR356_359; /* offset: 0x01A4 size: 32 bit */
16081  INTC_PSR_32B_tag PSR360_363; /* offset: 0x01A8 size: 32 bit */
16082  INTC_PSR_32B_tag PSR364_367; /* offset: 0x01AC size: 32 bit */
16083  INTC_PSR_32B_tag PSR368_371; /* offset: 0x01B0 size: 32 bit */
16084  INTC_PSR_32B_tag PSR372_375; /* offset: 0x01B4 size: 32 bit */
16085  INTC_PSR_32B_tag PSR376_379; /* offset: 0x01B8 size: 32 bit */
16086  INTC_PSR_32B_tag PSR380_383; /* offset: 0x01BC size: 32 bit */
16087  INTC_PSR_32B_tag PSR384_387; /* offset: 0x01C0 size: 32 bit */
16088  INTC_PSR_32B_tag PSR388_391; /* offset: 0x01C4 size: 32 bit */
16089  INTC_PSR_32B_tag PSR392_395; /* offset: 0x01C8 size: 32 bit */
16090  INTC_PSR_32B_tag PSR396_399; /* offset: 0x01CC size: 32 bit */
16091  INTC_PSR_32B_tag PSR400_403; /* offset: 0x01D0 size: 32 bit */
16092  INTC_PSR_32B_tag PSR404_407; /* offset: 0x01D4 size: 32 bit */
16093  INTC_PSR_32B_tag PSR408_411; /* offset: 0x01D8 size: 32 bit */
16094  INTC_PSR_32B_tag PSR412_415; /* offset: 0x01DC size: 32 bit */
16095  INTC_PSR_32B_tag PSR416_419; /* offset: 0x01E0 size: 32 bit */
16096  INTC_PSR_32B_tag PSR420_423; /* offset: 0x01E4 size: 32 bit */
16097  INTC_PSR_32B_tag PSR424_427; /* offset: 0x01E8 size: 32 bit */
16098  INTC_PSR_32B_tag PSR428_431; /* offset: 0x01EC size: 32 bit */
16099  INTC_PSR_32B_tag PSR432_435; /* offset: 0x01F0 size: 32 bit */
16100  INTC_PSR_32B_tag PSR436_439; /* offset: 0x01F4 size: 32 bit */
16101  INTC_PSR_32B_tag PSR440_443; /* offset: 0x01F8 size: 32 bit */
16102  INTC_PSR_32B_tag PSR444_447; /* offset: 0x01FC size: 32 bit */
16103  INTC_PSR_32B_tag PSR448_451; /* offset: 0x0200 size: 32 bit */
16104  INTC_PSR_32B_tag PSR452_455; /* offset: 0x0204 size: 32 bit */
16105  INTC_PSR_32B_tag PSR456_459; /* offset: 0x0208 size: 32 bit */
16106  INTC_PSR_32B_tag PSR460_463; /* offset: 0x020C size: 32 bit */
16107  INTC_PSR_32B_tag PSR464_467; /* offset: 0x0210 size: 32 bit */
16108  INTC_PSR_32B_tag PSR468_471; /* offset: 0x0214 size: 32 bit */
16109  INTC_PSR_32B_tag PSR472_475; /* offset: 0x0218 size: 32 bit */
16110  INTC_PSR_32B_tag PSR476_479; /* offset: 0x021C size: 32 bit */
16111  INTC_PSR_32B_tag PSR480_483; /* offset: 0x0220 size: 32 bit */
16112  INTC_PSR_32B_tag PSR484_487; /* offset: 0x0224 size: 32 bit */
16113  INTC_PSR_32B_tag PSR488_491; /* offset: 0x0228 size: 32 bit */
16114  INTC_PSR_32B_tag PSR492_495; /* offset: 0x022C size: 32 bit */
16115  INTC_PSR_32B_tag PSR496_499; /* offset: 0x0230 size: 32 bit */
16116  INTC_PSR_32B_tag PSR500_503; /* offset: 0x0234 size: 32 bit */
16117  INTC_PSR_32B_tag PSR504_507; /* offset: 0x0238 size: 32 bit */
16118  INTC_PSR_32B_tag PSR508_511; /* offset: 0x023C size: 32 bit */
16119  };
16120 
16121  struct {
16122  /* PSR0-511 - Priority Select Registers */
16123  INTC_PSR_8B_tag PSR0; /* offset: 0x0040 size: 8 bit */
16124  INTC_PSR_8B_tag PSR1; /* offset: 0x0041 size: 8 bit */
16125  INTC_PSR_8B_tag PSR2; /* offset: 0x0042 size: 8 bit */
16126  INTC_PSR_8B_tag PSR3; /* offset: 0x0043 size: 8 bit */
16127  INTC_PSR_8B_tag PSR4; /* offset: 0x0044 size: 8 bit */
16128  INTC_PSR_8B_tag PSR5; /* offset: 0x0045 size: 8 bit */
16129  INTC_PSR_8B_tag PSR6; /* offset: 0x0046 size: 8 bit */
16130  INTC_PSR_8B_tag PSR7; /* offset: 0x0047 size: 8 bit */
16131  INTC_PSR_8B_tag PSR8; /* offset: 0x0048 size: 8 bit */
16132  INTC_PSR_8B_tag PSR9; /* offset: 0x0049 size: 8 bit */
16133  INTC_PSR_8B_tag PSR10; /* offset: 0x004A size: 8 bit */
16134  INTC_PSR_8B_tag PSR11; /* offset: 0x004B size: 8 bit */
16135  INTC_PSR_8B_tag PSR12; /* offset: 0x004C size: 8 bit */
16136  INTC_PSR_8B_tag PSR13; /* offset: 0x004D size: 8 bit */
16137  INTC_PSR_8B_tag PSR14; /* offset: 0x004E size: 8 bit */
16138  INTC_PSR_8B_tag PSR15; /* offset: 0x004F size: 8 bit */
16139  INTC_PSR_8B_tag PSR16; /* offset: 0x0050 size: 8 bit */
16140  INTC_PSR_8B_tag PSR17; /* offset: 0x0051 size: 8 bit */
16141  INTC_PSR_8B_tag PSR18; /* offset: 0x0052 size: 8 bit */
16142  INTC_PSR_8B_tag PSR19; /* offset: 0x0053 size: 8 bit */
16143  INTC_PSR_8B_tag PSR20; /* offset: 0x0054 size: 8 bit */
16144  INTC_PSR_8B_tag PSR21; /* offset: 0x0055 size: 8 bit */
16145  INTC_PSR_8B_tag PSR22; /* offset: 0x0056 size: 8 bit */
16146  INTC_PSR_8B_tag PSR23; /* offset: 0x0057 size: 8 bit */
16147  INTC_PSR_8B_tag PSR24; /* offset: 0x0058 size: 8 bit */
16148  INTC_PSR_8B_tag PSR25; /* offset: 0x0059 size: 8 bit */
16149  INTC_PSR_8B_tag PSR26; /* offset: 0x005A size: 8 bit */
16150  INTC_PSR_8B_tag PSR27; /* offset: 0x005B size: 8 bit */
16151  INTC_PSR_8B_tag PSR28; /* offset: 0x005C size: 8 bit */
16152  INTC_PSR_8B_tag PSR29; /* offset: 0x005D size: 8 bit */
16153  INTC_PSR_8B_tag PSR30; /* offset: 0x005E size: 8 bit */
16154  INTC_PSR_8B_tag PSR31; /* offset: 0x005F size: 8 bit */
16155  INTC_PSR_8B_tag PSR32; /* offset: 0x0060 size: 8 bit */
16156  INTC_PSR_8B_tag PSR33; /* offset: 0x0061 size: 8 bit */
16157  INTC_PSR_8B_tag PSR34; /* offset: 0x0062 size: 8 bit */
16158  INTC_PSR_8B_tag PSR35; /* offset: 0x0063 size: 8 bit */
16159  INTC_PSR_8B_tag PSR36; /* offset: 0x0064 size: 8 bit */
16160  INTC_PSR_8B_tag PSR37; /* offset: 0x0065 size: 8 bit */
16161  INTC_PSR_8B_tag PSR38; /* offset: 0x0066 size: 8 bit */
16162  INTC_PSR_8B_tag PSR39; /* offset: 0x0067 size: 8 bit */
16163  INTC_PSR_8B_tag PSR40; /* offset: 0x0068 size: 8 bit */
16164  INTC_PSR_8B_tag PSR41; /* offset: 0x0069 size: 8 bit */
16165  INTC_PSR_8B_tag PSR42; /* offset: 0x006A size: 8 bit */
16166  INTC_PSR_8B_tag PSR43; /* offset: 0x006B size: 8 bit */
16167  INTC_PSR_8B_tag PSR44; /* offset: 0x006C size: 8 bit */
16168  INTC_PSR_8B_tag PSR45; /* offset: 0x006D size: 8 bit */
16169  INTC_PSR_8B_tag PSR46; /* offset: 0x006E size: 8 bit */
16170  INTC_PSR_8B_tag PSR47; /* offset: 0x006F size: 8 bit */
16171  INTC_PSR_8B_tag PSR48; /* offset: 0x0070 size: 8 bit */
16172  INTC_PSR_8B_tag PSR49; /* offset: 0x0071 size: 8 bit */
16173  INTC_PSR_8B_tag PSR50; /* offset: 0x0072 size: 8 bit */
16174  INTC_PSR_8B_tag PSR51; /* offset: 0x0073 size: 8 bit */
16175  INTC_PSR_8B_tag PSR52; /* offset: 0x0074 size: 8 bit */
16176  INTC_PSR_8B_tag PSR53; /* offset: 0x0075 size: 8 bit */
16177  INTC_PSR_8B_tag PSR54; /* offset: 0x0076 size: 8 bit */
16178  INTC_PSR_8B_tag PSR55; /* offset: 0x0077 size: 8 bit */
16179  INTC_PSR_8B_tag PSR56; /* offset: 0x0078 size: 8 bit */
16180  INTC_PSR_8B_tag PSR57; /* offset: 0x0079 size: 8 bit */
16181  INTC_PSR_8B_tag PSR58; /* offset: 0x007A size: 8 bit */
16182  INTC_PSR_8B_tag PSR59; /* offset: 0x007B size: 8 bit */
16183  INTC_PSR_8B_tag PSR60; /* offset: 0x007C size: 8 bit */
16184  INTC_PSR_8B_tag PSR61; /* offset: 0x007D size: 8 bit */
16185  INTC_PSR_8B_tag PSR62; /* offset: 0x007E size: 8 bit */
16186  INTC_PSR_8B_tag PSR63; /* offset: 0x007F size: 8 bit */
16187  INTC_PSR_8B_tag PSR64; /* offset: 0x0080 size: 8 bit */
16188  INTC_PSR_8B_tag PSR65; /* offset: 0x0081 size: 8 bit */
16189  INTC_PSR_8B_tag PSR66; /* offset: 0x0082 size: 8 bit */
16190  INTC_PSR_8B_tag PSR67; /* offset: 0x0083 size: 8 bit */
16191  INTC_PSR_8B_tag PSR68; /* offset: 0x0084 size: 8 bit */
16192  INTC_PSR_8B_tag PSR69; /* offset: 0x0085 size: 8 bit */
16193  INTC_PSR_8B_tag PSR70; /* offset: 0x0086 size: 8 bit */
16194  INTC_PSR_8B_tag PSR71; /* offset: 0x0087 size: 8 bit */
16195  INTC_PSR_8B_tag PSR72; /* offset: 0x0088 size: 8 bit */
16196  INTC_PSR_8B_tag PSR73; /* offset: 0x0089 size: 8 bit */
16197  INTC_PSR_8B_tag PSR74; /* offset: 0x008A size: 8 bit */
16198  INTC_PSR_8B_tag PSR75; /* offset: 0x008B size: 8 bit */
16199  INTC_PSR_8B_tag PSR76; /* offset: 0x008C size: 8 bit */
16200  INTC_PSR_8B_tag PSR77; /* offset: 0x008D size: 8 bit */
16201  INTC_PSR_8B_tag PSR78; /* offset: 0x008E size: 8 bit */
16202  INTC_PSR_8B_tag PSR79; /* offset: 0x008F size: 8 bit */
16203  INTC_PSR_8B_tag PSR80; /* offset: 0x0090 size: 8 bit */
16204  INTC_PSR_8B_tag PSR81; /* offset: 0x0091 size: 8 bit */
16205  INTC_PSR_8B_tag PSR82; /* offset: 0x0092 size: 8 bit */
16206  INTC_PSR_8B_tag PSR83; /* offset: 0x0093 size: 8 bit */
16207  INTC_PSR_8B_tag PSR84; /* offset: 0x0094 size: 8 bit */
16208  INTC_PSR_8B_tag PSR85; /* offset: 0x0095 size: 8 bit */
16209  INTC_PSR_8B_tag PSR86; /* offset: 0x0096 size: 8 bit */
16210  INTC_PSR_8B_tag PSR87; /* offset: 0x0097 size: 8 bit */
16211  INTC_PSR_8B_tag PSR88; /* offset: 0x0098 size: 8 bit */
16212  INTC_PSR_8B_tag PSR89; /* offset: 0x0099 size: 8 bit */
16213  INTC_PSR_8B_tag PSR90; /* offset: 0x009A size: 8 bit */
16214  INTC_PSR_8B_tag PSR91; /* offset: 0x009B size: 8 bit */
16215  INTC_PSR_8B_tag PSR92; /* offset: 0x009C size: 8 bit */
16216  INTC_PSR_8B_tag PSR93; /* offset: 0x009D size: 8 bit */
16217  INTC_PSR_8B_tag PSR94; /* offset: 0x009E size: 8 bit */
16218  INTC_PSR_8B_tag PSR95; /* offset: 0x009F size: 8 bit */
16219  INTC_PSR_8B_tag PSR96; /* offset: 0x00A0 size: 8 bit */
16220  INTC_PSR_8B_tag PSR97; /* offset: 0x00A1 size: 8 bit */
16221  INTC_PSR_8B_tag PSR98; /* offset: 0x00A2 size: 8 bit */
16222  INTC_PSR_8B_tag PSR99; /* offset: 0x00A3 size: 8 bit */
16223  INTC_PSR_8B_tag PSR100; /* offset: 0x00A4 size: 8 bit */
16224  INTC_PSR_8B_tag PSR101; /* offset: 0x00A5 size: 8 bit */
16225  INTC_PSR_8B_tag PSR102; /* offset: 0x00A6 size: 8 bit */
16226  INTC_PSR_8B_tag PSR103; /* offset: 0x00A7 size: 8 bit */
16227  INTC_PSR_8B_tag PSR104; /* offset: 0x00A8 size: 8 bit */
16228  INTC_PSR_8B_tag PSR105; /* offset: 0x00A9 size: 8 bit */
16229  INTC_PSR_8B_tag PSR106; /* offset: 0x00AA size: 8 bit */
16230  INTC_PSR_8B_tag PSR107; /* offset: 0x00AB size: 8 bit */
16231  INTC_PSR_8B_tag PSR108; /* offset: 0x00AC size: 8 bit */
16232  INTC_PSR_8B_tag PSR109; /* offset: 0x00AD size: 8 bit */
16233  INTC_PSR_8B_tag PSR110; /* offset: 0x00AE size: 8 bit */
16234  INTC_PSR_8B_tag PSR111; /* offset: 0x00AF size: 8 bit */
16235  INTC_PSR_8B_tag PSR112; /* offset: 0x00B0 size: 8 bit */
16236  INTC_PSR_8B_tag PSR113; /* offset: 0x00B1 size: 8 bit */
16237  INTC_PSR_8B_tag PSR114; /* offset: 0x00B2 size: 8 bit */
16238  INTC_PSR_8B_tag PSR115; /* offset: 0x00B3 size: 8 bit */
16239  INTC_PSR_8B_tag PSR116; /* offset: 0x00B4 size: 8 bit */
16240  INTC_PSR_8B_tag PSR117; /* offset: 0x00B5 size: 8 bit */
16241  INTC_PSR_8B_tag PSR118; /* offset: 0x00B6 size: 8 bit */
16242  INTC_PSR_8B_tag PSR119; /* offset: 0x00B7 size: 8 bit */
16243  INTC_PSR_8B_tag PSR120; /* offset: 0x00B8 size: 8 bit */
16244  INTC_PSR_8B_tag PSR121; /* offset: 0x00B9 size: 8 bit */
16245  INTC_PSR_8B_tag PSR122; /* offset: 0x00BA size: 8 bit */
16246  INTC_PSR_8B_tag PSR123; /* offset: 0x00BB size: 8 bit */
16247  INTC_PSR_8B_tag PSR124; /* offset: 0x00BC size: 8 bit */
16248  INTC_PSR_8B_tag PSR125; /* offset: 0x00BD size: 8 bit */
16249  INTC_PSR_8B_tag PSR126; /* offset: 0x00BE size: 8 bit */
16250  INTC_PSR_8B_tag PSR127; /* offset: 0x00BF size: 8 bit */
16251  INTC_PSR_8B_tag PSR128; /* offset: 0x00C0 size: 8 bit */
16252  INTC_PSR_8B_tag PSR129; /* offset: 0x00C1 size: 8 bit */
16253  INTC_PSR_8B_tag PSR130; /* offset: 0x00C2 size: 8 bit */
16254  INTC_PSR_8B_tag PSR131; /* offset: 0x00C3 size: 8 bit */
16255  INTC_PSR_8B_tag PSR132; /* offset: 0x00C4 size: 8 bit */
16256  INTC_PSR_8B_tag PSR133; /* offset: 0x00C5 size: 8 bit */
16257  INTC_PSR_8B_tag PSR134; /* offset: 0x00C6 size: 8 bit */
16258  INTC_PSR_8B_tag PSR135; /* offset: 0x00C7 size: 8 bit */
16259  INTC_PSR_8B_tag PSR136; /* offset: 0x00C8 size: 8 bit */
16260  INTC_PSR_8B_tag PSR137; /* offset: 0x00C9 size: 8 bit */
16261  INTC_PSR_8B_tag PSR138; /* offset: 0x00CA size: 8 bit */
16262  INTC_PSR_8B_tag PSR139; /* offset: 0x00CB size: 8 bit */
16263  INTC_PSR_8B_tag PSR140; /* offset: 0x00CC size: 8 bit */
16264  INTC_PSR_8B_tag PSR141; /* offset: 0x00CD size: 8 bit */
16265  INTC_PSR_8B_tag PSR142; /* offset: 0x00CE size: 8 bit */
16266  INTC_PSR_8B_tag PSR143; /* offset: 0x00CF size: 8 bit */
16267  INTC_PSR_8B_tag PSR144; /* offset: 0x00D0 size: 8 bit */
16268  INTC_PSR_8B_tag PSR145; /* offset: 0x00D1 size: 8 bit */
16269  INTC_PSR_8B_tag PSR146; /* offset: 0x00D2 size: 8 bit */
16270  INTC_PSR_8B_tag PSR147; /* offset: 0x00D3 size: 8 bit */
16271  INTC_PSR_8B_tag PSR148; /* offset: 0x00D4 size: 8 bit */
16272  INTC_PSR_8B_tag PSR149; /* offset: 0x00D5 size: 8 bit */
16273  INTC_PSR_8B_tag PSR150; /* offset: 0x00D6 size: 8 bit */
16274  INTC_PSR_8B_tag PSR151; /* offset: 0x00D7 size: 8 bit */
16275  INTC_PSR_8B_tag PSR152; /* offset: 0x00D8 size: 8 bit */
16276  INTC_PSR_8B_tag PSR153; /* offset: 0x00D9 size: 8 bit */
16277  INTC_PSR_8B_tag PSR154; /* offset: 0x00DA size: 8 bit */
16278  INTC_PSR_8B_tag PSR155; /* offset: 0x00DB size: 8 bit */
16279  INTC_PSR_8B_tag PSR156; /* offset: 0x00DC size: 8 bit */
16280  INTC_PSR_8B_tag PSR157; /* offset: 0x00DD size: 8 bit */
16281  INTC_PSR_8B_tag PSR158; /* offset: 0x00DE size: 8 bit */
16282  INTC_PSR_8B_tag PSR159; /* offset: 0x00DF size: 8 bit */
16283  INTC_PSR_8B_tag PSR160; /* offset: 0x00E0 size: 8 bit */
16284  INTC_PSR_8B_tag PSR161; /* offset: 0x00E1 size: 8 bit */
16285  INTC_PSR_8B_tag PSR162; /* offset: 0x00E2 size: 8 bit */
16286  INTC_PSR_8B_tag PSR163; /* offset: 0x00E3 size: 8 bit */
16287  INTC_PSR_8B_tag PSR164; /* offset: 0x00E4 size: 8 bit */
16288  INTC_PSR_8B_tag PSR165; /* offset: 0x00E5 size: 8 bit */
16289  INTC_PSR_8B_tag PSR166; /* offset: 0x00E6 size: 8 bit */
16290  INTC_PSR_8B_tag PSR167; /* offset: 0x00E7 size: 8 bit */
16291  INTC_PSR_8B_tag PSR168; /* offset: 0x00E8 size: 8 bit */
16292  INTC_PSR_8B_tag PSR169; /* offset: 0x00E9 size: 8 bit */
16293  INTC_PSR_8B_tag PSR170; /* offset: 0x00EA size: 8 bit */
16294  INTC_PSR_8B_tag PSR171; /* offset: 0x00EB size: 8 bit */
16295  INTC_PSR_8B_tag PSR172; /* offset: 0x00EC size: 8 bit */
16296  INTC_PSR_8B_tag PSR173; /* offset: 0x00ED size: 8 bit */
16297  INTC_PSR_8B_tag PSR174; /* offset: 0x00EE size: 8 bit */
16298  INTC_PSR_8B_tag PSR175; /* offset: 0x00EF size: 8 bit */
16299  INTC_PSR_8B_tag PSR176; /* offset: 0x00F0 size: 8 bit */
16300  INTC_PSR_8B_tag PSR177; /* offset: 0x00F1 size: 8 bit */
16301  INTC_PSR_8B_tag PSR178; /* offset: 0x00F2 size: 8 bit */
16302  INTC_PSR_8B_tag PSR179; /* offset: 0x00F3 size: 8 bit */
16303  INTC_PSR_8B_tag PSR180; /* offset: 0x00F4 size: 8 bit */
16304  INTC_PSR_8B_tag PSR181; /* offset: 0x00F5 size: 8 bit */
16305  INTC_PSR_8B_tag PSR182; /* offset: 0x00F6 size: 8 bit */
16306  INTC_PSR_8B_tag PSR183; /* offset: 0x00F7 size: 8 bit */
16307  INTC_PSR_8B_tag PSR184; /* offset: 0x00F8 size: 8 bit */
16308  INTC_PSR_8B_tag PSR185; /* offset: 0x00F9 size: 8 bit */
16309  INTC_PSR_8B_tag PSR186; /* offset: 0x00FA size: 8 bit */
16310  INTC_PSR_8B_tag PSR187; /* offset: 0x00FB size: 8 bit */
16311  INTC_PSR_8B_tag PSR188; /* offset: 0x00FC size: 8 bit */
16312  INTC_PSR_8B_tag PSR189; /* offset: 0x00FD size: 8 bit */
16313  INTC_PSR_8B_tag PSR190; /* offset: 0x00FE size: 8 bit */
16314  INTC_PSR_8B_tag PSR191; /* offset: 0x00FF size: 8 bit */
16315  INTC_PSR_8B_tag PSR192; /* offset: 0x0100 size: 8 bit */
16316  INTC_PSR_8B_tag PSR193; /* offset: 0x0101 size: 8 bit */
16317  INTC_PSR_8B_tag PSR194; /* offset: 0x0102 size: 8 bit */
16318  INTC_PSR_8B_tag PSR195; /* offset: 0x0103 size: 8 bit */
16319  INTC_PSR_8B_tag PSR196; /* offset: 0x0104 size: 8 bit */
16320  INTC_PSR_8B_tag PSR197; /* offset: 0x0105 size: 8 bit */
16321  INTC_PSR_8B_tag PSR198; /* offset: 0x0106 size: 8 bit */
16322  INTC_PSR_8B_tag PSR199; /* offset: 0x0107 size: 8 bit */
16323  INTC_PSR_8B_tag PSR200; /* offset: 0x0108 size: 8 bit */
16324  INTC_PSR_8B_tag PSR201; /* offset: 0x0109 size: 8 bit */
16325  INTC_PSR_8B_tag PSR202; /* offset: 0x010A size: 8 bit */
16326  INTC_PSR_8B_tag PSR203; /* offset: 0x010B size: 8 bit */
16327  INTC_PSR_8B_tag PSR204; /* offset: 0x010C size: 8 bit */
16328  INTC_PSR_8B_tag PSR205; /* offset: 0x010D size: 8 bit */
16329  INTC_PSR_8B_tag PSR206; /* offset: 0x010E size: 8 bit */
16330  INTC_PSR_8B_tag PSR207; /* offset: 0x010F size: 8 bit */
16331  INTC_PSR_8B_tag PSR208; /* offset: 0x0110 size: 8 bit */
16332  INTC_PSR_8B_tag PSR209; /* offset: 0x0111 size: 8 bit */
16333  INTC_PSR_8B_tag PSR210; /* offset: 0x0112 size: 8 bit */
16334  INTC_PSR_8B_tag PSR211; /* offset: 0x0113 size: 8 bit */
16335  INTC_PSR_8B_tag PSR212; /* offset: 0x0114 size: 8 bit */
16336  INTC_PSR_8B_tag PSR213; /* offset: 0x0115 size: 8 bit */
16337  INTC_PSR_8B_tag PSR214; /* offset: 0x0116 size: 8 bit */
16338  INTC_PSR_8B_tag PSR215; /* offset: 0x0117 size: 8 bit */
16339  INTC_PSR_8B_tag PSR216; /* offset: 0x0118 size: 8 bit */
16340  INTC_PSR_8B_tag PSR217; /* offset: 0x0119 size: 8 bit */
16341  INTC_PSR_8B_tag PSR218; /* offset: 0x011A size: 8 bit */
16342  INTC_PSR_8B_tag PSR219; /* offset: 0x011B size: 8 bit */
16343  INTC_PSR_8B_tag PSR220; /* offset: 0x011C size: 8 bit */
16344  INTC_PSR_8B_tag PSR221; /* offset: 0x011D size: 8 bit */
16345  INTC_PSR_8B_tag PSR222; /* offset: 0x011E size: 8 bit */
16346  INTC_PSR_8B_tag PSR223; /* offset: 0x011F size: 8 bit */
16347  INTC_PSR_8B_tag PSR224; /* offset: 0x0120 size: 8 bit */
16348  INTC_PSR_8B_tag PSR225; /* offset: 0x0121 size: 8 bit */
16349  INTC_PSR_8B_tag PSR226; /* offset: 0x0122 size: 8 bit */
16350  INTC_PSR_8B_tag PSR227; /* offset: 0x0123 size: 8 bit */
16351  INTC_PSR_8B_tag PSR228; /* offset: 0x0124 size: 8 bit */
16352  INTC_PSR_8B_tag PSR229; /* offset: 0x0125 size: 8 bit */
16353  INTC_PSR_8B_tag PSR230; /* offset: 0x0126 size: 8 bit */
16354  INTC_PSR_8B_tag PSR231; /* offset: 0x0127 size: 8 bit */
16355  INTC_PSR_8B_tag PSR232; /* offset: 0x0128 size: 8 bit */
16356  INTC_PSR_8B_tag PSR233; /* offset: 0x0129 size: 8 bit */
16357  INTC_PSR_8B_tag PSR234; /* offset: 0x012A size: 8 bit */
16358  INTC_PSR_8B_tag PSR235; /* offset: 0x012B size: 8 bit */
16359  INTC_PSR_8B_tag PSR236; /* offset: 0x012C size: 8 bit */
16360  INTC_PSR_8B_tag PSR237; /* offset: 0x012D size: 8 bit */
16361  INTC_PSR_8B_tag PSR238; /* offset: 0x012E size: 8 bit */
16362  INTC_PSR_8B_tag PSR239; /* offset: 0x012F size: 8 bit */
16363  INTC_PSR_8B_tag PSR240; /* offset: 0x0130 size: 8 bit */
16364  INTC_PSR_8B_tag PSR241; /* offset: 0x0131 size: 8 bit */
16365  INTC_PSR_8B_tag PSR242; /* offset: 0x0132 size: 8 bit */
16366  INTC_PSR_8B_tag PSR243; /* offset: 0x0133 size: 8 bit */
16367  INTC_PSR_8B_tag PSR244; /* offset: 0x0134 size: 8 bit */
16368  INTC_PSR_8B_tag PSR245; /* offset: 0x0135 size: 8 bit */
16369  INTC_PSR_8B_tag PSR246; /* offset: 0x0136 size: 8 bit */
16370  INTC_PSR_8B_tag PSR247; /* offset: 0x0137 size: 8 bit */
16371  INTC_PSR_8B_tag PSR248; /* offset: 0x0138 size: 8 bit */
16372  INTC_PSR_8B_tag PSR249; /* offset: 0x0139 size: 8 bit */
16373  INTC_PSR_8B_tag PSR250; /* offset: 0x013A size: 8 bit */
16374  INTC_PSR_8B_tag PSR251; /* offset: 0x013B size: 8 bit */
16375  INTC_PSR_8B_tag PSR252; /* offset: 0x013C size: 8 bit */
16376  INTC_PSR_8B_tag PSR253; /* offset: 0x013D size: 8 bit */
16377  INTC_PSR_8B_tag PSR254; /* offset: 0x013E size: 8 bit */
16378  INTC_PSR_8B_tag PSR255; /* offset: 0x013F size: 8 bit */
16379  INTC_PSR_8B_tag PSR256; /* offset: 0x0140 size: 8 bit */
16380  INTC_PSR_8B_tag PSR257; /* offset: 0x0141 size: 8 bit */
16381  INTC_PSR_8B_tag PSR258; /* offset: 0x0142 size: 8 bit */
16382  INTC_PSR_8B_tag PSR259; /* offset: 0x0143 size: 8 bit */
16383  INTC_PSR_8B_tag PSR260; /* offset: 0x0144 size: 8 bit */
16384  INTC_PSR_8B_tag PSR261; /* offset: 0x0145 size: 8 bit */
16385  INTC_PSR_8B_tag PSR262; /* offset: 0x0146 size: 8 bit */
16386  INTC_PSR_8B_tag PSR263; /* offset: 0x0147 size: 8 bit */
16387  INTC_PSR_8B_tag PSR264; /* offset: 0x0148 size: 8 bit */
16388  INTC_PSR_8B_tag PSR265; /* offset: 0x0149 size: 8 bit */
16389  INTC_PSR_8B_tag PSR266; /* offset: 0x014A size: 8 bit */
16390  INTC_PSR_8B_tag PSR267; /* offset: 0x014B size: 8 bit */
16391  INTC_PSR_8B_tag PSR268; /* offset: 0x014C size: 8 bit */
16392  INTC_PSR_8B_tag PSR269; /* offset: 0x014D size: 8 bit */
16393  INTC_PSR_8B_tag PSR270; /* offset: 0x014E size: 8 bit */
16394  INTC_PSR_8B_tag PSR271; /* offset: 0x014F size: 8 bit */
16395  INTC_PSR_8B_tag PSR272; /* offset: 0x0150 size: 8 bit */
16396  INTC_PSR_8B_tag PSR273; /* offset: 0x0151 size: 8 bit */
16397  INTC_PSR_8B_tag PSR274; /* offset: 0x0152 size: 8 bit */
16398  INTC_PSR_8B_tag PSR275; /* offset: 0x0153 size: 8 bit */
16399  INTC_PSR_8B_tag PSR276; /* offset: 0x0154 size: 8 bit */
16400  INTC_PSR_8B_tag PSR277; /* offset: 0x0155 size: 8 bit */
16401  INTC_PSR_8B_tag PSR278; /* offset: 0x0156 size: 8 bit */
16402  INTC_PSR_8B_tag PSR279; /* offset: 0x0157 size: 8 bit */
16403  INTC_PSR_8B_tag PSR280; /* offset: 0x0158 size: 8 bit */
16404  INTC_PSR_8B_tag PSR281; /* offset: 0x0159 size: 8 bit */
16405  INTC_PSR_8B_tag PSR282; /* offset: 0x015A size: 8 bit */
16406  INTC_PSR_8B_tag PSR283; /* offset: 0x015B size: 8 bit */
16407  INTC_PSR_8B_tag PSR284; /* offset: 0x015C size: 8 bit */
16408  INTC_PSR_8B_tag PSR285; /* offset: 0x015D size: 8 bit */
16409  INTC_PSR_8B_tag PSR286; /* offset: 0x015E size: 8 bit */
16410  INTC_PSR_8B_tag PSR287; /* offset: 0x015F size: 8 bit */
16411  INTC_PSR_8B_tag PSR288; /* offset: 0x0160 size: 8 bit */
16412  INTC_PSR_8B_tag PSR289; /* offset: 0x0161 size: 8 bit */
16413  INTC_PSR_8B_tag PSR290; /* offset: 0x0162 size: 8 bit */
16414  INTC_PSR_8B_tag PSR291; /* offset: 0x0163 size: 8 bit */
16415  INTC_PSR_8B_tag PSR292; /* offset: 0x0164 size: 8 bit */
16416  INTC_PSR_8B_tag PSR293; /* offset: 0x0165 size: 8 bit */
16417  INTC_PSR_8B_tag PSR294; /* offset: 0x0166 size: 8 bit */
16418  INTC_PSR_8B_tag PSR295; /* offset: 0x0167 size: 8 bit */
16419  INTC_PSR_8B_tag PSR296; /* offset: 0x0168 size: 8 bit */
16420  INTC_PSR_8B_tag PSR297; /* offset: 0x0169 size: 8 bit */
16421  INTC_PSR_8B_tag PSR298; /* offset: 0x016A size: 8 bit */
16422  INTC_PSR_8B_tag PSR299; /* offset: 0x016B size: 8 bit */
16423  INTC_PSR_8B_tag PSR300; /* offset: 0x016C size: 8 bit */
16424  INTC_PSR_8B_tag PSR301; /* offset: 0x016D size: 8 bit */
16425  INTC_PSR_8B_tag PSR302; /* offset: 0x016E size: 8 bit */
16426  INTC_PSR_8B_tag PSR303; /* offset: 0x016F size: 8 bit */
16427  INTC_PSR_8B_tag PSR304; /* offset: 0x0170 size: 8 bit */
16428  INTC_PSR_8B_tag PSR305; /* offset: 0x0171 size: 8 bit */
16429  INTC_PSR_8B_tag PSR306; /* offset: 0x0172 size: 8 bit */
16430  INTC_PSR_8B_tag PSR307; /* offset: 0x0173 size: 8 bit */
16431  INTC_PSR_8B_tag PSR308; /* offset: 0x0174 size: 8 bit */
16432  INTC_PSR_8B_tag PSR309; /* offset: 0x0175 size: 8 bit */
16433  INTC_PSR_8B_tag PSR310; /* offset: 0x0176 size: 8 bit */
16434  INTC_PSR_8B_tag PSR311; /* offset: 0x0177 size: 8 bit */
16435  INTC_PSR_8B_tag PSR312; /* offset: 0x0178 size: 8 bit */
16436  INTC_PSR_8B_tag PSR313; /* offset: 0x0179 size: 8 bit */
16437  INTC_PSR_8B_tag PSR314; /* offset: 0x017A size: 8 bit */
16438  INTC_PSR_8B_tag PSR315; /* offset: 0x017B size: 8 bit */
16439  INTC_PSR_8B_tag PSR316; /* offset: 0x017C size: 8 bit */
16440  INTC_PSR_8B_tag PSR317; /* offset: 0x017D size: 8 bit */
16441  INTC_PSR_8B_tag PSR318; /* offset: 0x017E size: 8 bit */
16442  INTC_PSR_8B_tag PSR319; /* offset: 0x017F size: 8 bit */
16443  INTC_PSR_8B_tag PSR320; /* offset: 0x0180 size: 8 bit */
16444  INTC_PSR_8B_tag PSR321; /* offset: 0x0181 size: 8 bit */
16445  INTC_PSR_8B_tag PSR322; /* offset: 0x0182 size: 8 bit */
16446  INTC_PSR_8B_tag PSR323; /* offset: 0x0183 size: 8 bit */
16447  INTC_PSR_8B_tag PSR324; /* offset: 0x0184 size: 8 bit */
16448  INTC_PSR_8B_tag PSR325; /* offset: 0x0185 size: 8 bit */
16449  INTC_PSR_8B_tag PSR326; /* offset: 0x0186 size: 8 bit */
16450  INTC_PSR_8B_tag PSR327; /* offset: 0x0187 size: 8 bit */
16451  INTC_PSR_8B_tag PSR328; /* offset: 0x0188 size: 8 bit */
16452  INTC_PSR_8B_tag PSR329; /* offset: 0x0189 size: 8 bit */
16453  INTC_PSR_8B_tag PSR330; /* offset: 0x018A size: 8 bit */
16454  INTC_PSR_8B_tag PSR331; /* offset: 0x018B size: 8 bit */
16455  INTC_PSR_8B_tag PSR332; /* offset: 0x018C size: 8 bit */
16456  INTC_PSR_8B_tag PSR333; /* offset: 0x018D size: 8 bit */
16457  INTC_PSR_8B_tag PSR334; /* offset: 0x018E size: 8 bit */
16458  INTC_PSR_8B_tag PSR335; /* offset: 0x018F size: 8 bit */
16459  INTC_PSR_8B_tag PSR336; /* offset: 0x0190 size: 8 bit */
16460  INTC_PSR_8B_tag PSR337; /* offset: 0x0191 size: 8 bit */
16461  INTC_PSR_8B_tag PSR338; /* offset: 0x0192 size: 8 bit */
16462  INTC_PSR_8B_tag PSR339; /* offset: 0x0193 size: 8 bit */
16463  INTC_PSR_8B_tag PSR340; /* offset: 0x0194 size: 8 bit */
16464  INTC_PSR_8B_tag PSR341; /* offset: 0x0195 size: 8 bit */
16465  INTC_PSR_8B_tag PSR342; /* offset: 0x0196 size: 8 bit */
16466  INTC_PSR_8B_tag PSR343; /* offset: 0x0197 size: 8 bit */
16467  INTC_PSR_8B_tag PSR344; /* offset: 0x0198 size: 8 bit */
16468  INTC_PSR_8B_tag PSR345; /* offset: 0x0199 size: 8 bit */
16469  INTC_PSR_8B_tag PSR346; /* offset: 0x019A size: 8 bit */
16470  INTC_PSR_8B_tag PSR347; /* offset: 0x019B size: 8 bit */
16471  INTC_PSR_8B_tag PSR348; /* offset: 0x019C size: 8 bit */
16472  INTC_PSR_8B_tag PSR349; /* offset: 0x019D size: 8 bit */
16473  INTC_PSR_8B_tag PSR350; /* offset: 0x019E size: 8 bit */
16474  INTC_PSR_8B_tag PSR351; /* offset: 0x019F size: 8 bit */
16475  INTC_PSR_8B_tag PSR352; /* offset: 0x01A0 size: 8 bit */
16476  INTC_PSR_8B_tag PSR353; /* offset: 0x01A1 size: 8 bit */
16477  INTC_PSR_8B_tag PSR354; /* offset: 0x01A2 size: 8 bit */
16478  INTC_PSR_8B_tag PSR355; /* offset: 0x01A3 size: 8 bit */
16479  INTC_PSR_8B_tag PSR356; /* offset: 0x01A4 size: 8 bit */
16480  INTC_PSR_8B_tag PSR357; /* offset: 0x01A5 size: 8 bit */
16481  INTC_PSR_8B_tag PSR358; /* offset: 0x01A6 size: 8 bit */
16482  INTC_PSR_8B_tag PSR359; /* offset: 0x01A7 size: 8 bit */
16483  INTC_PSR_8B_tag PSR360; /* offset: 0x01A8 size: 8 bit */
16484  INTC_PSR_8B_tag PSR361; /* offset: 0x01A9 size: 8 bit */
16485  INTC_PSR_8B_tag PSR362; /* offset: 0x01AA size: 8 bit */
16486  INTC_PSR_8B_tag PSR363; /* offset: 0x01AB size: 8 bit */
16487  INTC_PSR_8B_tag PSR364; /* offset: 0x01AC size: 8 bit */
16488  INTC_PSR_8B_tag PSR365; /* offset: 0x01AD size: 8 bit */
16489  INTC_PSR_8B_tag PSR366; /* offset: 0x01AE size: 8 bit */
16490  INTC_PSR_8B_tag PSR367; /* offset: 0x01AF size: 8 bit */
16491  INTC_PSR_8B_tag PSR368; /* offset: 0x01B0 size: 8 bit */
16492  INTC_PSR_8B_tag PSR369; /* offset: 0x01B1 size: 8 bit */
16493  INTC_PSR_8B_tag PSR370; /* offset: 0x01B2 size: 8 bit */
16494  INTC_PSR_8B_tag PSR371; /* offset: 0x01B3 size: 8 bit */
16495  INTC_PSR_8B_tag PSR372; /* offset: 0x01B4 size: 8 bit */
16496  INTC_PSR_8B_tag PSR373; /* offset: 0x01B5 size: 8 bit */
16497  INTC_PSR_8B_tag PSR374; /* offset: 0x01B6 size: 8 bit */
16498  INTC_PSR_8B_tag PSR375; /* offset: 0x01B7 size: 8 bit */
16499  INTC_PSR_8B_tag PSR376; /* offset: 0x01B8 size: 8 bit */
16500  INTC_PSR_8B_tag PSR377; /* offset: 0x01B9 size: 8 bit */
16501  INTC_PSR_8B_tag PSR378; /* offset: 0x01BA size: 8 bit */
16502  INTC_PSR_8B_tag PSR379; /* offset: 0x01BB size: 8 bit */
16503  INTC_PSR_8B_tag PSR380; /* offset: 0x01BC size: 8 bit */
16504  INTC_PSR_8B_tag PSR381; /* offset: 0x01BD size: 8 bit */
16505  INTC_PSR_8B_tag PSR382; /* offset: 0x01BE size: 8 bit */
16506  INTC_PSR_8B_tag PSR383; /* offset: 0x01BF size: 8 bit */
16507  INTC_PSR_8B_tag PSR384; /* offset: 0x01C0 size: 8 bit */
16508  INTC_PSR_8B_tag PSR385; /* offset: 0x01C1 size: 8 bit */
16509  INTC_PSR_8B_tag PSR386; /* offset: 0x01C2 size: 8 bit */
16510  INTC_PSR_8B_tag PSR387; /* offset: 0x01C3 size: 8 bit */
16511  INTC_PSR_8B_tag PSR388; /* offset: 0x01C4 size: 8 bit */
16512  INTC_PSR_8B_tag PSR389; /* offset: 0x01C5 size: 8 bit */
16513  INTC_PSR_8B_tag PSR390; /* offset: 0x01C6 size: 8 bit */
16514  INTC_PSR_8B_tag PSR391; /* offset: 0x01C7 size: 8 bit */
16515  INTC_PSR_8B_tag PSR392; /* offset: 0x01C8 size: 8 bit */
16516  INTC_PSR_8B_tag PSR393; /* offset: 0x01C9 size: 8 bit */
16517  INTC_PSR_8B_tag PSR394; /* offset: 0x01CA size: 8 bit */
16518  INTC_PSR_8B_tag PSR395; /* offset: 0x01CB size: 8 bit */
16519  INTC_PSR_8B_tag PSR396; /* offset: 0x01CC size: 8 bit */
16520  INTC_PSR_8B_tag PSR397; /* offset: 0x01CD size: 8 bit */
16521  INTC_PSR_8B_tag PSR398; /* offset: 0x01CE size: 8 bit */
16522  INTC_PSR_8B_tag PSR399; /* offset: 0x01CF size: 8 bit */
16523  INTC_PSR_8B_tag PSR400; /* offset: 0x01D0 size: 8 bit */
16524  INTC_PSR_8B_tag PSR401; /* offset: 0x01D1 size: 8 bit */
16525  INTC_PSR_8B_tag PSR402; /* offset: 0x01D2 size: 8 bit */
16526  INTC_PSR_8B_tag PSR403; /* offset: 0x01D3 size: 8 bit */
16527  INTC_PSR_8B_tag PSR404; /* offset: 0x01D4 size: 8 bit */
16528  INTC_PSR_8B_tag PSR405; /* offset: 0x01D5 size: 8 bit */
16529  INTC_PSR_8B_tag PSR406; /* offset: 0x01D6 size: 8 bit */
16530  INTC_PSR_8B_tag PSR407; /* offset: 0x01D7 size: 8 bit */
16531  INTC_PSR_8B_tag PSR408; /* offset: 0x01D8 size: 8 bit */
16532  INTC_PSR_8B_tag PSR409; /* offset: 0x01D9 size: 8 bit */
16533  INTC_PSR_8B_tag PSR410; /* offset: 0x01DA size: 8 bit */
16534  INTC_PSR_8B_tag PSR411; /* offset: 0x01DB size: 8 bit */
16535  INTC_PSR_8B_tag PSR412; /* offset: 0x01DC size: 8 bit */
16536  INTC_PSR_8B_tag PSR413; /* offset: 0x01DD size: 8 bit */
16537  INTC_PSR_8B_tag PSR414; /* offset: 0x01DE size: 8 bit */
16538  INTC_PSR_8B_tag PSR415; /* offset: 0x01DF size: 8 bit */
16539  INTC_PSR_8B_tag PSR416; /* offset: 0x01E0 size: 8 bit */
16540  INTC_PSR_8B_tag PSR417; /* offset: 0x01E1 size: 8 bit */
16541  INTC_PSR_8B_tag PSR418; /* offset: 0x01E2 size: 8 bit */
16542  INTC_PSR_8B_tag PSR419; /* offset: 0x01E3 size: 8 bit */
16543  INTC_PSR_8B_tag PSR420; /* offset: 0x01E4 size: 8 bit */
16544  INTC_PSR_8B_tag PSR421; /* offset: 0x01E5 size: 8 bit */
16545  INTC_PSR_8B_tag PSR422; /* offset: 0x01E6 size: 8 bit */
16546  INTC_PSR_8B_tag PSR423; /* offset: 0x01E7 size: 8 bit */
16547  INTC_PSR_8B_tag PSR424; /* offset: 0x01E8 size: 8 bit */
16548  INTC_PSR_8B_tag PSR425; /* offset: 0x01E9 size: 8 bit */
16549  INTC_PSR_8B_tag PSR426; /* offset: 0x01EA size: 8 bit */
16550  INTC_PSR_8B_tag PSR427; /* offset: 0x01EB size: 8 bit */
16551  INTC_PSR_8B_tag PSR428; /* offset: 0x01EC size: 8 bit */
16552  INTC_PSR_8B_tag PSR429; /* offset: 0x01ED size: 8 bit */
16553  INTC_PSR_8B_tag PSR430; /* offset: 0x01EE size: 8 bit */
16554  INTC_PSR_8B_tag PSR431; /* offset: 0x01EF size: 8 bit */
16555  INTC_PSR_8B_tag PSR432; /* offset: 0x01F0 size: 8 bit */
16556  INTC_PSR_8B_tag PSR433; /* offset: 0x01F1 size: 8 bit */
16557  INTC_PSR_8B_tag PSR434; /* offset: 0x01F2 size: 8 bit */
16558  INTC_PSR_8B_tag PSR435; /* offset: 0x01F3 size: 8 bit */
16559  INTC_PSR_8B_tag PSR436; /* offset: 0x01F4 size: 8 bit */
16560  INTC_PSR_8B_tag PSR437; /* offset: 0x01F5 size: 8 bit */
16561  INTC_PSR_8B_tag PSR438; /* offset: 0x01F6 size: 8 bit */
16562  INTC_PSR_8B_tag PSR439; /* offset: 0x01F7 size: 8 bit */
16563  INTC_PSR_8B_tag PSR440; /* offset: 0x01F8 size: 8 bit */
16564  INTC_PSR_8B_tag PSR441; /* offset: 0x01F9 size: 8 bit */
16565  INTC_PSR_8B_tag PSR442; /* offset: 0x01FA size: 8 bit */
16566  INTC_PSR_8B_tag PSR443; /* offset: 0x01FB size: 8 bit */
16567  INTC_PSR_8B_tag PSR444; /* offset: 0x01FC size: 8 bit */
16568  INTC_PSR_8B_tag PSR445; /* offset: 0x01FD size: 8 bit */
16569  INTC_PSR_8B_tag PSR446; /* offset: 0x01FE size: 8 bit */
16570  INTC_PSR_8B_tag PSR447; /* offset: 0x01FF size: 8 bit */
16571  INTC_PSR_8B_tag PSR448; /* offset: 0x0200 size: 8 bit */
16572  INTC_PSR_8B_tag PSR449; /* offset: 0x0201 size: 8 bit */
16573  INTC_PSR_8B_tag PSR450; /* offset: 0x0202 size: 8 bit */
16574  INTC_PSR_8B_tag PSR451; /* offset: 0x0203 size: 8 bit */
16575  INTC_PSR_8B_tag PSR452; /* offset: 0x0204 size: 8 bit */
16576  INTC_PSR_8B_tag PSR453; /* offset: 0x0205 size: 8 bit */
16577  INTC_PSR_8B_tag PSR454; /* offset: 0x0206 size: 8 bit */
16578  INTC_PSR_8B_tag PSR455; /* offset: 0x0207 size: 8 bit */
16579  INTC_PSR_8B_tag PSR456; /* offset: 0x0208 size: 8 bit */
16580  INTC_PSR_8B_tag PSR457; /* offset: 0x0209 size: 8 bit */
16581  INTC_PSR_8B_tag PSR458; /* offset: 0x020A size: 8 bit */
16582  INTC_PSR_8B_tag PSR459; /* offset: 0x020B size: 8 bit */
16583  INTC_PSR_8B_tag PSR460; /* offset: 0x020C size: 8 bit */
16584  INTC_PSR_8B_tag PSR461; /* offset: 0x020D size: 8 bit */
16585  INTC_PSR_8B_tag PSR462; /* offset: 0x020E size: 8 bit */
16586  INTC_PSR_8B_tag PSR463; /* offset: 0x020F size: 8 bit */
16587  INTC_PSR_8B_tag PSR464; /* offset: 0x0210 size: 8 bit */
16588  INTC_PSR_8B_tag PSR465; /* offset: 0x0211 size: 8 bit */
16589  INTC_PSR_8B_tag PSR466; /* offset: 0x0212 size: 8 bit */
16590  INTC_PSR_8B_tag PSR467; /* offset: 0x0213 size: 8 bit */
16591  INTC_PSR_8B_tag PSR468; /* offset: 0x0214 size: 8 bit */
16592  INTC_PSR_8B_tag PSR469; /* offset: 0x0215 size: 8 bit */
16593  INTC_PSR_8B_tag PSR470; /* offset: 0x0216 size: 8 bit */
16594  INTC_PSR_8B_tag PSR471; /* offset: 0x0217 size: 8 bit */
16595  INTC_PSR_8B_tag PSR472; /* offset: 0x0218 size: 8 bit */
16596  INTC_PSR_8B_tag PSR473; /* offset: 0x0219 size: 8 bit */
16597  INTC_PSR_8B_tag PSR474; /* offset: 0x021A size: 8 bit */
16598  INTC_PSR_8B_tag PSR475; /* offset: 0x021B size: 8 bit */
16599  INTC_PSR_8B_tag PSR476; /* offset: 0x021C size: 8 bit */
16600  INTC_PSR_8B_tag PSR477; /* offset: 0x021D size: 8 bit */
16601  INTC_PSR_8B_tag PSR478; /* offset: 0x021E size: 8 bit */
16602  INTC_PSR_8B_tag PSR479; /* offset: 0x021F size: 8 bit */
16603  INTC_PSR_8B_tag PSR480; /* offset: 0x0220 size: 8 bit */
16604  INTC_PSR_8B_tag PSR481; /* offset: 0x0221 size: 8 bit */
16605  INTC_PSR_8B_tag PSR482; /* offset: 0x0222 size: 8 bit */
16606  INTC_PSR_8B_tag PSR483; /* offset: 0x0223 size: 8 bit */
16607  INTC_PSR_8B_tag PSR484; /* offset: 0x0224 size: 8 bit */
16608  INTC_PSR_8B_tag PSR485; /* offset: 0x0225 size: 8 bit */
16609  INTC_PSR_8B_tag PSR486; /* offset: 0x0226 size: 8 bit */
16610  INTC_PSR_8B_tag PSR487; /* offset: 0x0227 size: 8 bit */
16611  INTC_PSR_8B_tag PSR488; /* offset: 0x0228 size: 8 bit */
16612  INTC_PSR_8B_tag PSR489; /* offset: 0x0229 size: 8 bit */
16613  INTC_PSR_8B_tag PSR490; /* offset: 0x022A size: 8 bit */
16614  INTC_PSR_8B_tag PSR491; /* offset: 0x022B size: 8 bit */
16615  INTC_PSR_8B_tag PSR492; /* offset: 0x022C size: 8 bit */
16616  INTC_PSR_8B_tag PSR493; /* offset: 0x022D size: 8 bit */
16617  INTC_PSR_8B_tag PSR494; /* offset: 0x022E size: 8 bit */
16618  INTC_PSR_8B_tag PSR495; /* offset: 0x022F size: 8 bit */
16619  INTC_PSR_8B_tag PSR496; /* offset: 0x0230 size: 8 bit */
16620  INTC_PSR_8B_tag PSR497; /* offset: 0x0231 size: 8 bit */
16621  INTC_PSR_8B_tag PSR498; /* offset: 0x0232 size: 8 bit */
16622  INTC_PSR_8B_tag PSR499; /* offset: 0x0233 size: 8 bit */
16623  INTC_PSR_8B_tag PSR500; /* offset: 0x0234 size: 8 bit */
16624  INTC_PSR_8B_tag PSR501; /* offset: 0x0235 size: 8 bit */
16625  INTC_PSR_8B_tag PSR502; /* offset: 0x0236 size: 8 bit */
16626  INTC_PSR_8B_tag PSR503; /* offset: 0x0237 size: 8 bit */
16627  INTC_PSR_8B_tag PSR504; /* offset: 0x0238 size: 8 bit */
16628  INTC_PSR_8B_tag PSR505; /* offset: 0x0239 size: 8 bit */
16629  INTC_PSR_8B_tag PSR506; /* offset: 0x023A size: 8 bit */
16630  INTC_PSR_8B_tag PSR507; /* offset: 0x023B size: 8 bit */
16631  INTC_PSR_8B_tag PSR508; /* offset: 0x023C size: 8 bit */
16632  INTC_PSR_8B_tag PSR509; /* offset: 0x023D size: 8 bit */
16633  INTC_PSR_8B_tag PSR510; /* offset: 0x023E size: 8 bit */
16634  INTC_PSR_8B_tag PSR511; /* offset: 0x023F size: 8 bit */
16635  };
16636 
16637  };
16638  } INTC_tag;
16639 
16640 
16641 #define INTC (*(volatile INTC_tag *) 0xFFF48000UL)
16642 
16643 
16644 
16645 /****************************************************************/
16646 /* */
16647 /* Module: DSPI */
16648 /* */
16649 /****************************************************************/
16650 
16651  typedef union { /* MCR - Module Configuration Register */
16652  vuint32_t R;
16653  struct {
16654  vuint32_t MSTR:1; /* Master/Slave mode select */
16655  vuint32_t CONT_SCKE:1; /* Continuous SCK Enable */
16656  vuint32_t DCONF:2; /* DSPI Configuration */
16657  vuint32_t FRZ:1; /* Freeze */
16658  vuint32_t MTFE:1; /* Modified Timing Format Enable */
16659  vuint32_t PCSSE:1; /* Peripheral Chip Select Strobe Enable */
16660  vuint32_t ROOE:1; /* Receive FIFO Overflow Overwrite Enable */
16661  vuint32_t PCSIS7:1; /* Peripheral Chip Select 7 Inactive State */
16662  vuint32_t PCSIS6:1; /* Peripheral Chip Select 6 Inactive State */
16663  vuint32_t PCSIS5:1; /* Peripheral Chip Select 5 Inactive State */
16664  vuint32_t PCSIS4:1; /* Peripheral Chip Select 4 Inactive State */
16665  vuint32_t PCSIS3:1; /* Peripheral Chip Select 3 Inactive State */
16666  vuint32_t PCSIS2:1; /* Peripheral Chip Select 2 Inactive State */
16667  vuint32_t PCSIS1:1; /* Peripheral Chip Select 1 Inactive State */
16668  vuint32_t PCSIS0:1; /* Peripheral Chip Select 0 Inactive State */
16669  vuint32_t DOZE:1; /* Doze Enable */
16670  vuint32_t MDIS:1; /* Module Disable */
16671  vuint32_t DIS_TXF:1; /* Disable Transmit FIFO */
16672  vuint32_t DIS_RXF:1; /* Disable Receive FIFO */
16673  vuint32_t CLR_TXF:1; /* Clear TX FIFO */
16674  vuint32_t CLR_RXF:1; /* Clear RX FIFO */
16675  vuint32_t SMPL_PT:2; /* Sample Point */
16676  vuint32_t:7;
16677  vuint32_t HALT:1; /* Halt */
16678  } B;
16679  } DSPI_MCR_32B_tag;
16680 
16681  typedef union { /* TCR - Transfer Count Register */
16682  vuint32_t R;
16683  struct {
16684 #ifndef USE_FIELD_ALIASES_DSPI
16685  vuint32_t SPI_TCNT:16; /* SPI Transfer Counter */
16686 #else
16687  vuint32_t TCNT:16; /* deprecated name - please avoid */
16688 #endif
16689  vuint32_t:16;
16690  } B;
16691  } DSPI_TCR_32B_tag;
16692 
16693 
16694  /* Register layout for all registers CTAR... */
16695 
16696  typedef union { /* CTAR0-7 - Clock and Transfer Attribute Registers */
16697  vuint32_t R;
16698  struct {
16699  vuint32_t DBR:1; /* Double Baud Rate */
16700  vuint32_t FMSZ:4; /* Frame Size */
16701  vuint32_t CPOL:1; /* Clock Polarity */
16702  vuint32_t CPHA:1; /* Clock Phase */
16703  vuint32_t LSBFE:1; /* LSB First Enable */
16704  vuint32_t PCSSCK:2; /* PCS to SCK Delay Prescaler */
16705  vuint32_t PASC:2; /* After SCK Delay Prescaler */
16706  vuint32_t PDT:2; /* Delay after Transfer Prescaler */
16707  vuint32_t PBR:2; /* Baud Rate Prescaler */
16708  vuint32_t CSSCK:4; /* PCS to SCK Delay Scaler */
16709  vuint32_t ASC:4; /* After SCK Delay Scaler */
16710  vuint32_t DT:4; /* Delay after Transfer Scaler */
16711  vuint32_t BR:4; /* Baud Rate Scaler */
16712  } B;
16713  } DSPI_CTAR_32B_tag;
16714 
16715  typedef union { /* SR - Status Register */
16716  vuint32_t R;
16717  struct {
16718  vuint32_t TCF:1; /* Transfer Complete Flag */
16719  vuint32_t TXRXS:1; /* TX & RX Status */
16720  vuint32_t:1;
16721  vuint32_t EOQF:1; /* End of queue Flag */
16722  vuint32_t TFUF:1; /* Transmit FIFO Underflow Flag */
16723  vuint32_t:1;
16724  vuint32_t TFFF:1; /* Transmit FIFO FIll Flag */
16725  vuint32_t:5;
16726  vuint32_t RFOF:1; /* Receive FIFO Overflow Flag */
16727  vuint32_t:1;
16728  vuint32_t RFDF:1; /* Receive FIFO Drain Flag */
16729  vuint32_t:1;
16730  vuint32_t TXCTR:4; /* TX FIFO Counter */
16731  vuint32_t TXNXTPTR:4; /* Transmit Next Pointer */
16732  vuint32_t RXCTR:4; /* RX FIFO Counter */
16733  vuint32_t POPNXTPTR:4; /* Pop Next Pointer */
16734  } B;
16735  } DSPI_SR_32B_tag;
16736 
16737  typedef union { /* RSER - DMA/Interrupt Request Register */
16738  vuint32_t R;
16739  struct {
16740 #ifndef USE_FIELD_ALIASES_DSPI
16741  vuint32_t TCF_RE:1; /* Transmission Complete Request Enable */
16742 #else
16743  vuint32_t TCFRE:1; /* deprecated name - please avoid */
16744 #endif
16745  vuint32_t:2;
16746 #ifndef USE_FIELD_ALIASES_DSPI
16747  vuint32_t EOQF_RE:1; /* DSPI Finished Request Enable */
16748 #else
16749  vuint32_t EOQFRE:1; /* deprecated name - please avoid */
16750 #endif
16751 #ifndef USE_FIELD_ALIASES_DSPI
16752  vuint32_t TFUF_RE:1; /* Transmit FIFO Underflow Request Enable */
16753 #else
16754  vuint32_t TFUFRE:1; /* deprecated name - please avoid */
16755 #endif
16756  vuint32_t:1;
16757 #ifndef USE_FIELD_ALIASES_DSPI
16758  vuint32_t TFFF_RE:1; /* Transmit FIFO Fill Request Enable */
16759 #else
16760  vuint32_t TFFFRE:1; /* deprecated name - please avoid */
16761 #endif
16762 #ifndef USE_FIELD_ALIASES_DSPI
16763  vuint32_t TFFF_DIRS:1; /* Transmit FIFO Fill DMA or Interrupt Request Select */
16764 #else
16765  vuint32_t TFFFDIRS:1; /* deprecated name - please avoid */
16766 #endif
16767  vuint32_t:4;
16768 #ifndef USE_FIELD_ALIASES_DSPI
16769  vuint32_t RFOF_RE:1; /* Receive FIFO overflow Request Enable */
16770 #else
16771  vuint32_t RFOFRE:1; /* deprecated name - please avoid */
16772 #endif
16773  vuint32_t:1;
16774 #ifndef USE_FIELD_ALIASES_DSPI
16775  vuint32_t RFDF_RE:1; /* Receive FIFO Drain Request Enable */
16776 #else
16777  vuint32_t RFDFRE:1; /* deprecated name - please avoid */
16778 #endif
16779 #ifndef USE_FIELD_ALIASES_DSPI
16780  vuint32_t RFDF_DIRS:1; /* Receive FIFO Drain DMA or Interrupt Request Select */
16781 #else
16782  vuint32_t RFDFDIRS:1; /* deprecated name - please avoid */
16783 #endif
16784  vuint32_t:16;
16785  } B;
16786  } DSPI_RSER_32B_tag;
16787 
16788  typedef union { /* PUSHR - PUSH TX FIFO Register */
16789  vuint32_t R;
16790  struct {
16791  vuint32_t CONT:1; /* Continuous Peripheral Chip Select Enable */
16792  vuint32_t CTAS:3; /* Clock and Transfer Attributes Select */
16793  vuint32_t EOQ:1; /* End of Queue */
16794  vuint32_t CTCNT:1; /* Clear SPI_TCNT */
16795  vuint32_t:2;
16796  vuint32_t PCS7:1; /* Peripheral Chip Select 7 */
16797  vuint32_t PCS6:1; /* Peripheral Chip Select 6 */
16798  vuint32_t PCS5:1; /* Peripheral Chip Select 5 */
16799  vuint32_t PCS4:1; /* Peripheral Chip Select 4 */
16800  vuint32_t PCS3:1; /* Peripheral Chip Select 3 */
16801  vuint32_t PCS2:1; /* Peripheral Chip Select 2 */
16802  vuint32_t PCS1:1; /* Peripheral Chip Select 1 */
16803  vuint32_t PCS0:1; /* Peripheral Chip Select 0 */
16804  vuint32_t TXDATA:16; /* Transmit Data */
16805  } B;
16806  } DSPI_PUSHR_32B_tag;
16807 
16808  typedef union { /* POPR - POP RX FIFO Register */
16809  vuint32_t R;
16810  struct {
16811  vuint32_t:16;
16812  vuint32_t RXDATA:16; /* Receive Data */
16813  } B;
16814  } DSPI_POPR_32B_tag;
16815 
16816 
16817  /* Register layout for all registers TXFR... */
16818 
16819  typedef union { /* Transmit FIFO Registers */
16820  vuint32_t R;
16821  struct {
16822 #ifndef USE_FIELD_ALIASES_DSPI
16823  vuint32_t FIFO_TXCMD:16; /* Transmit Command */
16824 #else
16825  vuint32_t TXCMD:16; /* deprecated name - please avoid */
16826 #endif
16827 #ifndef USE_FIELD_ALIASES_DSPI
16828  vuint32_t FIFO_TXDATA:16; /* Transmit Data */
16829 #else
16830  vuint32_t TXDATA:16; /* deprecated name - please avoid */
16831 #endif
16832  } B;
16833  } DSPI_TXFR_32B_tag;
16834 
16835 
16836  /* Register layout for all registers RXFR... */
16837 
16838  typedef union { /* Receive FIFO Registers */
16839  vuint32_t R;
16840  struct {
16841  vuint32_t:16;
16842 #ifndef USE_FIELD_ALIASES_DSPI
16843  vuint32_t FIFO_RXDATA:16; /* Transmit Data */
16844 #else
16845  vuint32_t RXDATA:16; /* deprecated name - please avoid */
16846 #endif
16847  } B;
16848  } DSPI_RXFR_32B_tag;
16849 
16850  typedef union { /* DSICR - DSI Configuration Register */
16851  vuint32_t R;
16852  struct {
16853  vuint32_t MTOE:1; /* Multiple Transfer Operation Enable */
16854  vuint32_t:1;
16855  vuint32_t MTOCNT:6; /* Multiple Transfer Operation Count */
16856  vuint32_t:4;
16857  vuint32_t TXSS:1; /* Transmit Data Source Select */
16858  vuint32_t TPOL:1; /* Trigger Polarity */
16859  vuint32_t TRRE:1; /* Trigger Reception Enable */
16860  vuint32_t CID:1; /* Change in Data Transfer Enable */
16861  vuint32_t DCONT:1; /* DSI Continuous Peripheral Chip Select Enable */
16862  vuint32_t DSICTAS:3; /* DSI CLock and Transfer Attributes Select */
16863  vuint32_t:4;
16864  vuint32_t DPCS7:1; /* DSI Peripheral Chip Select 7 */
16865  vuint32_t DPCS6:1; /* DSI Peripheral Chip Select 6 */
16866  vuint32_t DPCS5:1; /* DSI Peripheral Chip Select 5 */
16867  vuint32_t DPCS4:1; /* DSI Peripheral Chip Select 4 */
16868  vuint32_t DPCS3:1; /* DSI Peripheral Chip Select 3 */
16869  vuint32_t DPCS2:1; /* DSI Peripheral Chip Select 2 */
16870  vuint32_t DPCS1:1; /* DSI Peripheral Chip Select 1 */
16871  vuint32_t DPCS0:1; /* DSI Peripheral Chip Select 0 */
16872  } B;
16873  } DSPI_DSICR_32B_tag;
16874 
16875  typedef union { /* SDR - DSI Serialization Data Register */
16876  vuint32_t R;
16877  struct {
16878  vuint32_t:16;
16879  vuint32_t SER_DATA:16; /* Serialized Data */
16880  } B;
16881  } DSPI_SDR_32B_tag;
16882 
16883  typedef union { /* ASDR - DSI Alternate Serialization Data Register */
16884  vuint32_t R;
16885  struct {
16886  vuint32_t:16;
16887  vuint32_t ASER_DATA:16; /* Alternate Serialized Data */
16888  } B;
16889  } DSPI_ASDR_32B_tag;
16890 
16891  typedef union { /* COMPR - DSI Transmit Comparison Register */
16892  vuint32_t R;
16893  struct {
16894  vuint32_t:16;
16895  vuint32_t COMP_DATA:16; /* Compare Data */
16896  } B;
16897  } DSPI_COMPR_32B_tag;
16898 
16899  typedef union { /* DDR - DSI Deserialization Data Register */
16900  vuint32_t R;
16901  struct {
16902  vuint32_t:16;
16903  vuint32_t DESER_DATA:16; /* Deserialized Data */
16904  } B;
16905  } DSPI_DDR_32B_tag;
16906 
16907  typedef union { /* DSICR1 - DSI Configuration Register 1 */
16908  vuint32_t R;
16909  } DSPI_DSICR1_32B_tag;
16910 
16911 
16912 
16913  typedef struct DSPI_struct_tag { /* start of DSPI_tag */
16914  /* MCR - Module Configuration Register */
16915  DSPI_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */
16916  int8_t DSPI_reserved_0004[4];
16917  /* TCR - Transfer Count Register */
16918  DSPI_TCR_32B_tag TCR; /* offset: 0x0008 size: 32 bit */
16919  union {
16920  /* CTAR0-7 - Clock and Transfer Attribute Registers */
16921  DSPI_CTAR_32B_tag CTAR[8]; /* offset: 0x000C (0x0004 x 8) */
16922 
16923  struct {
16924  /* CTAR0-7 - Clock and Transfer Attribute Registers */
16925  DSPI_CTAR_32B_tag CTAR0; /* offset: 0x000C size: 32 bit */
16926  DSPI_CTAR_32B_tag CTAR1; /* offset: 0x0010 size: 32 bit */
16927  DSPI_CTAR_32B_tag CTAR2; /* offset: 0x0014 size: 32 bit */
16928  DSPI_CTAR_32B_tag CTAR3; /* offset: 0x0018 size: 32 bit */
16929  DSPI_CTAR_32B_tag CTAR4; /* offset: 0x001C size: 32 bit */
16930  DSPI_CTAR_32B_tag CTAR5; /* offset: 0x0020 size: 32 bit */
16931  DSPI_CTAR_32B_tag CTAR6; /* offset: 0x0024 size: 32 bit */
16932  DSPI_CTAR_32B_tag CTAR7; /* offset: 0x0028 size: 32 bit */
16933  };
16934 
16935  };
16936  /* SR - Status Register */
16937  DSPI_SR_32B_tag SR; /* offset: 0x002C size: 32 bit */
16938  /* RSER - DMA/Interrupt Request Register */
16939  DSPI_RSER_32B_tag RSER; /* offset: 0x0030 size: 32 bit */
16940  /* PUSHR - PUSH TX FIFO Register */
16941  DSPI_PUSHR_32B_tag PUSHR; /* offset: 0x0034 size: 32 bit */
16942  /* POPR - POP RX FIFO Register */
16943  DSPI_POPR_32B_tag POPR; /* offset: 0x0038 size: 32 bit */
16944  union {
16945  /* Transmit FIFO Registers */
16946  DSPI_TXFR_32B_tag TXFR[5]; /* offset: 0x003C (0x0004 x 5) */
16947 
16948  struct {
16949  /* Transmit FIFO Registers */
16950  DSPI_TXFR_32B_tag TXFR0; /* offset: 0x003C size: 32 bit */
16951  DSPI_TXFR_32B_tag TXFR1; /* offset: 0x0040 size: 32 bit */
16952  DSPI_TXFR_32B_tag TXFR2; /* offset: 0x0044 size: 32 bit */
16953  DSPI_TXFR_32B_tag TXFR3; /* offset: 0x0048 size: 32 bit */
16954  DSPI_TXFR_32B_tag TXFR4; /* offset: 0x004C size: 32 bit */
16955  };
16956 
16957  };
16958  int8_t DSPI_reserved_0050_C[44];
16959  union {
16960  /* Receive FIFO Registers */
16961  DSPI_RXFR_32B_tag RXFR[5]; /* offset: 0x007C (0x0004 x 5) */
16962 
16963  struct {
16964  /* Receive FIFO Registers */
16965  DSPI_RXFR_32B_tag RXFR0; /* offset: 0x007C size: 32 bit */
16966  DSPI_RXFR_32B_tag RXFR1; /* offset: 0x0080 size: 32 bit */
16967  DSPI_RXFR_32B_tag RXFR2; /* offset: 0x0084 size: 32 bit */
16968  DSPI_RXFR_32B_tag RXFR3; /* offset: 0x0088 size: 32 bit */
16969  DSPI_RXFR_32B_tag RXFR4; /* offset: 0x008C size: 32 bit */
16970  };
16971 
16972  };
16973  int8_t DSPI_reserved_0090[44];
16974  /* DSICR - DSI Configuration Register */
16975  DSPI_DSICR_32B_tag DSICR; /* offset: 0x00BC size: 32 bit */
16976  /* SDR - DSI Serialization Data Register */
16977  DSPI_SDR_32B_tag SDR; /* offset: 0x00C0 size: 32 bit */
16978  /* ASDR - DSI Alternate Serialization Data Register */
16979  DSPI_ASDR_32B_tag ASDR; /* offset: 0x00C4 size: 32 bit */
16980  /* COMPR - DSI Transmit Comparison Register */
16981  DSPI_COMPR_32B_tag COMPR; /* offset: 0x00C8 size: 32 bit */
16982  /* DDR - DSI Deserialization Data Register */
16983  DSPI_DDR_32B_tag DDR; /* offset: 0x00CC size: 32 bit */
16984  /* DSICR1 - DSI Configuration Register 1 */
16985  DSPI_DSICR1_32B_tag DSICR1; /* offset: 0x00D0 size: 32 bit */
16986  } DSPI_tag;
16987 
16988 
16989 #define DSPI_A (*(volatile DSPI_tag *) 0xFFF90000UL)
16990 #define DSPI_B (*(volatile DSPI_tag *) 0xFFF94000UL)
16991 #define DSPI_C (*(volatile DSPI_tag *) 0xFFF98000UL)
16992 
16993 
16994 
16995 /****************************************************************/
16996 /* */
16997 /* Module: FLEXCAN */
16998 /* */
16999 /****************************************************************/
17000 
17001  typedef union { /* MCR - Module Configuration Register */
17002  vuint32_t R;
17003  struct {
17004  vuint32_t MDIS:1; /* Module Disable */
17005  vuint32_t FRZ:1; /* Freeze Enable */
17006  vuint32_t FEN:1; /* FIFO Enable */
17007  vuint32_t HALT:1; /* Halt Flexcan */
17008 #ifndef USE_FIELD_ALIASES_FLEXCAN
17009  vuint32_t NOT_RDY:1; /* Flexcan Not Ready */
17010 #else
17011  vuint32_t NOTRDY:1; /* deprecated name - please avoid */
17012 #endif
17013 #ifndef USE_FIELD_ALIASES_FLEXCAN
17014  vuint32_t WAK_MSK:1; /* Wake Up Interrupt Mask */
17015 #else
17016  vuint32_t WAKMSK:1; /* deprecated name - please avoid */
17017 #endif
17018 #ifndef USE_FIELD_ALIASES_FLEXCAN
17019  vuint32_t SOFT_RST:1; /* Soft Reset */
17020 #else
17021  vuint32_t SOFTRST:1; /* deprecated name - please avoid */
17022 #endif
17023 #ifndef USE_FIELD_ALIASES_FLEXCAN
17024  vuint32_t FRZ_ACK:1; /* Freeze Mode Acknowledge */
17025 #else
17026  vuint32_t FRZACK:1; /* deprecated name - please avoid */
17027 #endif
17028  vuint32_t SUPV:1; /* Supervisor Mode */
17029 #ifndef USE_FIELD_ALIASES_FLEXCAN
17030  vuint32_t SLF_WAK:1; /* Self Wake Up */
17031 #else
17032  vuint32_t SLFWAK:1; /* deprecated name - please avoid */
17033 #endif
17034 #ifndef USE_FIELD_ALIASES_FLEXCAN
17035  vuint32_t WRN_EN:1; /* Warning Interrupt Enable */
17036 #else
17037  vuint32_t WRNEN:1; /* deprecated name - please avoid */
17038 #endif
17039 #ifndef USE_FIELD_ALIASES_FLEXCAN
17040  vuint32_t LPM_ACK:1; /* Low Power Mode Acknowledge */
17041 #else
17042  vuint32_t LPMACK:1; /* deprecated name - please avoid */
17043 #endif
17044 #ifndef USE_FIELD_ALIASES_FLEXCAN
17045  vuint32_t WAK_SRC:1; /* Wake Up Source */
17046 #else
17047  vuint32_t WAKSRC:1; /* deprecated name - please avoid */
17048 #endif
17049  vuint32_t DOZE:1; /* Doze Mode Enable */
17050 #ifndef USE_FIELD_ALIASES_FLEXCAN
17051  vuint32_t SRX_DIS:1; /* Self Reception Disable */
17052 #else
17053  vuint32_t SRXDIS:1; /* deprecated name - please avoid */
17054 #endif
17055  vuint32_t BCC:1; /* Backwards Compatibility Configuration */
17056  vuint32_t:2;
17057  vuint32_t LPRIO_EN:1; /* Local Priority Enable */
17058  vuint32_t AEN:1; /* Abort Enable */
17059  vuint32_t:2;
17060  vuint32_t IDAM:2; /* ID Acceptance Mode */
17061  vuint32_t:2;
17062  vuint32_t MAXMB:6; /* Maximum Number of Message Buffers */
17063  } B;
17064  } FLEXCAN_MCR_32B_tag;
17065 
17066  typedef union { /* CTRL - Control Register */
17067  vuint32_t R;
17068  struct {
17069  vuint32_t PRESDIV:8; /* Prescaler Divsion Factor */
17070  vuint32_t RJW:2; /* Resync Jump Width */
17071  vuint32_t PSEG1:3; /* Phase Segment 1 */
17072  vuint32_t PSEG2:3; /* Phase Segment 2 */
17073 #ifndef USE_FIELD_ALIASES_FLEXCAN
17074  vuint32_t BOFF_MSK:1; /* Bus Off Mask */
17075 #else
17076  vuint32_t BOFFMSK:1; /* deprecated name - please avoid */
17077 #endif
17078 #ifndef USE_FIELD_ALIASES_FLEXCAN
17079  vuint32_t ERR_MSK:1; /* Error Mask */
17080 #else
17081  vuint32_t ERRMSK:1; /* deprecated name - please avoid */
17082 #endif
17083 #ifndef USE_FIELD_ALIASES_FLEXCAN
17084  vuint32_t CLK_SRC:1; /* CAN Engine Clock Source */
17085 #else
17086  vuint32_t CLKSRC:1; /* deprecated name - please avoid */
17087 #endif
17088  vuint32_t LPB:1; /* Loop Back */
17089 #ifndef USE_FIELD_ALIASES_FLEXCAN
17090  vuint32_t TWRN_MSK:1; /* Tx Warning Interrupt Mask */
17091 #else
17092  vuint32_t TWRNMSK:1; /* deprecated name - please avoid */
17093 #endif
17094 #ifndef USE_FIELD_ALIASES_FLEXCAN
17095  vuint32_t RWRN_MSK:1; /* Rx Warning Interrupt Mask */
17096 #else
17097  vuint32_t RWRNMSK:1; /* deprecated name - please avoid */
17098 #endif
17099  vuint32_t:2;
17100  vuint32_t SMP:1; /* Sampling Mode */
17101 #ifndef USE_FIELD_ALIASES_FLEXCAN
17102  vuint32_t BOFF_REC:1; /* Bus Off Recovery Mode */
17103 #else
17104  vuint32_t BOFFREC:1; /* deprecated name - please avoid */
17105 #endif
17106  vuint32_t TSYN:1; /* Timer Sync Mode */
17107  vuint32_t LBUF:1; /* Lowest Buffer Transmitted First */
17108  vuint32_t LOM:1; /* Listen-Only Mode */
17109  vuint32_t PROPSEG:3; /* Propagation Segment */
17110  } B;
17111  } FLEXCAN_CTRL_32B_tag;
17112 
17113  typedef union { /* TIMER - Free Running Timer */
17114  vuint32_t R;
17115  } FLEXCAN_TIMER_32B_tag;
17116 
17117  typedef union { /* RXGMASK - Rx Global Mask Register */
17118  vuint32_t R;
17119 #ifndef USE_FIELD_ALIASES_FLEXCAN
17120  struct {
17121  vuint32_t MI:32; /* deprecated field -- do not use */
17122  } B;
17123 #endif
17124  } FLEXCAN_RXGMASK_32B_tag;
17125 
17126  typedef union { /* RX14MASK - Rx 14 Mask Register */
17127  vuint32_t R;
17128 #ifndef USE_FIELD_ALIASES_FLEXCAN
17129  struct {
17130  vuint32_t MI:32; /* deprecated field -- do not use */
17131  } B;
17132 #endif
17133  } FLEXCAN_RX14MASK_32B_tag;
17134 
17135  typedef union { /* RX15MASK - Rx 15 Mask Register */
17136  vuint32_t R;
17137 #ifndef USE_FIELD_ALIASES_FLEXCAN
17138  struct {
17139  vuint32_t MI:32; /* deprecated field -- do not use */
17140  } B;
17141 #endif
17142  } FLEXCAN_RX15MASK_32B_tag;
17143 
17144  typedef union { /* ECR - Error Counter Register */
17145  vuint32_t R;
17146  struct {
17147  vuint32_t:16;
17148 #ifndef USE_FIELD_ALIASES_FLEXCAN
17149  vuint32_t RX_ERR_COUNTER:8; /* Rx Error Counter */
17150 #else
17151  vuint32_t RXECNT:8; /* deprecated name - please avoid */
17152 #endif
17153 #ifndef USE_FIELD_ALIASES_FLEXCAN
17154  vuint32_t TX_ERR_COUNTER:8; /* Tx Error Counter */
17155 #else
17156  vuint32_t TXECNT:8; /* deprecated name - please avoid */
17157 #endif
17158  } B;
17159  } FLEXCAN_ECR_32B_tag;
17160 
17161  typedef union { /* ESR - Error and Status Register */
17162  vuint32_t R;
17163  struct {
17164  vuint32_t:14;
17165 #ifndef USE_FIELD_ALIASES_FLEXCAN
17166  vuint32_t TWRN_INT:1; /* Tx Warning Interrupt Flag */
17167 #else
17168  vuint32_t TWRNINT:1; /* deprecated name - please avoid */
17169 #endif
17170 #ifndef USE_FIELD_ALIASES_FLEXCAN
17171  vuint32_t RWRN_INT:1; /* Rx Warning Interrupt Flag */
17172 #else
17173  vuint32_t RWRNINT:1; /* deprecated name - please avoid */
17174 #endif
17175 #ifndef USE_FIELD_ALIASES_FLEXCAN
17176  vuint32_t BIT1_ERR:1; /* Bit 1 Error */
17177 #else
17178  vuint32_t BIT1ERR:1; /* deprecated name - please avoid */
17179 #endif
17180 #ifndef USE_FIELD_ALIASES_FLEXCAN
17181  vuint32_t BIT0_ERR:1; /* Bit 0 Error */
17182 #else
17183  vuint32_t BIT0ERR:1; /* deprecated name - please avoid */
17184 #endif
17185 #ifndef USE_FIELD_ALIASES_FLEXCAN
17186  vuint32_t ACK_ERR:1; /* Acknowledge Error */
17187 #else
17188  vuint32_t ACKERR:1; /* deprecated name - please avoid */
17189 #endif
17190 #ifndef USE_FIELD_ALIASES_FLEXCAN
17191  vuint32_t CRC_ERR:1; /* Cyclic Redundancy Check Error */
17192 #else
17193  vuint32_t CRCERR:1; /* deprecated name - please avoid */
17194 #endif
17195 #ifndef USE_FIELD_ALIASES_FLEXCAN
17196  vuint32_t FRM_ERR:1; /* Form Error */
17197 #else
17198  vuint32_t FRMERR:1; /* deprecated name - please avoid */
17199 #endif
17200 #ifndef USE_FIELD_ALIASES_FLEXCAN
17201  vuint32_t STF_ERR:1; /* Stuffing Error */
17202 #else
17203  vuint32_t STFERR:1; /* deprecated name - please avoid */
17204 #endif
17205 #ifndef USE_FIELD_ALIASES_FLEXCAN
17206  vuint32_t TX_WRN:1; /* Tx Error Counter */
17207 #else
17208  vuint32_t TXWRN:1; /* deprecated name - please avoid */
17209 #endif
17210 #ifndef USE_FIELD_ALIASES_FLEXCAN
17211  vuint32_t RX_WRN:1; /* Rx Error Counter */
17212 #else
17213  vuint32_t RXWRN:1; /* deprecated name - please avoid */
17214 #endif
17215  vuint32_t IDLE:1; /* CAN bus Idle State */
17216  vuint32_t TXRX:1; /* Current Flexcan Status */
17217 #ifndef USE_FIELD_ALIASES_FLEXCAN
17218  vuint32_t FLT_CONF:2; /* Fault Confinement State */
17219 #else
17220  vuint32_t FLTCONF:2; /* deprecated name - please avoid */
17221 #endif
17222  vuint32_t:1;
17223 #ifndef USE_FIELD_ALIASES_FLEXCAN
17224  vuint32_t BOFF_INT:1; /* Bus Off Interrupt */
17225 #else
17226  vuint32_t BOFFINT:1; /* deprecated name - please avoid */
17227 #endif
17228 #ifndef USE_FIELD_ALIASES_FLEXCAN
17229  vuint32_t ERR_INT:1; /* Error Interrupt */
17230 #else
17231  vuint32_t ERRINT:1; /* deprecated name - please avoid */
17232 #endif
17233 #ifndef USE_FIELD_ALIASES_FLEXCAN
17234  vuint32_t WAK_INT:1; /* Wake-Up Interrupt */
17235 #else
17236  vuint32_t WAKINT:1; /* deprecated name - please avoid */
17237 #endif
17238  } B;
17239  } FLEXCAN_ESR_32B_tag;
17240 
17241  typedef union { /* IMASK2 - Interrupt Masks 2 Register */
17242  vuint32_t R;
17243  struct {
17244  vuint32_t BUF63M:1; /* Buffer MB Mask 63 Bit */
17245  vuint32_t BUF62M:1; /* Buffer MB Mask 62 Bit */
17246  vuint32_t BUF61M:1; /* Buffer MB Mask 61 Bit */
17247  vuint32_t BUF60M:1; /* Buffer MB Mask 60 Bit */
17248  vuint32_t BUF59M:1; /* Buffer MB Mask 59 Bit */
17249  vuint32_t BUF58M:1; /* Buffer MB Mask 58 Bit */
17250  vuint32_t BUF57M:1; /* Buffer MB Mask 57 Bit */
17251  vuint32_t BUF56M:1; /* Buffer MB Mask 56 Bit */
17252  vuint32_t BUF55M:1; /* Buffer MB Mask 55 Bit */
17253  vuint32_t BUF54M:1; /* Buffer MB Mask 54 Bit */
17254  vuint32_t BUF53M:1; /* Buffer MB Mask 53 Bit */
17255  vuint32_t BUF52M:1; /* Buffer MB Mask 52 Bit */
17256  vuint32_t BUF51M:1; /* Buffer MB Mask 51 Bit */
17257  vuint32_t BUF50M:1; /* Buffer MB Mask 50 Bit */
17258  vuint32_t BUF49M:1; /* Buffer MB Mask 49 Bit */
17259  vuint32_t BUF48M:1; /* Buffer MB Mask 48 Bit */
17260  vuint32_t BUF47M:1; /* Buffer MB Mask 47 Bit */
17261  vuint32_t BUF46M:1; /* Buffer MB Mask 46 Bit */
17262  vuint32_t BUF45M:1; /* Buffer MB Mask 45 Bit */
17263  vuint32_t BUF44M:1; /* Buffer MB Mask 44 Bit */
17264  vuint32_t BUF43M:1; /* Buffer MB Mask 43 Bit */
17265  vuint32_t BUF42M:1; /* Buffer MB Mask 42 Bit */
17266  vuint32_t BUF41M:1; /* Buffer MB Mask 41 Bit */
17267  vuint32_t BUF40M:1; /* Buffer MB Mask 40 Bit */
17268  vuint32_t BUF39M:1; /* Buffer MB Mask 39 Bit */
17269  vuint32_t BUF38M:1; /* Buffer MB Mask 38 Bit */
17270  vuint32_t BUF37M:1; /* Buffer MB Mask 37 Bit */
17271  vuint32_t BUF36M:1; /* Buffer MB Mask 36 Bit */
17272  vuint32_t BUF35M:1; /* Buffer MB Mask 35 Bit */
17273  vuint32_t BUF34M:1; /* Buffer MB Mask 34 Bit */
17274  vuint32_t BUF33M:1; /* Buffer MB Mask 33 Bit */
17275  vuint32_t BUF32M:1; /* Buffer MB Mask 32 Bit */
17276  } B;
17277  } FLEXCAN_IMASK2_32B_tag;
17278 
17279  typedef union { /* IMASK1 - Interrupt Masks 1 Register */
17280  vuint32_t R;
17281  struct {
17282  vuint32_t BUF31M:1; /* Buffer MB Mask 31 Bit */
17283  vuint32_t BUF30M:1; /* Buffer MB Mask 30 Bit */
17284  vuint32_t BUF29M:1; /* Buffer MB Mask 29 Bit */
17285  vuint32_t BUF28M:1; /* Buffer MB Mask 28 Bit */
17286  vuint32_t BUF27M:1; /* Buffer MB Mask 27 Bit */
17287  vuint32_t BUF26M:1; /* Buffer MB Mask 26 Bit */
17288  vuint32_t BUF25M:1; /* Buffer MB Mask 25 Bit */
17289  vuint32_t BUF24M:1; /* Buffer MB Mask 24 Bit */
17290  vuint32_t BUF23M:1; /* Buffer MB Mask 23 Bit */
17291  vuint32_t BUF22M:1; /* Buffer MB Mask 22 Bit */
17292  vuint32_t BUF21M:1; /* Buffer MB Mask 21 Bit */
17293  vuint32_t BUF20M:1; /* Buffer MB Mask 20 Bit */
17294  vuint32_t BUF19M:1; /* Buffer MB Mask 19 Bit */
17295  vuint32_t BUF18M:1; /* Buffer MB Mask 18 Bit */
17296  vuint32_t BUF17M:1; /* Buffer MB Mask 17 Bit */
17297  vuint32_t BUF16M:1; /* Buffer MB Mask 16 Bit */
17298  vuint32_t BUF15M:1; /* Buffer MB Mask 15 Bit */
17299  vuint32_t BUF14M:1; /* Buffer MB Mask 14 Bit */
17300  vuint32_t BUF13M:1; /* Buffer MB Mask 13 Bit */
17301  vuint32_t BUF12M:1; /* Buffer MB Mask 12 Bit */
17302  vuint32_t BUF11M:1; /* Buffer MB Mask 11 Bit */
17303  vuint32_t BUF10M:1; /* Buffer MB Mask 10 Bit */
17304 #ifndef USE_FIELD_ALIASES_FLEXCAN
17305  vuint32_t BUF9M:1; /* Buffer MB Mask 9 Bit */
17306 #else
17307  vuint32_t BUF09M:1; /* deprecated name - please avoid */
17308 #endif
17309 #ifndef USE_FIELD_ALIASES_FLEXCAN
17310  vuint32_t BUF8M:1; /* Buffer MB Mask 8 Bit */
17311 #else
17312  vuint32_t BUF08M:1; /* deprecated name - please avoid */
17313 #endif
17314 #ifndef USE_FIELD_ALIASES_FLEXCAN
17315  vuint32_t BUF7M:1; /* Buffer MB Mask 7 Bit */
17316 #else
17317  vuint32_t BUF07M:1; /* deprecated name - please avoid */
17318 #endif
17319 #ifndef USE_FIELD_ALIASES_FLEXCAN
17320  vuint32_t BUF6M:1; /* Buffer MB Mask 6 Bit */
17321 #else
17322  vuint32_t BUF06M:1; /* deprecated name - please avoid */
17323 #endif
17324 #ifndef USE_FIELD_ALIASES_FLEXCAN
17325  vuint32_t BUF5M:1; /* Buffer MB Mask 5 Bit */
17326 #else
17327  vuint32_t BUF05M:1; /* deprecated name - please avoid */
17328 #endif
17329 #ifndef USE_FIELD_ALIASES_FLEXCAN
17330  vuint32_t BUF4M:1; /* Buffer MB Mask 4 Bit */
17331 #else
17332  vuint32_t BUF04M:1; /* deprecated name - please avoid */
17333 #endif
17334 #ifndef USE_FIELD_ALIASES_FLEXCAN
17335  vuint32_t BUF3M:1; /* Buffer MB Mask 3 Bit */
17336 #else
17337  vuint32_t BUF03M:1; /* deprecated name - please avoid */
17338 #endif
17339 #ifndef USE_FIELD_ALIASES_FLEXCAN
17340  vuint32_t BUF2M:1; /* Buffer MB Mask 2 Bit */
17341 #else
17342  vuint32_t BUF02M:1; /* deprecated name - please avoid */
17343 #endif
17344 #ifndef USE_FIELD_ALIASES_FLEXCAN
17345  vuint32_t BUF1M:1; /* Buffer MB Mask 1 Bit */
17346 #else
17347  vuint32_t BUF01M:1; /* deprecated name - please avoid */
17348 #endif
17349 #ifndef USE_FIELD_ALIASES_FLEXCAN
17350  vuint32_t BUF0M:1; /* Buffer MB Mask 0 Bit */
17351 #else
17352  vuint32_t BUF00M:1; /* deprecated name - please avoid */
17353 #endif
17354  } B;
17355  } FLEXCAN_IMASK1_32B_tag;
17356 
17357  typedef union { /* IFLAG2 - Interrupt Flags 2 Register */
17358  vuint32_t R;
17359  struct {
17360  vuint32_t BUF63I:1; /* Buffer MB Interrupt 63 Bit */
17361  vuint32_t BUF62I:1; /* Buffer MB Interrupt 62 Bit */
17362  vuint32_t BUF61I:1; /* Buffer MB Interrupt 61 Bit */
17363  vuint32_t BUF60I:1; /* Buffer MB Interrupt 60 Bit */
17364  vuint32_t BUF59I:1; /* Buffer MB Interrupt 59 Bit */
17365  vuint32_t BUF58I:1; /* Buffer MB Interrupt 58 Bit */
17366  vuint32_t BUF57I:1; /* Buffer MB Interrupt 57 Bit */
17367  vuint32_t BUF56I:1; /* Buffer MB Interrupt 56 Bit */
17368  vuint32_t BUF55I:1; /* Buffer MB Interrupt 55 Bit */
17369  vuint32_t BUF54I:1; /* Buffer MB Interrupt 54 Bit */
17370  vuint32_t BUF53I:1; /* Buffer MB Interrupt 53 Bit */
17371  vuint32_t BUF52I:1; /* Buffer MB Interrupt 52 Bit */
17372  vuint32_t BUF51I:1; /* Buffer MB Interrupt 51 Bit */
17373  vuint32_t BUF50I:1; /* Buffer MB Interrupt 50 Bit */
17374  vuint32_t BUF49I:1; /* Buffer MB Interrupt 49 Bit */
17375  vuint32_t BUF48I:1; /* Buffer MB Interrupt 48 Bit */
17376  vuint32_t BUF47I:1; /* Buffer MB Interrupt 47 Bit */
17377  vuint32_t BUF46I:1; /* Buffer MB Interrupt 46 Bit */
17378  vuint32_t BUF45I:1; /* Buffer MB Interrupt 45 Bit */
17379  vuint32_t BUF44I:1; /* Buffer MB Interrupt 44 Bit */
17380  vuint32_t BUF43I:1; /* Buffer MB Interrupt 43 Bit */
17381  vuint32_t BUF42I:1; /* Buffer MB Interrupt 42 Bit */
17382  vuint32_t BUF41I:1; /* Buffer MB Interrupt 41 Bit */
17383  vuint32_t BUF40I:1; /* Buffer MB Interrupt 40 Bit */
17384  vuint32_t BUF39I:1; /* Buffer MB Interrupt 39 Bit */
17385  vuint32_t BUF38I:1; /* Buffer MB Interrupt 38 Bit */
17386  vuint32_t BUF37I:1; /* Buffer MB Interrupt 37 Bit */
17387  vuint32_t BUF36I:1; /* Buffer MB Interrupt 36 Bit */
17388  vuint32_t BUF35I:1; /* Buffer MB Interrupt 35 Bit */
17389  vuint32_t BUF34I:1; /* Buffer MB Interrupt 34 Bit */
17390  vuint32_t BUF33I:1; /* Buffer MB Interrupt 33 Bit */
17391  vuint32_t BUF32I:1; /* Buffer MB Interrupt 32 Bit */
17392  } B;
17393  } FLEXCAN_IFLAG2_32B_tag;
17394 
17395  typedef union { /* IFLAG1 - Interrupt Flags 1 Register */
17396  vuint32_t R;
17397  struct {
17398  vuint32_t BUF31I:1; /* Buffer MB Interrupt 31 Bit */
17399  vuint32_t BUF30I:1; /* Buffer MB Interrupt 30 Bit */
17400  vuint32_t BUF29I:1; /* Buffer MB Interrupt 29 Bit */
17401  vuint32_t BUF28I:1; /* Buffer MB Interrupt 28 Bit */
17402  vuint32_t BUF27I:1; /* Buffer MB Interrupt 27 Bit */
17403  vuint32_t BUF26I:1; /* Buffer MB Interrupt 26 Bit */
17404  vuint32_t BUF25I:1; /* Buffer MB Interrupt 25 Bit */
17405  vuint32_t BUF24I:1; /* Buffer MB Interrupt 24 Bit */
17406  vuint32_t BUF23I:1; /* Buffer MB Interrupt 23 Bit */
17407  vuint32_t BUF22I:1; /* Buffer MB Interrupt 22 Bit */
17408  vuint32_t BUF21I:1; /* Buffer MB Interrupt 21 Bit */
17409  vuint32_t BUF20I:1; /* Buffer MB Interrupt 20 Bit */
17410  vuint32_t BUF19I:1; /* Buffer MB Interrupt 19 Bit */
17411  vuint32_t BUF18I:1; /* Buffer MB Interrupt 18 Bit */
17412  vuint32_t BUF17I:1; /* Buffer MB Interrupt 17 Bit */
17413  vuint32_t BUF16I:1; /* Buffer MB Interrupt 16 Bit */
17414  vuint32_t BUF15I:1; /* Buffer MB Interrupt 15 Bit */
17415  vuint32_t BUF14I:1; /* Buffer MB Interrupt 14 Bit */
17416  vuint32_t BUF13I:1; /* Buffer MB Interrupt 13 Bit */
17417  vuint32_t BUF12I:1; /* Buffer MB Interrupt 12 Bit */
17418  vuint32_t BUF11I:1; /* Buffer MB Interrupt 11 Bit */
17419  vuint32_t BUF10I:1; /* Buffer MB Interrupt 10 Bit */
17420 #ifndef USE_FIELD_ALIASES_FLEXCAN
17421  vuint32_t BUF9I:1; /* Buffer MB Interrupt 9 Bit */
17422 #else
17423  vuint32_t BUF09I:1; /* deprecated name - please avoid */
17424 #endif
17425 #ifndef USE_FIELD_ALIASES_FLEXCAN
17426  vuint32_t BUF8I:1; /* Buffer MB Interrupt 8 Bit */
17427 #else
17428  vuint32_t BUF08I:1; /* deprecated name - please avoid */
17429 #endif
17430 #ifndef USE_FIELD_ALIASES_FLEXCAN
17431  vuint32_t BUF7I:1; /* Buffer MB Interrupt 7 Bit */
17432 #else
17433  vuint32_t BUF07I:1; /* deprecated name - please avoid */
17434 #endif
17435 #ifndef USE_FIELD_ALIASES_FLEXCAN
17436  vuint32_t BUF6I:1; /* Buffer MB Interrupt 6 Bit */
17437 #else
17438  vuint32_t BUF06I:1; /* deprecated name - please avoid */
17439 #endif
17440 #ifndef USE_FIELD_ALIASES_FLEXCAN
17441  vuint32_t BUF5I:1; /* Buffer MB Interrupt 5 Bit */
17442 #else
17443  vuint32_t BUF05I:1; /* deprecated name - please avoid */
17444 #endif
17445 #ifndef USE_FIELD_ALIASES_FLEXCAN
17446  vuint32_t BUF4I:1; /* Buffer MB Interrupt 4 Bit */
17447 #else
17448  vuint32_t BUF04I:1; /* deprecated name - please avoid */
17449 #endif
17450 #ifndef USE_FIELD_ALIASES_FLEXCAN
17451  vuint32_t BUF3I:1; /* Buffer MB Interrupt 3 Bit */
17452 #else
17453  vuint32_t BUF03I:1; /* deprecated name - please avoid */
17454 #endif
17455 #ifndef USE_FIELD_ALIASES_FLEXCAN
17456  vuint32_t BUF2I:1; /* Buffer MB Interrupt 2 Bit */
17457 #else
17458  vuint32_t BUF02I:1; /* deprecated name - please avoid */
17459 #endif
17460 #ifndef USE_FIELD_ALIASES_FLEXCAN
17461  vuint32_t BUF1I:1; /* Buffer MB Interrupt 1 Bit */
17462 #else
17463  vuint32_t BUF01I:1; /* deprecated name - please avoid */
17464 #endif
17465 #ifndef USE_FIELD_ALIASES_FLEXCAN
17466  vuint32_t BUF0I:1; /* Buffer MB Interrupt 0 Bit */
17467 #else
17468  vuint32_t BUF00I:1; /* deprecated name - please avoid */
17469 #endif
17470  } B;
17471  } FLEXCAN_IFLAG1_32B_tag;
17472 
17473 
17474  /* Register layout for all registers MSG_CS... */
17475 
17476  typedef union { /* Message Buffer Control and Status */
17477  vuint32_t R;
17478  struct {
17479  vuint32_t:4;
17480  vuint32_t CODE:4; /* Message Buffer Code */
17481  vuint32_t:1;
17482  vuint32_t SRR:1; /* Substitute Remote Request */
17483  vuint32_t IDE:1; /* ID Extended Bit */
17484  vuint32_t RTR:1; /* Remote Transmission Request */
17485  vuint32_t LENGTH:4; /* Length of Data in Bytes */
17486  vuint32_t TIMESTAMP:16; /* Free-Running Counter Time Stamp */
17487  } B;
17488  } FLEXCAN_MSG_CS_32B_tag;
17489 
17490 
17491  /* Register layout for all registers MSG_ID... */
17492 
17493  typedef union { /* Message Buffer Identifier Field */
17494  vuint32_t R;
17495  struct {
17496  vuint32_t PRIO:3; /* Local Priority */
17497  vuint32_t STD_ID:11;
17498  vuint32_t EXT_ID:18;
17499  } B;
17500  } FLEXCAN_MSG_ID_32B_tag;
17501 
17502 
17503  /* Register layout for all registers MSG_BYTE0_3... */
17504 
17505  typedef union { /* Message Buffer Data Register */
17506  vuint32_t R;
17507  vuint8_t BYTE[4]; /* individual bytes can be accessed */
17508  vuint32_t WORD; /* individual words can be accessed */
17509  } FLEXCAN_MSG_DATA_32B_tag;
17510 
17511  typedef union {
17512  vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */
17513  vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */
17514  vuint32_t W[2]; /* Data buffer in words (32 bits) */
17515  vuint32_t R[2]; /* Data buffer in words (32 bits) */
17516  } FLEXCAN_MSG_DATA2_32B_tag;
17517 
17518  /* Register layout for all registers MSG_BYTE4_7 matches xxx */
17519 
17520 
17521  /* Register layout for all registers RXIMR... */
17522 
17523  typedef union { /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */
17524  vuint32_t R;
17525  } FLEXCAN_RXIMR_32B_tag;
17526 
17527 
17528  typedef struct FLEXCAN_MB_struct_tag {
17529 
17530  union {
17531  /* Message Buffer Control and Status */
17532  FLEXCAN_MSG_CS_32B_tag MSG_CS; /* relative offset: 0x0000 */
17533  FLEXCAN_MSG_CS_32B_tag CS; /* deprecated - please avoid */
17534  };
17535  union {
17536  /* Message Buffer Identifier Field */
17537  FLEXCAN_MSG_ID_32B_tag MSG_ID; /* relative offset: 0x0004 */
17538  FLEXCAN_MSG_ID_32B_tag ID; /* deprecated - please avoid */
17539  };
17540  union { /* Message Buffer Data Register */
17541 
17542  struct {
17543  FLEXCAN_MSG_DATA_32B_tag MSG_BYTE0_3; /* relative offset: 0x0008 */
17544  /* Message Buffer Data Register */
17545  FLEXCAN_MSG_DATA_32B_tag MSG_BYTE4_7; /* relative offset: 0x000C */
17546  };
17547 
17548  FLEXCAN_MSG_DATA2_32B_tag DATA; /* relative offset: 0x000C */
17549 
17550  };
17551 
17552  } FLEXCAN_MB_tag;
17553 
17554 
17555  typedef struct FLEXCAN_struct_tag { /* start of FLEXCAN_tag */
17556  /* MCR - Module Configuration Register */
17557  FLEXCAN_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */
17558  union {
17559  /* CTRL - Control Register */
17560  FLEXCAN_CTRL_32B_tag CTRL; /* offset: 0x0004 size: 32 bit */
17561 
17562  FLEXCAN_CTRL_32B_tag CR; /* deprecated - please avoid */
17563 
17564  };
17565  /* TIMER - Free Running Timer */
17566  FLEXCAN_TIMER_32B_tag TIMER; /* offset: 0x0008 size: 32 bit */
17567  int8_t FLEXCAN_reserved_000C[4];
17568  /* RXGMASK - Rx Global Mask Register */
17569  FLEXCAN_RXGMASK_32B_tag RXGMASK; /* offset: 0x0010 size: 32 bit */
17570  /* RX14MASK - Rx 14 Mask Register */
17571  FLEXCAN_RX14MASK_32B_tag RX14MASK; /* offset: 0x0014 size: 32 bit */
17572  /* RX15MASK - Rx 15 Mask Register */
17573  FLEXCAN_RX15MASK_32B_tag RX15MASK; /* offset: 0x0018 size: 32 bit */
17574  /* ECR - Error Counter Register */
17575  FLEXCAN_ECR_32B_tag ECR; /* offset: 0x001C size: 32 bit */
17576  /* ESR - Error and Status Register */
17577  FLEXCAN_ESR_32B_tag ESR; /* offset: 0x0020 size: 32 bit */
17578  union {
17579  FLEXCAN_IMASK2_32B_tag IMRH; /* deprecated - please avoid */
17580 
17581  /* IMASK2 - Interrupt Masks 2 Register */
17582  FLEXCAN_IMASK2_32B_tag IMASK2; /* offset: 0x0024 size: 32 bit */
17583 
17584  };
17585  union {
17586  FLEXCAN_IMASK1_32B_tag IMRL; /* deprecated - please avoid */
17587 
17588  /* IMASK1 - Interrupt Masks 1 Register */
17589  FLEXCAN_IMASK1_32B_tag IMASK1; /* offset: 0x0028 size: 32 bit */
17590 
17591  };
17592  union {
17593  FLEXCAN_IFLAG2_32B_tag IFRH; /* deprecated - please avoid */
17594 
17595  /* IFLAG2 - Interrupt Flags 2 Register */
17596  FLEXCAN_IFLAG2_32B_tag IFLAG2; /* offset: 0x002C size: 32 bit */
17597 
17598  };
17599  union {
17600  FLEXCAN_IFLAG1_32B_tag IFRL; /* deprecated - please avoid */
17601 
17602  /* IFLAG1 - Interrupt Flags 1 Register */
17603  FLEXCAN_IFLAG1_32B_tag IFLAG1; /* offset: 0x0030 size: 32 bit */
17604 
17605  };
17606  int8_t FLEXCAN_reserved_0034_C[76];
17607  union {
17608  /* Register set MB */
17609  FLEXCAN_MB_tag MB[64]; /* offset: 0x0080 (0x0010 x 64) */
17610 
17611  /* Alias name for MB */
17612  FLEXCAN_MB_tag BUF[64]; /* deprecated - please avoid */
17613 
17614  struct {
17615  /* Message Buffer Control and Status */
17616  FLEXCAN_MSG_CS_32B_tag MSG0_CS; /* offset: 0x0080 size: 32 bit */
17617  /* Message Buffer Identifier Field */
17618  FLEXCAN_MSG_ID_32B_tag MSG0_ID; /* offset: 0x0084 size: 32 bit */
17619  /* Message Buffer Data Register */
17620  FLEXCAN_MSG_DATA_32B_tag MSG0_BYTE0_3; /* offset: 0x0088 size: 32 bit */
17621  /* Message Buffer Data Register */
17622  FLEXCAN_MSG_DATA_32B_tag MSG0_BYTE4_7; /* offset: 0x008C size: 32 bit */
17623  /* Message Buffer Control and Status */
17624  FLEXCAN_MSG_CS_32B_tag MSG1_CS; /* offset: 0x0090 size: 32 bit */
17625  /* Message Buffer Identifier Field */
17626  FLEXCAN_MSG_ID_32B_tag MSG1_ID; /* offset: 0x0094 size: 32 bit */
17627  /* Message Buffer Data Register */
17628  FLEXCAN_MSG_DATA_32B_tag MSG1_BYTE0_3; /* offset: 0x0098 size: 32 bit */
17629  /* Message Buffer Data Register */
17630  FLEXCAN_MSG_DATA_32B_tag MSG1_BYTE4_7; /* offset: 0x009C size: 32 bit */
17631  /* Message Buffer Control and Status */
17632  FLEXCAN_MSG_CS_32B_tag MSG2_CS; /* offset: 0x00A0 size: 32 bit */
17633  /* Message Buffer Identifier Field */
17634  FLEXCAN_MSG_ID_32B_tag MSG2_ID; /* offset: 0x00A4 size: 32 bit */
17635  /* Message Buffer Data Register */
17636  FLEXCAN_MSG_DATA_32B_tag MSG2_BYTE0_3; /* offset: 0x00A8 size: 32 bit */
17637  /* Message Buffer Data Register */
17638  FLEXCAN_MSG_DATA_32B_tag MSG2_BYTE4_7; /* offset: 0x00AC size: 32 bit */
17639  /* Message Buffer Control and Status */
17640  FLEXCAN_MSG_CS_32B_tag MSG3_CS; /* offset: 0x00B0 size: 32 bit */
17641  /* Message Buffer Identifier Field */
17642  FLEXCAN_MSG_ID_32B_tag MSG3_ID; /* offset: 0x00B4 size: 32 bit */
17643  /* Message Buffer Data Register */
17644  FLEXCAN_MSG_DATA_32B_tag MSG3_BYTE0_3; /* offset: 0x00B8 size: 32 bit */
17645  /* Message Buffer Data Register */
17646  FLEXCAN_MSG_DATA_32B_tag MSG3_BYTE4_7; /* offset: 0x00BC size: 32 bit */
17647  /* Message Buffer Control and Status */
17648  FLEXCAN_MSG_CS_32B_tag MSG4_CS; /* offset: 0x00C0 size: 32 bit */
17649  /* Message Buffer Identifier Field */
17650  FLEXCAN_MSG_ID_32B_tag MSG4_ID; /* offset: 0x00C4 size: 32 bit */
17651  /* Message Buffer Data Register */
17652  FLEXCAN_MSG_DATA_32B_tag MSG4_BYTE0_3; /* offset: 0x00C8 size: 32 bit */
17653  /* Message Buffer Data Register */
17654  FLEXCAN_MSG_DATA_32B_tag MSG4_BYTE4_7; /* offset: 0x00CC size: 32 bit */
17655  /* Message Buffer Control and Status */
17656  FLEXCAN_MSG_CS_32B_tag MSG5_CS; /* offset: 0x00D0 size: 32 bit */
17657  /* Message Buffer Identifier Field */
17658  FLEXCAN_MSG_ID_32B_tag MSG5_ID; /* offset: 0x00D4 size: 32 bit */
17659  /* Message Buffer Data Register */
17660  FLEXCAN_MSG_DATA_32B_tag MSG5_BYTE0_3; /* offset: 0x00D8 size: 32 bit */
17661  /* Message Buffer Data Register */
17662  FLEXCAN_MSG_DATA_32B_tag MSG5_BYTE4_7; /* offset: 0x00DC size: 32 bit */
17663  /* Message Buffer Control and Status */
17664  FLEXCAN_MSG_CS_32B_tag MSG6_CS; /* offset: 0x00E0 size: 32 bit */
17665  /* Message Buffer Identifier Field */
17666  FLEXCAN_MSG_ID_32B_tag MSG6_ID; /* offset: 0x00E4 size: 32 bit */
17667  /* Message Buffer Data Register */
17668  FLEXCAN_MSG_DATA_32B_tag MSG6_BYTE0_3; /* offset: 0x00E8 size: 32 bit */
17669  /* Message Buffer Data Register */
17670  FLEXCAN_MSG_DATA_32B_tag MSG6_BYTE4_7; /* offset: 0x00EC size: 32 bit */
17671  /* Message Buffer Control and Status */
17672  FLEXCAN_MSG_CS_32B_tag MSG7_CS; /* offset: 0x00F0 size: 32 bit */
17673  /* Message Buffer Identifier Field */
17674  FLEXCAN_MSG_ID_32B_tag MSG7_ID; /* offset: 0x00F4 size: 32 bit */
17675  /* Message Buffer Data Register */
17676  FLEXCAN_MSG_DATA_32B_tag MSG7_BYTE0_3; /* offset: 0x00F8 size: 32 bit */
17677  /* Message Buffer Data Register */
17678  FLEXCAN_MSG_DATA_32B_tag MSG7_BYTE4_7; /* offset: 0x00FC size: 32 bit */
17679  /* Message Buffer Control and Status */
17680  FLEXCAN_MSG_CS_32B_tag MSG8_CS; /* offset: 0x0100 size: 32 bit */
17681  /* Message Buffer Identifier Field */
17682  FLEXCAN_MSG_ID_32B_tag MSG8_ID; /* offset: 0x0104 size: 32 bit */
17683  /* Message Buffer Data Register */
17684  FLEXCAN_MSG_DATA_32B_tag MSG8_BYTE0_3; /* offset: 0x0108 size: 32 bit */
17685  /* Message Buffer Data Register */
17686  FLEXCAN_MSG_DATA_32B_tag MSG8_BYTE4_7; /* offset: 0x010C size: 32 bit */
17687  /* Message Buffer Control and Status */
17688  FLEXCAN_MSG_CS_32B_tag MSG9_CS; /* offset: 0x0110 size: 32 bit */
17689  /* Message Buffer Identifier Field */
17690  FLEXCAN_MSG_ID_32B_tag MSG9_ID; /* offset: 0x0114 size: 32 bit */
17691  /* Message Buffer Data Register */
17692  FLEXCAN_MSG_DATA_32B_tag MSG9_BYTE0_3; /* offset: 0x0118 size: 32 bit */
17693  /* Message Buffer Data Register */
17694  FLEXCAN_MSG_DATA_32B_tag MSG9_BYTE4_7; /* offset: 0x011C size: 32 bit */
17695  /* Message Buffer Control and Status */
17696  FLEXCAN_MSG_CS_32B_tag MSG10_CS; /* offset: 0x0120 size: 32 bit */
17697  /* Message Buffer Identifier Field */
17698  FLEXCAN_MSG_ID_32B_tag MSG10_ID; /* offset: 0x0124 size: 32 bit */
17699  /* Message Buffer Data Register */
17700  FLEXCAN_MSG_DATA_32B_tag MSG10_BYTE0_3; /* offset: 0x0128 size: 32 bit */
17701  /* Message Buffer Data Register */
17702  FLEXCAN_MSG_DATA_32B_tag MSG10_BYTE4_7; /* offset: 0x012C size: 32 bit */
17703  /* Message Buffer Control and Status */
17704  FLEXCAN_MSG_CS_32B_tag MSG11_CS; /* offset: 0x0130 size: 32 bit */
17705  /* Message Buffer Identifier Field */
17706  FLEXCAN_MSG_ID_32B_tag MSG11_ID; /* offset: 0x0134 size: 32 bit */
17707  /* Message Buffer Data Register */
17708  FLEXCAN_MSG_DATA_32B_tag MSG11_BYTE0_3; /* offset: 0x0138 size: 32 bit */
17709  /* Message Buffer Data Register */
17710  FLEXCAN_MSG_DATA_32B_tag MSG11_BYTE4_7; /* offset: 0x013C size: 32 bit */
17711  /* Message Buffer Control and Status */
17712  FLEXCAN_MSG_CS_32B_tag MSG12_CS; /* offset: 0x0140 size: 32 bit */
17713  /* Message Buffer Identifier Field */
17714  FLEXCAN_MSG_ID_32B_tag MSG12_ID; /* offset: 0x0144 size: 32 bit */
17715  /* Message Buffer Data Register */
17716  FLEXCAN_MSG_DATA_32B_tag MSG12_BYTE0_3; /* offset: 0x0148 size: 32 bit */
17717  /* Message Buffer Data Register */
17718  FLEXCAN_MSG_DATA_32B_tag MSG12_BYTE4_7; /* offset: 0x014C size: 32 bit */
17719  /* Message Buffer Control and Status */
17720  FLEXCAN_MSG_CS_32B_tag MSG13_CS; /* offset: 0x0150 size: 32 bit */
17721  /* Message Buffer Identifier Field */
17722  FLEXCAN_MSG_ID_32B_tag MSG13_ID; /* offset: 0x0154 size: 32 bit */
17723  /* Message Buffer Data Register */
17724  FLEXCAN_MSG_DATA_32B_tag MSG13_BYTE0_3; /* offset: 0x0158 size: 32 bit */
17725  /* Message Buffer Data Register */
17726  FLEXCAN_MSG_DATA_32B_tag MSG13_BYTE4_7; /* offset: 0x015C size: 32 bit */
17727  /* Message Buffer Control and Status */
17728  FLEXCAN_MSG_CS_32B_tag MSG14_CS; /* offset: 0x0160 size: 32 bit */
17729  /* Message Buffer Identifier Field */
17730  FLEXCAN_MSG_ID_32B_tag MSG14_ID; /* offset: 0x0164 size: 32 bit */
17731  /* Message Buffer Data Register */
17732  FLEXCAN_MSG_DATA_32B_tag MSG14_BYTE0_3; /* offset: 0x0168 size: 32 bit */
17733  /* Message Buffer Data Register */
17734  FLEXCAN_MSG_DATA_32B_tag MSG14_BYTE4_7; /* offset: 0x016C size: 32 bit */
17735  /* Message Buffer Control and Status */
17736  FLEXCAN_MSG_CS_32B_tag MSG15_CS; /* offset: 0x0170 size: 32 bit */
17737  /* Message Buffer Identifier Field */
17738  FLEXCAN_MSG_ID_32B_tag MSG15_ID; /* offset: 0x0174 size: 32 bit */
17739  /* Message Buffer Data Register */
17740  FLEXCAN_MSG_DATA_32B_tag MSG15_BYTE0_3; /* offset: 0x0178 size: 32 bit */
17741  /* Message Buffer Data Register */
17742  FLEXCAN_MSG_DATA_32B_tag MSG15_BYTE4_7; /* offset: 0x017C size: 32 bit */
17743  /* Message Buffer Control and Status */
17744  FLEXCAN_MSG_CS_32B_tag MSG16_CS; /* offset: 0x0180 size: 32 bit */
17745  /* Message Buffer Identifier Field */
17746  FLEXCAN_MSG_ID_32B_tag MSG16_ID; /* offset: 0x0184 size: 32 bit */
17747  /* Message Buffer Data Register */
17748  FLEXCAN_MSG_DATA_32B_tag MSG16_BYTE0_3; /* offset: 0x0188 size: 32 bit */
17749  /* Message Buffer Data Register */
17750  FLEXCAN_MSG_DATA_32B_tag MSG16_BYTE4_7; /* offset: 0x018C size: 32 bit */
17751  /* Message Buffer Control and Status */
17752  FLEXCAN_MSG_CS_32B_tag MSG17_CS; /* offset: 0x0190 size: 32 bit */
17753  /* Message Buffer Identifier Field */
17754  FLEXCAN_MSG_ID_32B_tag MSG17_ID; /* offset: 0x0194 size: 32 bit */
17755  /* Message Buffer Data Register */
17756  FLEXCAN_MSG_DATA_32B_tag MSG17_BYTE0_3; /* offset: 0x0198 size: 32 bit */
17757  /* Message Buffer Data Register */
17758  FLEXCAN_MSG_DATA_32B_tag MSG17_BYTE4_7; /* offset: 0x019C size: 32 bit */
17759  /* Message Buffer Control and Status */
17760  FLEXCAN_MSG_CS_32B_tag MSG18_CS; /* offset: 0x01A0 size: 32 bit */
17761  /* Message Buffer Identifier Field */
17762  FLEXCAN_MSG_ID_32B_tag MSG18_ID; /* offset: 0x01A4 size: 32 bit */
17763  /* Message Buffer Data Register */
17764  FLEXCAN_MSG_DATA_32B_tag MSG18_BYTE0_3; /* offset: 0x01A8 size: 32 bit */
17765  /* Message Buffer Data Register */
17766  FLEXCAN_MSG_DATA_32B_tag MSG18_BYTE4_7; /* offset: 0x01AC size: 32 bit */
17767  /* Message Buffer Control and Status */
17768  FLEXCAN_MSG_CS_32B_tag MSG19_CS; /* offset: 0x01B0 size: 32 bit */
17769  /* Message Buffer Identifier Field */
17770  FLEXCAN_MSG_ID_32B_tag MSG19_ID; /* offset: 0x01B4 size: 32 bit */
17771  /* Message Buffer Data Register */
17772  FLEXCAN_MSG_DATA_32B_tag MSG19_BYTE0_3; /* offset: 0x01B8 size: 32 bit */
17773  /* Message Buffer Data Register */
17774  FLEXCAN_MSG_DATA_32B_tag MSG19_BYTE4_7; /* offset: 0x01BC size: 32 bit */
17775  /* Message Buffer Control and Status */
17776  FLEXCAN_MSG_CS_32B_tag MSG20_CS; /* offset: 0x01C0 size: 32 bit */
17777  /* Message Buffer Identifier Field */
17778  FLEXCAN_MSG_ID_32B_tag MSG20_ID; /* offset: 0x01C4 size: 32 bit */
17779  /* Message Buffer Data Register */
17780  FLEXCAN_MSG_DATA_32B_tag MSG20_BYTE0_3; /* offset: 0x01C8 size: 32 bit */
17781  /* Message Buffer Data Register */
17782  FLEXCAN_MSG_DATA_32B_tag MSG20_BYTE4_7; /* offset: 0x01CC size: 32 bit */
17783  /* Message Buffer Control and Status */
17784  FLEXCAN_MSG_CS_32B_tag MSG21_CS; /* offset: 0x01D0 size: 32 bit */
17785  /* Message Buffer Identifier Field */
17786  FLEXCAN_MSG_ID_32B_tag MSG21_ID; /* offset: 0x01D4 size: 32 bit */
17787  /* Message Buffer Data Register */
17788  FLEXCAN_MSG_DATA_32B_tag MSG21_BYTE0_3; /* offset: 0x01D8 size: 32 bit */
17789  /* Message Buffer Data Register */
17790  FLEXCAN_MSG_DATA_32B_tag MSG21_BYTE4_7; /* offset: 0x01DC size: 32 bit */
17791  /* Message Buffer Control and Status */
17792  FLEXCAN_MSG_CS_32B_tag MSG22_CS; /* offset: 0x01E0 size: 32 bit */
17793  /* Message Buffer Identifier Field */
17794  FLEXCAN_MSG_ID_32B_tag MSG22_ID; /* offset: 0x01E4 size: 32 bit */
17795  /* Message Buffer Data Register */
17796  FLEXCAN_MSG_DATA_32B_tag MSG22_BYTE0_3; /* offset: 0x01E8 size: 32 bit */
17797  /* Message Buffer Data Register */
17798  FLEXCAN_MSG_DATA_32B_tag MSG22_BYTE4_7; /* offset: 0x01EC size: 32 bit */
17799  /* Message Buffer Control and Status */
17800  FLEXCAN_MSG_CS_32B_tag MSG23_CS; /* offset: 0x01F0 size: 32 bit */
17801  /* Message Buffer Identifier Field */
17802  FLEXCAN_MSG_ID_32B_tag MSG23_ID; /* offset: 0x01F4 size: 32 bit */
17803  /* Message Buffer Data Register */
17804  FLEXCAN_MSG_DATA_32B_tag MSG23_BYTE0_3; /* offset: 0x01F8 size: 32 bit */
17805  /* Message Buffer Data Register */
17806  FLEXCAN_MSG_DATA_32B_tag MSG23_BYTE4_7; /* offset: 0x01FC size: 32 bit */
17807  /* Message Buffer Control and Status */
17808  FLEXCAN_MSG_CS_32B_tag MSG24_CS; /* offset: 0x0200 size: 32 bit */
17809  /* Message Buffer Identifier Field */
17810  FLEXCAN_MSG_ID_32B_tag MSG24_ID; /* offset: 0x0204 size: 32 bit */
17811  /* Message Buffer Data Register */
17812  FLEXCAN_MSG_DATA_32B_tag MSG24_BYTE0_3; /* offset: 0x0208 size: 32 bit */
17813  /* Message Buffer Data Register */
17814  FLEXCAN_MSG_DATA_32B_tag MSG24_BYTE4_7; /* offset: 0x020C size: 32 bit */
17815  /* Message Buffer Control and Status */
17816  FLEXCAN_MSG_CS_32B_tag MSG25_CS; /* offset: 0x0210 size: 32 bit */
17817  /* Message Buffer Identifier Field */
17818  FLEXCAN_MSG_ID_32B_tag MSG25_ID; /* offset: 0x0214 size: 32 bit */
17819  /* Message Buffer Data Register */
17820  FLEXCAN_MSG_DATA_32B_tag MSG25_BYTE0_3; /* offset: 0x0218 size: 32 bit */
17821  /* Message Buffer Data Register */
17822  FLEXCAN_MSG_DATA_32B_tag MSG25_BYTE4_7; /* offset: 0x021C size: 32 bit */
17823  /* Message Buffer Control and Status */
17824  FLEXCAN_MSG_CS_32B_tag MSG26_CS; /* offset: 0x0220 size: 32 bit */
17825  /* Message Buffer Identifier Field */
17826  FLEXCAN_MSG_ID_32B_tag MSG26_ID; /* offset: 0x0224 size: 32 bit */
17827  /* Message Buffer Data Register */
17828  FLEXCAN_MSG_DATA_32B_tag MSG26_BYTE0_3; /* offset: 0x0228 size: 32 bit */
17829  /* Message Buffer Data Register */
17830  FLEXCAN_MSG_DATA_32B_tag MSG26_BYTE4_7; /* offset: 0x022C size: 32 bit */
17831  /* Message Buffer Control and Status */
17832  FLEXCAN_MSG_CS_32B_tag MSG27_CS; /* offset: 0x0230 size: 32 bit */
17833  /* Message Buffer Identifier Field */
17834  FLEXCAN_MSG_ID_32B_tag MSG27_ID; /* offset: 0x0234 size: 32 bit */
17835  /* Message Buffer Data Register */
17836  FLEXCAN_MSG_DATA_32B_tag MSG27_BYTE0_3; /* offset: 0x0238 size: 32 bit */
17837  /* Message Buffer Data Register */
17838  FLEXCAN_MSG_DATA_32B_tag MSG27_BYTE4_7; /* offset: 0x023C size: 32 bit */
17839  /* Message Buffer Control and Status */
17840  FLEXCAN_MSG_CS_32B_tag MSG28_CS; /* offset: 0x0240 size: 32 bit */
17841  /* Message Buffer Identifier Field */
17842  FLEXCAN_MSG_ID_32B_tag MSG28_ID; /* offset: 0x0244 size: 32 bit */
17843  /* Message Buffer Data Register */
17844  FLEXCAN_MSG_DATA_32B_tag MSG28_BYTE0_3; /* offset: 0x0248 size: 32 bit */
17845  /* Message Buffer Data Register */
17846  FLEXCAN_MSG_DATA_32B_tag MSG28_BYTE4_7; /* offset: 0x024C size: 32 bit */
17847  /* Message Buffer Control and Status */
17848  FLEXCAN_MSG_CS_32B_tag MSG29_CS; /* offset: 0x0250 size: 32 bit */
17849  /* Message Buffer Identifier Field */
17850  FLEXCAN_MSG_ID_32B_tag MSG29_ID; /* offset: 0x0254 size: 32 bit */
17851  /* Message Buffer Data Register */
17852  FLEXCAN_MSG_DATA_32B_tag MSG29_BYTE0_3; /* offset: 0x0258 size: 32 bit */
17853  /* Message Buffer Data Register */
17854  FLEXCAN_MSG_DATA_32B_tag MSG29_BYTE4_7; /* offset: 0x025C size: 32 bit */
17855  /* Message Buffer Control and Status */
17856  FLEXCAN_MSG_CS_32B_tag MSG30_CS; /* offset: 0x0260 size: 32 bit */
17857  /* Message Buffer Identifier Field */
17858  FLEXCAN_MSG_ID_32B_tag MSG30_ID; /* offset: 0x0264 size: 32 bit */
17859  /* Message Buffer Data Register */
17860  FLEXCAN_MSG_DATA_32B_tag MSG30_BYTE0_3; /* offset: 0x0268 size: 32 bit */
17861  /* Message Buffer Data Register */
17862  FLEXCAN_MSG_DATA_32B_tag MSG30_BYTE4_7; /* offset: 0x026C size: 32 bit */
17863  /* Message Buffer Control and Status */
17864  FLEXCAN_MSG_CS_32B_tag MSG31_CS; /* offset: 0x0270 size: 32 bit */
17865  /* Message Buffer Identifier Field */
17866  FLEXCAN_MSG_ID_32B_tag MSG31_ID; /* offset: 0x0274 size: 32 bit */
17867  /* Message Buffer Data Register */
17868  FLEXCAN_MSG_DATA_32B_tag MSG31_BYTE0_3; /* offset: 0x0278 size: 32 bit */
17869  /* Message Buffer Data Register */
17870  FLEXCAN_MSG_DATA_32B_tag MSG31_BYTE4_7; /* offset: 0x027C size: 32 bit */
17871  /* Message Buffer Control and Status */
17872  FLEXCAN_MSG_CS_32B_tag MSG32_CS; /* offset: 0x0280 size: 32 bit */
17873  /* Message Buffer Identifier Field */
17874  FLEXCAN_MSG_ID_32B_tag MSG32_ID; /* offset: 0x0284 size: 32 bit */
17875  /* Message Buffer Data Register */
17876  FLEXCAN_MSG_DATA_32B_tag MSG32_BYTE0_3; /* offset: 0x0288 size: 32 bit */
17877  /* Message Buffer Data Register */
17878  FLEXCAN_MSG_DATA_32B_tag MSG32_BYTE4_7; /* offset: 0x028C size: 32 bit */
17879  /* Message Buffer Control and Status */
17880  FLEXCAN_MSG_CS_32B_tag MSG33_CS; /* offset: 0x0290 size: 32 bit */
17881  /* Message Buffer Identifier Field */
17882  FLEXCAN_MSG_ID_32B_tag MSG33_ID; /* offset: 0x0294 size: 32 bit */
17883  /* Message Buffer Data Register */
17884  FLEXCAN_MSG_DATA_32B_tag MSG33_BYTE0_3; /* offset: 0x0298 size: 32 bit */
17885  /* Message Buffer Data Register */
17886  FLEXCAN_MSG_DATA_32B_tag MSG33_BYTE4_7; /* offset: 0x029C size: 32 bit */
17887  /* Message Buffer Control and Status */
17888  FLEXCAN_MSG_CS_32B_tag MSG34_CS; /* offset: 0x02A0 size: 32 bit */
17889  /* Message Buffer Identifier Field */
17890  FLEXCAN_MSG_ID_32B_tag MSG34_ID; /* offset: 0x02A4 size: 32 bit */
17891  /* Message Buffer Data Register */
17892  FLEXCAN_MSG_DATA_32B_tag MSG34_BYTE0_3; /* offset: 0x02A8 size: 32 bit */
17893  /* Message Buffer Data Register */
17894  FLEXCAN_MSG_DATA_32B_tag MSG34_BYTE4_7; /* offset: 0x02AC size: 32 bit */
17895  /* Message Buffer Control and Status */
17896  FLEXCAN_MSG_CS_32B_tag MSG35_CS; /* offset: 0x02B0 size: 32 bit */
17897  /* Message Buffer Identifier Field */
17898  FLEXCAN_MSG_ID_32B_tag MSG35_ID; /* offset: 0x02B4 size: 32 bit */
17899  /* Message Buffer Data Register */
17900  FLEXCAN_MSG_DATA_32B_tag MSG35_BYTE0_3; /* offset: 0x02B8 size: 32 bit */
17901  /* Message Buffer Data Register */
17902  FLEXCAN_MSG_DATA_32B_tag MSG35_BYTE4_7; /* offset: 0x02BC size: 32 bit */
17903  /* Message Buffer Control and Status */
17904  FLEXCAN_MSG_CS_32B_tag MSG36_CS; /* offset: 0x02C0 size: 32 bit */
17905  /* Message Buffer Identifier Field */
17906  FLEXCAN_MSG_ID_32B_tag MSG36_ID; /* offset: 0x02C4 size: 32 bit */
17907  /* Message Buffer Data Register */
17908  FLEXCAN_MSG_DATA_32B_tag MSG36_BYTE0_3; /* offset: 0x02C8 size: 32 bit */
17909  /* Message Buffer Data Register */
17910  FLEXCAN_MSG_DATA_32B_tag MSG36_BYTE4_7; /* offset: 0x02CC size: 32 bit */
17911  /* Message Buffer Control and Status */
17912  FLEXCAN_MSG_CS_32B_tag MSG37_CS; /* offset: 0x02D0 size: 32 bit */
17913  /* Message Buffer Identifier Field */
17914  FLEXCAN_MSG_ID_32B_tag MSG37_ID; /* offset: 0x02D4 size: 32 bit */
17915  /* Message Buffer Data Register */
17916  FLEXCAN_MSG_DATA_32B_tag MSG37_BYTE0_3; /* offset: 0x02D8 size: 32 bit */
17917  /* Message Buffer Data Register */
17918  FLEXCAN_MSG_DATA_32B_tag MSG37_BYTE4_7; /* offset: 0x02DC size: 32 bit */
17919  /* Message Buffer Control and Status */
17920  FLEXCAN_MSG_CS_32B_tag MSG38_CS; /* offset: 0x02E0 size: 32 bit */
17921  /* Message Buffer Identifier Field */
17922  FLEXCAN_MSG_ID_32B_tag MSG38_ID; /* offset: 0x02E4 size: 32 bit */
17923  /* Message Buffer Data Register */
17924  FLEXCAN_MSG_DATA_32B_tag MSG38_BYTE0_3; /* offset: 0x02E8 size: 32 bit */
17925  /* Message Buffer Data Register */
17926  FLEXCAN_MSG_DATA_32B_tag MSG38_BYTE4_7; /* offset: 0x02EC size: 32 bit */
17927  /* Message Buffer Control and Status */
17928  FLEXCAN_MSG_CS_32B_tag MSG39_CS; /* offset: 0x02F0 size: 32 bit */
17929  /* Message Buffer Identifier Field */
17930  FLEXCAN_MSG_ID_32B_tag MSG39_ID; /* offset: 0x02F4 size: 32 bit */
17931  /* Message Buffer Data Register */
17932  FLEXCAN_MSG_DATA_32B_tag MSG39_BYTE0_3; /* offset: 0x02F8 size: 32 bit */
17933  /* Message Buffer Data Register */
17934  FLEXCAN_MSG_DATA_32B_tag MSG39_BYTE4_7; /* offset: 0x02FC size: 32 bit */
17935  /* Message Buffer Control and Status */
17936  FLEXCAN_MSG_CS_32B_tag MSG40_CS; /* offset: 0x0300 size: 32 bit */
17937  /* Message Buffer Identifier Field */
17938  FLEXCAN_MSG_ID_32B_tag MSG40_ID; /* offset: 0x0304 size: 32 bit */
17939  /* Message Buffer Data Register */
17940  FLEXCAN_MSG_DATA_32B_tag MSG40_BYTE0_3; /* offset: 0x0308 size: 32 bit */
17941  /* Message Buffer Data Register */
17942  FLEXCAN_MSG_DATA_32B_tag MSG40_BYTE4_7; /* offset: 0x030C size: 32 bit */
17943  /* Message Buffer Control and Status */
17944  FLEXCAN_MSG_CS_32B_tag MSG41_CS; /* offset: 0x0310 size: 32 bit */
17945  /* Message Buffer Identifier Field */
17946  FLEXCAN_MSG_ID_32B_tag MSG41_ID; /* offset: 0x0314 size: 32 bit */
17947  /* Message Buffer Data Register */
17948  FLEXCAN_MSG_DATA_32B_tag MSG41_BYTE0_3; /* offset: 0x0318 size: 32 bit */
17949  /* Message Buffer Data Register */
17950  FLEXCAN_MSG_DATA_32B_tag MSG41_BYTE4_7; /* offset: 0x031C size: 32 bit */
17951  /* Message Buffer Control and Status */
17952  FLEXCAN_MSG_CS_32B_tag MSG42_CS; /* offset: 0x0320 size: 32 bit */
17953  /* Message Buffer Identifier Field */
17954  FLEXCAN_MSG_ID_32B_tag MSG42_ID; /* offset: 0x0324 size: 32 bit */
17955  /* Message Buffer Data Register */
17956  FLEXCAN_MSG_DATA_32B_tag MSG42_BYTE0_3; /* offset: 0x0328 size: 32 bit */
17957  /* Message Buffer Data Register */
17958  FLEXCAN_MSG_DATA_32B_tag MSG42_BYTE4_7; /* offset: 0x032C size: 32 bit */
17959  /* Message Buffer Control and Status */
17960  FLEXCAN_MSG_CS_32B_tag MSG43_CS; /* offset: 0x0330 size: 32 bit */
17961  /* Message Buffer Identifier Field */
17962  FLEXCAN_MSG_ID_32B_tag MSG43_ID; /* offset: 0x0334 size: 32 bit */
17963  /* Message Buffer Data Register */
17964  FLEXCAN_MSG_DATA_32B_tag MSG43_BYTE0_3; /* offset: 0x0338 size: 32 bit */
17965  /* Message Buffer Data Register */
17966  FLEXCAN_MSG_DATA_32B_tag MSG43_BYTE4_7; /* offset: 0x033C size: 32 bit */
17967  /* Message Buffer Control and Status */
17968  FLEXCAN_MSG_CS_32B_tag MSG44_CS; /* offset: 0x0340 size: 32 bit */
17969  /* Message Buffer Identifier Field */
17970  FLEXCAN_MSG_ID_32B_tag MSG44_ID; /* offset: 0x0344 size: 32 bit */
17971  /* Message Buffer Data Register */
17972  FLEXCAN_MSG_DATA_32B_tag MSG44_BYTE0_3; /* offset: 0x0348 size: 32 bit */
17973  /* Message Buffer Data Register */
17974  FLEXCAN_MSG_DATA_32B_tag MSG44_BYTE4_7; /* offset: 0x034C size: 32 bit */
17975  /* Message Buffer Control and Status */
17976  FLEXCAN_MSG_CS_32B_tag MSG45_CS; /* offset: 0x0350 size: 32 bit */
17977  /* Message Buffer Identifier Field */
17978  FLEXCAN_MSG_ID_32B_tag MSG45_ID; /* offset: 0x0354 size: 32 bit */
17979  /* Message Buffer Data Register */
17980  FLEXCAN_MSG_DATA_32B_tag MSG45_BYTE0_3; /* offset: 0x0358 size: 32 bit */
17981  /* Message Buffer Data Register */
17982  FLEXCAN_MSG_DATA_32B_tag MSG45_BYTE4_7; /* offset: 0x035C size: 32 bit */
17983  /* Message Buffer Control and Status */
17984  FLEXCAN_MSG_CS_32B_tag MSG46_CS; /* offset: 0x0360 size: 32 bit */
17985  /* Message Buffer Identifier Field */
17986  FLEXCAN_MSG_ID_32B_tag MSG46_ID; /* offset: 0x0364 size: 32 bit */
17987  /* Message Buffer Data Register */
17988  FLEXCAN_MSG_DATA_32B_tag MSG46_BYTE0_3; /* offset: 0x0368 size: 32 bit */
17989  /* Message Buffer Data Register */
17990  FLEXCAN_MSG_DATA_32B_tag MSG46_BYTE4_7; /* offset: 0x036C size: 32 bit */
17991  /* Message Buffer Control and Status */
17992  FLEXCAN_MSG_CS_32B_tag MSG47_CS; /* offset: 0x0370 size: 32 bit */
17993  /* Message Buffer Identifier Field */
17994  FLEXCAN_MSG_ID_32B_tag MSG47_ID; /* offset: 0x0374 size: 32 bit */
17995  /* Message Buffer Data Register */
17996  FLEXCAN_MSG_DATA_32B_tag MSG47_BYTE0_3; /* offset: 0x0378 size: 32 bit */
17997  /* Message Buffer Data Register */
17998  FLEXCAN_MSG_DATA_32B_tag MSG47_BYTE4_7; /* offset: 0x037C size: 32 bit */
17999  /* Message Buffer Control and Status */
18000  FLEXCAN_MSG_CS_32B_tag MSG48_CS; /* offset: 0x0380 size: 32 bit */
18001  /* Message Buffer Identifier Field */
18002  FLEXCAN_MSG_ID_32B_tag MSG48_ID; /* offset: 0x0384 size: 32 bit */
18003  /* Message Buffer Data Register */
18004  FLEXCAN_MSG_DATA_32B_tag MSG48_BYTE0_3; /* offset: 0x0388 size: 32 bit */
18005  /* Message Buffer Data Register */
18006  FLEXCAN_MSG_DATA_32B_tag MSG48_BYTE4_7; /* offset: 0x038C size: 32 bit */
18007  /* Message Buffer Control and Status */
18008  FLEXCAN_MSG_CS_32B_tag MSG49_CS; /* offset: 0x0390 size: 32 bit */
18009  /* Message Buffer Identifier Field */
18010  FLEXCAN_MSG_ID_32B_tag MSG49_ID; /* offset: 0x0394 size: 32 bit */
18011  /* Message Buffer Data Register */
18012  FLEXCAN_MSG_DATA_32B_tag MSG49_BYTE0_3; /* offset: 0x0398 size: 32 bit */
18013  /* Message Buffer Data Register */
18014  FLEXCAN_MSG_DATA_32B_tag MSG49_BYTE4_7; /* offset: 0x039C size: 32 bit */
18015  /* Message Buffer Control and Status */
18016  FLEXCAN_MSG_CS_32B_tag MSG50_CS; /* offset: 0x03A0 size: 32 bit */
18017  /* Message Buffer Identifier Field */
18018  FLEXCAN_MSG_ID_32B_tag MSG50_ID; /* offset: 0x03A4 size: 32 bit */
18019  /* Message Buffer Data Register */
18020  FLEXCAN_MSG_DATA_32B_tag MSG50_BYTE0_3; /* offset: 0x03A8 size: 32 bit */
18021  /* Message Buffer Data Register */
18022  FLEXCAN_MSG_DATA_32B_tag MSG50_BYTE4_7; /* offset: 0x03AC size: 32 bit */
18023  /* Message Buffer Control and Status */
18024  FLEXCAN_MSG_CS_32B_tag MSG51_CS; /* offset: 0x03B0 size: 32 bit */
18025  /* Message Buffer Identifier Field */
18026  FLEXCAN_MSG_ID_32B_tag MSG51_ID; /* offset: 0x03B4 size: 32 bit */
18027  /* Message Buffer Data Register */
18028  FLEXCAN_MSG_DATA_32B_tag MSG51_BYTE0_3; /* offset: 0x03B8 size: 32 bit */
18029  /* Message Buffer Data Register */
18030  FLEXCAN_MSG_DATA_32B_tag MSG51_BYTE4_7; /* offset: 0x03BC size: 32 bit */
18031  /* Message Buffer Control and Status */
18032  FLEXCAN_MSG_CS_32B_tag MSG52_CS; /* offset: 0x03C0 size: 32 bit */
18033  /* Message Buffer Identifier Field */
18034  FLEXCAN_MSG_ID_32B_tag MSG52_ID; /* offset: 0x03C4 size: 32 bit */
18035  /* Message Buffer Data Register */
18036  FLEXCAN_MSG_DATA_32B_tag MSG52_BYTE0_3; /* offset: 0x03C8 size: 32 bit */
18037  /* Message Buffer Data Register */
18038  FLEXCAN_MSG_DATA_32B_tag MSG52_BYTE4_7; /* offset: 0x03CC size: 32 bit */
18039  /* Message Buffer Control and Status */
18040  FLEXCAN_MSG_CS_32B_tag MSG53_CS; /* offset: 0x03D0 size: 32 bit */
18041  /* Message Buffer Identifier Field */
18042  FLEXCAN_MSG_ID_32B_tag MSG53_ID; /* offset: 0x03D4 size: 32 bit */
18043  /* Message Buffer Data Register */
18044  FLEXCAN_MSG_DATA_32B_tag MSG53_BYTE0_3; /* offset: 0x03D8 size: 32 bit */
18045  /* Message Buffer Data Register */
18046  FLEXCAN_MSG_DATA_32B_tag MSG53_BYTE4_7; /* offset: 0x03DC size: 32 bit */
18047  /* Message Buffer Control and Status */
18048  FLEXCAN_MSG_CS_32B_tag MSG54_CS; /* offset: 0x03E0 size: 32 bit */
18049  /* Message Buffer Identifier Field */
18050  FLEXCAN_MSG_ID_32B_tag MSG54_ID; /* offset: 0x03E4 size: 32 bit */
18051  /* Message Buffer Data Register */
18052  FLEXCAN_MSG_DATA_32B_tag MSG54_BYTE0_3; /* offset: 0x03E8 size: 32 bit */
18053  /* Message Buffer Data Register */
18054  FLEXCAN_MSG_DATA_32B_tag MSG54_BYTE4_7; /* offset: 0x03EC size: 32 bit */
18055  /* Message Buffer Control and Status */
18056  FLEXCAN_MSG_CS_32B_tag MSG55_CS; /* offset: 0x03F0 size: 32 bit */
18057  /* Message Buffer Identifier Field */
18058  FLEXCAN_MSG_ID_32B_tag MSG55_ID; /* offset: 0x03F4 size: 32 bit */
18059  /* Message Buffer Data Register */
18060  FLEXCAN_MSG_DATA_32B_tag MSG55_BYTE0_3; /* offset: 0x03F8 size: 32 bit */
18061  /* Message Buffer Data Register */
18062  FLEXCAN_MSG_DATA_32B_tag MSG55_BYTE4_7; /* offset: 0x03FC size: 32 bit */
18063  /* Message Buffer Control and Status */
18064  FLEXCAN_MSG_CS_32B_tag MSG56_CS; /* offset: 0x0400 size: 32 bit */
18065  /* Message Buffer Identifier Field */
18066  FLEXCAN_MSG_ID_32B_tag MSG56_ID; /* offset: 0x0404 size: 32 bit */
18067  /* Message Buffer Data Register */
18068  FLEXCAN_MSG_DATA_32B_tag MSG56_BYTE0_3; /* offset: 0x0408 size: 32 bit */
18069  /* Message Buffer Data Register */
18070  FLEXCAN_MSG_DATA_32B_tag MSG56_BYTE4_7; /* offset: 0x040C size: 32 bit */
18071  /* Message Buffer Control and Status */
18072  FLEXCAN_MSG_CS_32B_tag MSG57_CS; /* offset: 0x0410 size: 32 bit */
18073  /* Message Buffer Identifier Field */
18074  FLEXCAN_MSG_ID_32B_tag MSG57_ID; /* offset: 0x0414 size: 32 bit */
18075  /* Message Buffer Data Register */
18076  FLEXCAN_MSG_DATA_32B_tag MSG57_BYTE0_3; /* offset: 0x0418 size: 32 bit */
18077  /* Message Buffer Data Register */
18078  FLEXCAN_MSG_DATA_32B_tag MSG57_BYTE4_7; /* offset: 0x041C size: 32 bit */
18079  /* Message Buffer Control and Status */
18080  FLEXCAN_MSG_CS_32B_tag MSG58_CS; /* offset: 0x0420 size: 32 bit */
18081  /* Message Buffer Identifier Field */
18082  FLEXCAN_MSG_ID_32B_tag MSG58_ID; /* offset: 0x0424 size: 32 bit */
18083  /* Message Buffer Data Register */
18084  FLEXCAN_MSG_DATA_32B_tag MSG58_BYTE0_3; /* offset: 0x0428 size: 32 bit */
18085  /* Message Buffer Data Register */
18086  FLEXCAN_MSG_DATA_32B_tag MSG58_BYTE4_7; /* offset: 0x042C size: 32 bit */
18087  /* Message Buffer Control and Status */
18088  FLEXCAN_MSG_CS_32B_tag MSG59_CS; /* offset: 0x0430 size: 32 bit */
18089  /* Message Buffer Identifier Field */
18090  FLEXCAN_MSG_ID_32B_tag MSG59_ID; /* offset: 0x0434 size: 32 bit */
18091  /* Message Buffer Data Register */
18092  FLEXCAN_MSG_DATA_32B_tag MSG59_BYTE0_3; /* offset: 0x0438 size: 32 bit */
18093  /* Message Buffer Data Register */
18094  FLEXCAN_MSG_DATA_32B_tag MSG59_BYTE4_7; /* offset: 0x043C size: 32 bit */
18095  /* Message Buffer Control and Status */
18096  FLEXCAN_MSG_CS_32B_tag MSG60_CS; /* offset: 0x0440 size: 32 bit */
18097  /* Message Buffer Identifier Field */
18098  FLEXCAN_MSG_ID_32B_tag MSG60_ID; /* offset: 0x0444 size: 32 bit */
18099  /* Message Buffer Data Register */
18100  FLEXCAN_MSG_DATA_32B_tag MSG60_BYTE0_3; /* offset: 0x0448 size: 32 bit */
18101  /* Message Buffer Data Register */
18102  FLEXCAN_MSG_DATA_32B_tag MSG60_BYTE4_7; /* offset: 0x044C size: 32 bit */
18103  /* Message Buffer Control and Status */
18104  FLEXCAN_MSG_CS_32B_tag MSG61_CS; /* offset: 0x0450 size: 32 bit */
18105  /* Message Buffer Identifier Field */
18106  FLEXCAN_MSG_ID_32B_tag MSG61_ID; /* offset: 0x0454 size: 32 bit */
18107  /* Message Buffer Data Register */
18108  FLEXCAN_MSG_DATA_32B_tag MSG61_BYTE0_3; /* offset: 0x0458 size: 32 bit */
18109  /* Message Buffer Data Register */
18110  FLEXCAN_MSG_DATA_32B_tag MSG61_BYTE4_7; /* offset: 0x045C size: 32 bit */
18111  /* Message Buffer Control and Status */
18112  FLEXCAN_MSG_CS_32B_tag MSG62_CS; /* offset: 0x0460 size: 32 bit */
18113  /* Message Buffer Identifier Field */
18114  FLEXCAN_MSG_ID_32B_tag MSG62_ID; /* offset: 0x0464 size: 32 bit */
18115  /* Message Buffer Data Register */
18116  FLEXCAN_MSG_DATA_32B_tag MSG62_BYTE0_3; /* offset: 0x0468 size: 32 bit */
18117  /* Message Buffer Data Register */
18118  FLEXCAN_MSG_DATA_32B_tag MSG62_BYTE4_7; /* offset: 0x046C size: 32 bit */
18119  /* Message Buffer Control and Status */
18120  FLEXCAN_MSG_CS_32B_tag MSG63_CS; /* offset: 0x0470 size: 32 bit */
18121  /* Message Buffer Identifier Field */
18122  FLEXCAN_MSG_ID_32B_tag MSG63_ID; /* offset: 0x0474 size: 32 bit */
18123  /* Message Buffer Data Register */
18124  FLEXCAN_MSG_DATA_32B_tag MSG63_BYTE0_3; /* offset: 0x0478 size: 32 bit */
18125  /* Message Buffer Data Register */
18126  FLEXCAN_MSG_DATA_32B_tag MSG63_BYTE4_7; /* offset: 0x047C size: 32 bit */
18127  };
18128 
18129  };
18130  int8_t FLEXCAN_reserved_0480_C[1024];
18131  union {
18132  /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */
18133  FLEXCAN_RXIMR_32B_tag RXIMR[64]; /* offset: 0x0880 (0x0004 x 64) */
18134 
18135  struct {
18136  /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */
18137  FLEXCAN_RXIMR_32B_tag RXIMR0; /* offset: 0x0880 size: 32 bit */
18138  FLEXCAN_RXIMR_32B_tag RXIMR1; /* offset: 0x0884 size: 32 bit */
18139  FLEXCAN_RXIMR_32B_tag RXIMR2; /* offset: 0x0888 size: 32 bit */
18140  FLEXCAN_RXIMR_32B_tag RXIMR3; /* offset: 0x088C size: 32 bit */
18141  FLEXCAN_RXIMR_32B_tag RXIMR4; /* offset: 0x0890 size: 32 bit */
18142  FLEXCAN_RXIMR_32B_tag RXIMR5; /* offset: 0x0894 size: 32 bit */
18143  FLEXCAN_RXIMR_32B_tag RXIMR6; /* offset: 0x0898 size: 32 bit */
18144  FLEXCAN_RXIMR_32B_tag RXIMR7; /* offset: 0x089C size: 32 bit */
18145  FLEXCAN_RXIMR_32B_tag RXIMR8; /* offset: 0x08A0 size: 32 bit */
18146  FLEXCAN_RXIMR_32B_tag RXIMR9; /* offset: 0x08A4 size: 32 bit */
18147  FLEXCAN_RXIMR_32B_tag RXIMR10; /* offset: 0x08A8 size: 32 bit */
18148  FLEXCAN_RXIMR_32B_tag RXIMR11; /* offset: 0x08AC size: 32 bit */
18149  FLEXCAN_RXIMR_32B_tag RXIMR12; /* offset: 0x08B0 size: 32 bit */
18150  FLEXCAN_RXIMR_32B_tag RXIMR13; /* offset: 0x08B4 size: 32 bit */
18151  FLEXCAN_RXIMR_32B_tag RXIMR14; /* offset: 0x08B8 size: 32 bit */
18152  FLEXCAN_RXIMR_32B_tag RXIMR15; /* offset: 0x08BC size: 32 bit */
18153  FLEXCAN_RXIMR_32B_tag RXIMR16; /* offset: 0x08C0 size: 32 bit */
18154  FLEXCAN_RXIMR_32B_tag RXIMR17; /* offset: 0x08C4 size: 32 bit */
18155  FLEXCAN_RXIMR_32B_tag RXIMR18; /* offset: 0x08C8 size: 32 bit */
18156  FLEXCAN_RXIMR_32B_tag RXIMR19; /* offset: 0x08CC size: 32 bit */
18157  FLEXCAN_RXIMR_32B_tag RXIMR20; /* offset: 0x08D0 size: 32 bit */
18158  FLEXCAN_RXIMR_32B_tag RXIMR21; /* offset: 0x08D4 size: 32 bit */
18159  FLEXCAN_RXIMR_32B_tag RXIMR22; /* offset: 0x08D8 size: 32 bit */
18160  FLEXCAN_RXIMR_32B_tag RXIMR23; /* offset: 0x08DC size: 32 bit */
18161  FLEXCAN_RXIMR_32B_tag RXIMR24; /* offset: 0x08E0 size: 32 bit */
18162  FLEXCAN_RXIMR_32B_tag RXIMR25; /* offset: 0x08E4 size: 32 bit */
18163  FLEXCAN_RXIMR_32B_tag RXIMR26; /* offset: 0x08E8 size: 32 bit */
18164  FLEXCAN_RXIMR_32B_tag RXIMR27; /* offset: 0x08EC size: 32 bit */
18165  FLEXCAN_RXIMR_32B_tag RXIMR28; /* offset: 0x08F0 size: 32 bit */
18166  FLEXCAN_RXIMR_32B_tag RXIMR29; /* offset: 0x08F4 size: 32 bit */
18167  FLEXCAN_RXIMR_32B_tag RXIMR30; /* offset: 0x08F8 size: 32 bit */
18168  FLEXCAN_RXIMR_32B_tag RXIMR31; /* offset: 0x08FC size: 32 bit */
18169  FLEXCAN_RXIMR_32B_tag RXIMR32; /* offset: 0x0900 size: 32 bit */
18170  FLEXCAN_RXIMR_32B_tag RXIMR33; /* offset: 0x0904 size: 32 bit */
18171  FLEXCAN_RXIMR_32B_tag RXIMR34; /* offset: 0x0908 size: 32 bit */
18172  FLEXCAN_RXIMR_32B_tag RXIMR35; /* offset: 0x090C size: 32 bit */
18173  FLEXCAN_RXIMR_32B_tag RXIMR36; /* offset: 0x0910 size: 32 bit */
18174  FLEXCAN_RXIMR_32B_tag RXIMR37; /* offset: 0x0914 size: 32 bit */
18175  FLEXCAN_RXIMR_32B_tag RXIMR38; /* offset: 0x0918 size: 32 bit */
18176  FLEXCAN_RXIMR_32B_tag RXIMR39; /* offset: 0x091C size: 32 bit */
18177  FLEXCAN_RXIMR_32B_tag RXIMR40; /* offset: 0x0920 size: 32 bit */
18178  FLEXCAN_RXIMR_32B_tag RXIMR41; /* offset: 0x0924 size: 32 bit */
18179  FLEXCAN_RXIMR_32B_tag RXIMR42; /* offset: 0x0928 size: 32 bit */
18180  FLEXCAN_RXIMR_32B_tag RXIMR43; /* offset: 0x092C size: 32 bit */
18181  FLEXCAN_RXIMR_32B_tag RXIMR44; /* offset: 0x0930 size: 32 bit */
18182  FLEXCAN_RXIMR_32B_tag RXIMR45; /* offset: 0x0934 size: 32 bit */
18183  FLEXCAN_RXIMR_32B_tag RXIMR46; /* offset: 0x0938 size: 32 bit */
18184  FLEXCAN_RXIMR_32B_tag RXIMR47; /* offset: 0x093C size: 32 bit */
18185  FLEXCAN_RXIMR_32B_tag RXIMR48; /* offset: 0x0940 size: 32 bit */
18186  FLEXCAN_RXIMR_32B_tag RXIMR49; /* offset: 0x0944 size: 32 bit */
18187  FLEXCAN_RXIMR_32B_tag RXIMR50; /* offset: 0x0948 size: 32 bit */
18188  FLEXCAN_RXIMR_32B_tag RXIMR51; /* offset: 0x094C size: 32 bit */
18189  FLEXCAN_RXIMR_32B_tag RXIMR52; /* offset: 0x0950 size: 32 bit */
18190  FLEXCAN_RXIMR_32B_tag RXIMR53; /* offset: 0x0954 size: 32 bit */
18191  FLEXCAN_RXIMR_32B_tag RXIMR54; /* offset: 0x0958 size: 32 bit */
18192  FLEXCAN_RXIMR_32B_tag RXIMR55; /* offset: 0x095C size: 32 bit */
18193  FLEXCAN_RXIMR_32B_tag RXIMR56; /* offset: 0x0960 size: 32 bit */
18194  FLEXCAN_RXIMR_32B_tag RXIMR57; /* offset: 0x0964 size: 32 bit */
18195  FLEXCAN_RXIMR_32B_tag RXIMR58; /* offset: 0x0968 size: 32 bit */
18196  FLEXCAN_RXIMR_32B_tag RXIMR59; /* offset: 0x096C size: 32 bit */
18197  FLEXCAN_RXIMR_32B_tag RXIMR60; /* offset: 0x0970 size: 32 bit */
18198  FLEXCAN_RXIMR_32B_tag RXIMR61; /* offset: 0x0974 size: 32 bit */
18199  FLEXCAN_RXIMR_32B_tag RXIMR62; /* offset: 0x0978 size: 32 bit */
18200  FLEXCAN_RXIMR_32B_tag RXIMR63; /* offset: 0x097C size: 32 bit */
18201  };
18202 
18203  };
18204  } FLEXCAN_tag;
18205 
18206 
18207 #define FLEXCAN_A (*(volatile FLEXCAN_tag *) 0xFFFC0000UL)
18208 #define FLEXCAN_B (*(volatile FLEXCAN_tag *) 0xFFFC4000UL)
18209 
18210 
18211 
18212 /****************************************************************/
18213 /* */
18214 /* Module: DMA_CH_MUX */
18215 /* */
18216 /****************************************************************/
18217 
18218 
18219  /* Register layout for all registers CHCONFIG... */
18220 
18221  typedef union { /* CHCONFIG[0-15] - Channel Configuration Registers */
18222  vuint8_t R;
18223  struct {
18224  vuint8_t ENBL:1; /* DMA Channel Enable */
18225  vuint8_t TRIG:1; /* DMA Channel Trigger Enable */
18226  vuint8_t SOURCE:6; /* DMA Channel Source */
18227  } B;
18228  } DMA_CH_MUX_CHCONFIG_8B_tag;
18229 
18230 
18231 
18232  typedef struct DMA_CH_MUX_struct_tag { /* start of DMA_CH_MUX_tag */
18233  union {
18234  /* CHCONFIG[0-15] - Channel Configuration Registers */
18235  DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG[16]; /* offset: 0x0000 (0x0001 x 16) */
18236 
18237  struct {
18238  /* CHCONFIG[0-15] - Channel Configuration Registers */
18239  DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG0; /* offset: 0x0000 size: 8 bit */
18240  DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG1; /* offset: 0x0001 size: 8 bit */
18241  DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG2; /* offset: 0x0002 size: 8 bit */
18242  DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG3; /* offset: 0x0003 size: 8 bit */
18243  DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG4; /* offset: 0x0004 size: 8 bit */
18244  DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG5; /* offset: 0x0005 size: 8 bit */
18245  DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG6; /* offset: 0x0006 size: 8 bit */
18246  DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG7; /* offset: 0x0007 size: 8 bit */
18247  DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG8; /* offset: 0x0008 size: 8 bit */
18248  DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG9; /* offset: 0x0009 size: 8 bit */
18249  DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG10; /* offset: 0x000A size: 8 bit */
18250  DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG11; /* offset: 0x000B size: 8 bit */
18251  DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG12; /* offset: 0x000C size: 8 bit */
18252  DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG13; /* offset: 0x000D size: 8 bit */
18253  DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG14; /* offset: 0x000E size: 8 bit */
18254  DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG15; /* offset: 0x000F size: 8 bit */
18255  };
18256 
18257  };
18258  } DMA_CH_MUX_tag;
18259 
18260 
18261 #define DMA_CH_MUX (*(volatile DMA_CH_MUX_tag *) 0xFFFDC000UL)
18262 
18263 
18264 
18265 /****************************************************************/
18266 /* */
18267 /* Module: FR */
18268 /* */
18269 /****************************************************************/
18270 
18271  typedef union { /* Module Version Number */
18272  vuint16_t R;
18273  struct {
18274  vuint16_t CHIVER:8; /* VERSION NUMBER OF CHI */
18275  vuint16_t PEVER:8; /* VERSION NUMBER OF PE */
18276  } B;
18277  } FR_MVR_16B_tag;
18278 
18279  typedef union { /* Module Configuration Register */
18280  vuint16_t R;
18281  struct {
18282  vuint16_t MEN:1; /* Module Enable */
18283  vuint16_t SBFF:1; /* System Bus Failure Freeze */
18284 #ifndef USE_FIELD_ALIASES_FR
18285  vuint16_t SCM:1; /* single channel device mode */
18286 #else
18287  vuint16_t SCMD:1; /* deprecated name - please avoid */
18288 #endif
18289  vuint16_t CHB:1; /* Channel B enable */
18290  vuint16_t CHA:1; /* channel A enable */
18291  vuint16_t SFFE:1; /* Sync. frame filter Enable */
18292  vuint16_t ECCE:1; /* ECC Functionlity Enable */
18293  vuint16_t TMODER:1; /* Functional Test mode */
18294  vuint16_t FUM:1; /* FIFO Update Mode */
18295  vuint16_t FAM:1; /* FIFO Address Mode */
18296  vuint16_t:1;
18297  vuint16_t CLKSEL:1; /* Protocol Engine clock source select */
18298 #ifndef USE_FIELD_ALIASES_FR
18299  vuint16_t BITRATE:3; /* Bus bit rate */
18300 #else
18301  vuint16_t PRESCALE:3; /* deprecated name - please avoid */
18302 #endif
18303  vuint16_t:1;
18304  } B;
18305  } FR_MCR_16B_tag;
18306 
18307  typedef union { /* SYSTEM MEMORY BASE ADD HIGH REG */
18308  vuint16_t R;
18309  struct {
18310  vuint16_t SMBA_31_16:16; /* SYS_MEM_BASE_ADDR[31:16] */
18311  } B;
18312  } FR_SYMBADHR_16B_tag;
18313 
18314  typedef union { /* SYSTEM MEMORY BASE ADD LOW REG */
18315  vuint16_t R;
18316  struct {
18317  vuint16_t SMBA_15_4:12; /* SYS_MEM_BASE_ADDR[15:4] */
18318  vuint16_t:4;
18319  } B;
18320  } FR_SYMBADLR_16B_tag;
18321 
18322  typedef union { /* STROBE SIGNAL CONTROL REGISTER */
18323  vuint16_t R;
18324  struct {
18325  vuint16_t WMD:1; /* DEFINES WRITE MODE OF REG */
18326  vuint16_t:3;
18327  vuint16_t SEL:4; /* STROBE SIGNSL SELECT */
18328  vuint16_t:3;
18329  vuint16_t ENB:1; /* STROBE SIGNAL ENABLE */
18330  vuint16_t:2;
18331  vuint16_t STBPSEL:2; /* STROBE PORT SELECT */
18332  } B;
18333  } FR_STBSCR_16B_tag;
18334 
18335  typedef union { /* MESSAGE BUFFER DATA SIZE REGISTER */
18336  vuint16_t R;
18337  struct {
18338  vuint16_t:1;
18339  vuint16_t MBSEG2DS:7; /* MESSAGE BUFFER SEGMENT 2 DATA SIZE */
18340  vuint16_t:1;
18341  vuint16_t MBSEG1DS:7; /* MESSAGE BUFFER SEGMENT 1 DATA SIZE */
18342  } B;
18343  } FR_MBDSR_16B_tag;
18344 
18345  typedef union { /* MESS. BUFFER SEG. SIZE & UTILISATION REG */
18346  vuint16_t R;
18347  struct {
18348  vuint16_t:2;
18349  vuint16_t LAST_MB_SEG1:6; /* LAST MESS BUFFER IN SEG 1 */
18350  vuint16_t:2;
18351  vuint16_t LAST_MB_UTIL:6; /* LAST MESSAGE BUFFER UTILISED */
18352  } B;
18353  } FR_MBSSUTR_16B_tag;
18354 
18355  typedef union { /* PE DRAM ACCESS REGISTER */
18356  vuint16_t R;
18357  struct {
18358  vuint16_t INST:4; /* PE DRAM ACCESS INSTRUCTION */
18359  vuint16_t ADDR:11; /* PE DRAM ACCESS ADDRESS */
18360  vuint16_t DAD:1; /* PE DRAM ACCESS DONE */
18361  } B;
18362  } FR_PEDRAR_16B_tag;
18363 
18364  typedef union { /* PE DRAM DATA REGISTER */
18365  vuint16_t R;
18366  struct {
18367  vuint16_t DATA:16; /* DATA TO BE READ OR WRITTEN */
18368  } B;
18369  } FR_PEDRDR_16B_tag;
18370 
18371  typedef union { /* PROTOCOL OPERATION CONTROL REG */
18372  vuint16_t R;
18373  struct {
18374  vuint16_t WME:1; /* WRITE MODE EXTERNAL CORRECTION */
18375  vuint16_t:3;
18376  vuint16_t EOC_AP:2; /* EXTERNAL OFFSET CORRECTION APPLICATION */
18377  vuint16_t ERC_AP:2; /* EXTERNAL RATE CORRECTION APPLICATION */
18378  vuint16_t BSY:1; /* PROTOCOL CONTROL COMMAND WRITE BUSY */
18379  vuint16_t:3;
18380  vuint16_t POCCMD:4; /* PROTOCOL CONTROL COMMAND */
18381  } B;
18382  } FR_POCR_16B_tag;
18383 
18384  typedef union { /* GLOBAL INTERRUPT FLAG & ENABLE REG */
18385  vuint16_t R;
18386  struct {
18387  vuint16_t MIF:1; /* MODULE INTERRUPT FLAG */
18388  vuint16_t PRIF:1; /* PROTOCOL INTERRUPT FLAG */
18389  vuint16_t CHIF:1; /* CHI INTERRUPT FLAG */
18390 #ifndef USE_FIELD_ALIASES_FR
18391  vuint16_t WUPIF:1; /* WAKEUP INTERRUPT FLAG */
18392 #else
18393  vuint16_t WKUPIF:1; /* deprecated name - please avoid */
18394 #endif
18395 #ifndef USE_FIELD_ALIASES_FR
18396  vuint16_t FAFBIF:1; /* RECEIVE FIFO CHANNEL B ALMOST FULL INTERRUPT FLAG */
18397 #else
18398  vuint16_t FNEBIF:1; /* deprecated name - please avoid */
18399 #endif
18400 #ifndef USE_FIELD_ALIASES_FR
18401  vuint16_t FAFAIF:1; /* RECEIVE FIFO CHANNEL A ALMOST FULL INTERRUPT FLAG */
18402 #else
18403  vuint16_t FNEAIF:1; /* deprecated name - please avoid */
18404 #endif
18405  vuint16_t RBIF:1; /* RECEIVE MESSAGE BUFFER INTERRUPT FLAG */
18406  vuint16_t TBIF:1; /* TRANSMIT BUFFER INTERRUPT FLAG */
18407  vuint16_t MIE:1; /* MODULE INTERRUPT ENABLE */
18408  vuint16_t PRIE:1; /* PROTOCOL INTERRUPT ENABLE */
18409  vuint16_t CHIE:1; /* CHI INTERRUPT ENABLE */
18410 #ifndef USE_FIELD_ALIASES_FR
18411  vuint16_t WUPIE:1; /* WAKEUP INTERRUPT ENABLE */
18412 #else
18413  vuint16_t WKUPIE:1; /* deprecated name - please avoid */
18414 #endif
18415  vuint16_t FNEBIE:1; /* RECEIVE FIFO CHANNEL B NOT EMPTY INTERRUPT ENABLE */
18416  vuint16_t FNEAIE:1; /* RECEIVE FIFO CHANNEL A NOT EMPTY INTERRUPT ENABLE */
18417  vuint16_t RBIE:1; /* RECEIVE BUFFER INTERRUPT ENABLE */
18418  vuint16_t TBIE:1; /* TRANSMIT BUFFER INTERRUPT ENABLE */
18419  } B;
18420  } FR_GIFER_16B_tag;
18421 
18422  typedef union { /* PROTOCOL INTERRUPT FLAG REGISTER 0 */
18423  vuint16_t R;
18424  struct {
18425 #ifndef USE_FIELD_ALIASES_FR
18426  vuint16_t FATL_IF:1; /* FATAL PROTOCOL ERROR INTERRUPT FLAG */
18427 #else
18428  vuint16_t FATLIF:1; /* deprecated name - please avoid */
18429 #endif
18430 #ifndef USE_FIELD_ALIASES_FR
18431  vuint16_t INTL_IF:1; /* INTERNAL PROTOCOL ERROR INTERRUPT FLAG */
18432 #else
18433  vuint16_t INTLIF:1; /* deprecated name - please avoid */
18434 #endif
18435 #ifndef USE_FIELD_ALIASES_FR
18436  vuint16_t ILCF_IF:1; /* ILLEGAL PROTOCOL CONFIGURATION INTERRUPT FLAG */
18437 #else
18438  vuint16_t ILCFIF:1; /* deprecated name - please avoid */
18439 #endif
18440 #ifndef USE_FIELD_ALIASES_FR
18441  vuint16_t CSA_IF:1; /* COLDSTART ABORT INTERRUPT FLAG */
18442 #else
18443  vuint16_t CSAIF:1; /* deprecated name - please avoid */
18444 #endif
18445 #ifndef USE_FIELD_ALIASES_FR
18446  vuint16_t MRC_IF:1; /* MISSING RATE CORRECTION INTERRUPT FLAG */
18447 #else
18448  vuint16_t MRCIF:1; /* deprecated name - please avoid */
18449 #endif
18450 #ifndef USE_FIELD_ALIASES_FR
18451  vuint16_t MOC_IF:1; /* MISSING OFFSET CORRECTION INTERRUPT FLAG */
18452 #else
18453  vuint16_t MOCIF:1; /* deprecated name - please avoid */
18454 #endif
18455 #ifndef USE_FIELD_ALIASES_FR
18456  vuint16_t CCL_IF:1; /* CLOCK CORRECTION LIMIT REACHED INTERRUPT FLAG */
18457 #else
18458  vuint16_t CCLIF:1; /* deprecated name - please avoid */
18459 #endif
18460 #ifndef USE_FIELD_ALIASES_FR
18461  vuint16_t MXS_IF:1; /* MAX SYNC FRAMES DETECTED INTERRUPT FLAG */
18462 #else
18463  vuint16_t MXSIF:1; /* deprecated name - please avoid */
18464 #endif
18465 #ifndef USE_FIELD_ALIASES_FR
18466  vuint16_t MTX_IF:1; /* MEDIA ACCESS TEST SYMBOL RECEIVED INTERRUPT FLAG */
18467 #else
18468  vuint16_t MTXIF:1; /* deprecated name - please avoid */
18469 #endif
18470 #ifndef USE_FIELD_ALIASES_FR
18471  vuint16_t LTXB_IF:1; /* pLATESTTX VIOLATION ON CHANNEL B INTERRUPT FLAG */
18472 #else
18473  vuint16_t LTXBIF:1; /* deprecated name - please avoid */
18474 #endif
18475 #ifndef USE_FIELD_ALIASES_FR
18476  vuint16_t LTXA_IF:1; /* pLATESTTX VIOLATION ON CHANNEL A INTERRUPT FLAG */
18477 #else
18478  vuint16_t LTXAIF:1; /* deprecated name - please avoid */
18479 #endif
18480 #ifndef USE_FIELD_ALIASES_FR
18481  vuint16_t TBVB_IF:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL B INTERRUPT FLAG */
18482 #else
18483  vuint16_t TBVBIF:1; /* deprecated name - please avoid */
18484 #endif
18485 #ifndef USE_FIELD_ALIASES_FR
18486  vuint16_t TBVA_IF:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL A INTERRUPT FLAG */
18487 #else
18488  vuint16_t TBVAIF:1; /* deprecated name - please avoid */
18489 #endif
18490 #ifndef USE_FIELD_ALIASES_FR
18491  vuint16_t TI2_IF:1; /* TIMER 2 EXPIRED INTERRUPT FLAG */
18492 #else
18493  vuint16_t TI2IF:1; /* deprecated name - please avoid */
18494 #endif
18495 #ifndef USE_FIELD_ALIASES_FR
18496  vuint16_t TI1_IF:1; /* TIMER 1 EXPIRED INTERRUPT FLAG */
18497 #else
18498  vuint16_t TI1IF:1; /* deprecated name - please avoid */
18499 #endif
18500 #ifndef USE_FIELD_ALIASES_FR
18501  vuint16_t CYS_IF:1; /* CYCLE START INTERRUPT FLAG */
18502 #else
18503  vuint16_t CYSIF:1; /* deprecated name - please avoid */
18504 #endif
18505  } B;
18506  } FR_PIFR0_16B_tag;
18507 
18508  typedef union { /* PROTOCOL INTERRUPT FLAG REGISTER 1 */
18509  vuint16_t R;
18510  struct {
18511 #ifndef USE_FIELD_ALIASES_FR
18512  vuint16_t EMC_IF:1; /* ERROR MODE CHANGED INTERRUPT FLAG */
18513 #else
18514  vuint16_t EMCIF:1; /* deprecated name - please avoid */
18515 #endif
18516 #ifndef USE_FIELD_ALIASES_FR
18517  vuint16_t IPC_IF:1; /* ILLEGAL PROTOCOL CONTROL COMMAND INTERRUPT FLAG */
18518 #else
18519  vuint16_t IPCIF:1; /* deprecated name - please avoid */
18520 #endif
18521 #ifndef USE_FIELD_ALIASES_FR
18522  vuint16_t PECF_IF:1; /* PROTOCOL ENGINE COMMUNICATION FAILURE INTERRUPT FLAG */
18523 #else
18524  vuint16_t PECFIF:1; /* deprecated name - please avoid */
18525 #endif
18526 #ifndef USE_FIELD_ALIASES_FR
18527  vuint16_t PSC_IF:1; /* PROTOCOL STATE CHANGED INTERRUPT FLAG */
18528 #else
18529  vuint16_t PSCIF:1; /* deprecated name - please avoid */
18530 #endif
18531 #ifndef USE_FIELD_ALIASES_FR
18532  vuint16_t SSI3_IF:1; /* SLOT STATUS COUNTER 3 INCREMENTED INTERRUPT FLAG */
18533 #else
18534  vuint16_t SSI3IF:1; /* deprecated name - please avoid */
18535 #endif
18536 #ifndef USE_FIELD_ALIASES_FR
18537  vuint16_t SSI2_IF:1; /* SLOT STATUS COUNTER 2 INCREMENTED INTERRUPT FLAG */
18538 #else
18539  vuint16_t SSI2IF:1; /* deprecated name - please avoid */
18540 #endif
18541 #ifndef USE_FIELD_ALIASES_FR
18542  vuint16_t SSI1_IF:1; /* SLOT STATUS COUNTER 1 INCREMENTED INTERRUPT FLAG */
18543 #else
18544  vuint16_t SSI1IF:1; /* deprecated name - please avoid */
18545 #endif
18546 #ifndef USE_FIELD_ALIASES_FR
18547  vuint16_t SSI0_IF:1; /* SLOT STATUS COUNTER 0 INCREMENTED INTERRUPT FLAG */
18548 #else
18549  vuint16_t SSI0IF:1; /* deprecated name - please avoid */
18550 #endif
18551  vuint16_t:2;
18552 #ifndef USE_FIELD_ALIASES_FR
18553  vuint16_t EVT_IF:1; /* EVEN CYCLE TABLE WRITTEN INTERRUPT FLAG */
18554 #else
18555  vuint16_t EVTIF:1; /* deprecated name - please avoid */
18556 #endif
18557 #ifndef USE_FIELD_ALIASES_FR
18558  vuint16_t ODT_IF:1; /* ODD CYCLE TABLE WRITTEN INTERRUPT FLAG */
18559 #else
18560  vuint16_t ODTIF:1; /* deprecated name - please avoid */
18561 #endif
18562  vuint16_t:4;
18563  } B;
18564  } FR_PIFR1_16B_tag;
18565 
18566  typedef union { /* PROTOCOL INTERRUPT ENABLE REGISTER 0 */
18567  vuint16_t R;
18568  struct {
18569 #ifndef USE_FIELD_ALIASES_FR
18570  vuint16_t FATL_IE:1; /* FATAL PROTOCOL ERROR INTERRUPT ENABLE */
18571 #else
18572  vuint16_t FATLIE:1; /* deprecated name - please avoid */
18573 #endif
18574 #ifndef USE_FIELD_ALIASES_FR
18575  vuint16_t INTL_IE:1; /* INTERNAL PROTOCOL ERROR INTERRUPT ENABLE */
18576 #else
18577  vuint16_t INTLIE:1; /* deprecated name - please avoid */
18578 #endif
18579 #ifndef USE_FIELD_ALIASES_FR
18580  vuint16_t ILCF_IE:1; /* ILLEGAL PROTOCOL CONFIGURATION INTERRUPT ENABLE */
18581 #else
18582  vuint16_t ILCFIE:1; /* deprecated name - please avoid */
18583 #endif
18584 #ifndef USE_FIELD_ALIASES_FR
18585  vuint16_t CSA_IE:1; /* COLDSTART ABORT INTERRUPT ENABLE */
18586 #else
18587  vuint16_t CSAIE:1; /* deprecated name - please avoid */
18588 #endif
18589 #ifndef USE_FIELD_ALIASES_FR
18590  vuint16_t MRC_IE:1; /* MISSING RATE CORRECTION INTERRUPT ENABLE */
18591 #else
18592  vuint16_t MRCIE:1; /* deprecated name - please avoid */
18593 #endif
18594 #ifndef USE_FIELD_ALIASES_FR
18595  vuint16_t MOC_IE:1; /* MISSING OFFSET CORRECTION INTERRUPT ENABLE */
18596 #else
18597  vuint16_t MOCIE:1; /* deprecated name - please avoid */
18598 #endif
18599 #ifndef USE_FIELD_ALIASES_FR
18600  vuint16_t CCL_IE:1; /* CLOCK CORRECTION LIMIT REACHED */
18601 #else
18602  vuint16_t CCLIE:1; /* deprecated name - please avoid */
18603 #endif
18604 #ifndef USE_FIELD_ALIASES_FR
18605  vuint16_t MXS_IE:1; /* MAX SYNC FRAMES DETECTED INTERRUPT ENABLE */
18606 #else
18607  vuint16_t MXSIE:1; /* deprecated name - please avoid */
18608 #endif
18609 #ifndef USE_FIELD_ALIASES_FR
18610  vuint16_t MTX_IE:1; /* MEDIA ACCESS TEST SYMBOL RECEIVED INTERRUPT ENABLE */
18611 #else
18612  vuint16_t MTXIE:1; /* deprecated name - please avoid */
18613 #endif
18614 #ifndef USE_FIELD_ALIASES_FR
18615  vuint16_t LTXB_IE:1; /* pLATESTTX VIOLATION ON CHANNEL B INTERRUPT ENABLE */
18616 #else
18617  vuint16_t LTXBIE:1; /* deprecated name - please avoid */
18618 #endif
18619 #ifndef USE_FIELD_ALIASES_FR
18620  vuint16_t LTXA_IE:1; /* pLATESTTX VIOLATION ON CHANNEL A INTERRUPT ENABLE */
18621 #else
18622  vuint16_t LTXAIE:1; /* deprecated name - please avoid */
18623 #endif
18624 #ifndef USE_FIELD_ALIASES_FR
18625  vuint16_t TBVB_IE:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL B INTERRUPT ENABLE */
18626 #else
18627  vuint16_t TBVBIE:1; /* deprecated name - please avoid */
18628 #endif
18629 #ifndef USE_FIELD_ALIASES_FR
18630  vuint16_t TBVA_IE:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL A INTERRUPT ENABLE */
18631 #else
18632  vuint16_t TBVAIE:1; /* deprecated name - please avoid */
18633 #endif
18634 #ifndef USE_FIELD_ALIASES_FR
18635  vuint16_t TI2_IE:1; /* TIMER 2 EXPIRED INTERRUPT ENABLE */
18636 #else
18637  vuint16_t TI2IE:1; /* deprecated name - please avoid */
18638 #endif
18639 #ifndef USE_FIELD_ALIASES_FR
18640  vuint16_t TI1_IE:1; /* TIMER 1 EXPIRED INTERRUPT ENABLE */
18641 #else
18642  vuint16_t TI1IE:1; /* deprecated name - please avoid */
18643 #endif
18644 #ifndef USE_FIELD_ALIASES_FR
18645  vuint16_t CYS_IE:1; /* CYCLE START INTERRUPT ENABLE */
18646 #else
18647  vuint16_t CYSIE:1; /* deprecated name - please avoid */
18648 #endif
18649  } B;
18650  } FR_PIER0_16B_tag;
18651 
18652  typedef union { /* PROTOCOL INTERRUPT ENABLE REGISTER 1 */
18653  vuint16_t R;
18654  struct {
18655 #ifndef USE_FIELD_ALIASES_FR
18656  vuint16_t EMC_IE:1; /* ERROR MODE CHANGED INTERRUPT Enable */
18657 #else
18658  vuint16_t EMCIE:1; /* deprecated name - please avoid */
18659 #endif
18660 #ifndef USE_FIELD_ALIASES_FR
18661  vuint16_t IPC_IE:1; /* ILLEGAL PROTOCOL CONTROL COMMAND INTERRUPT Enable */
18662 #else
18663  vuint16_t IPCIE:1; /* deprecated name - please avoid */
18664 #endif
18665 #ifndef USE_FIELD_ALIASES_FR
18666  vuint16_t PECF_IE:1; /* PROTOCOL ENGINE COMMUNICATION FAILURE INTERRUPT Enable */
18667 #else
18668  vuint16_t PECFIE:1; /* deprecated name - please avoid */
18669 #endif
18670 #ifndef USE_FIELD_ALIASES_FR
18671  vuint16_t PSC_IE:1; /* PROTOCOL STATE CHANGED INTERRUPT Enable */
18672 #else
18673  vuint16_t PSCIE:1; /* deprecated name - please avoid */
18674 #endif
18675 #ifndef USE_FIELD_ALIASES_FR
18676  vuint16_t SSI_3_0_IE:4; /* SLOT STATUS COUNTER INCREMENTED INTERRUPT Enable */
18677 #else
18678  vuint16_t SSI3IE:1;
18679  vuint16_t SSI2IE:1;
18680  vuint16_t SSI1IE:1;
18681  vuint16_t SSI0IE:1;
18682 #endif
18683 
18684  vuint16_t:2;
18685 #ifndef USE_FIELD_ALIASES_FR
18686  vuint16_t EVT_IE:1; /* EVEN CYCLE TABLE WRITTEN INTERRUPT Enable */
18687 #else
18688  vuint16_t EVTIE:1; /* deprecated name - please avoid */
18689 #endif
18690 #ifndef USE_FIELD_ALIASES_FR
18691  vuint16_t ODT_IE:1; /* ODD CYCLE TABLE WRITTEN INTERRUPT Enable */
18692 #else
18693  vuint16_t ODTIE:1; /* deprecated name - please avoid */
18694 #endif
18695  vuint16_t:4;
18696  } B;
18697  } FR_PIER1_16B_tag;
18698 
18699  typedef union { /* CHI ERROR FLAG REGISTER */
18700  vuint16_t R;
18701  struct {
18702 #ifndef USE_FIELD_ALIASES_FR
18703  vuint16_t FRLB_EF:1; /* FRAME LOST CHANNEL B ERROR FLAG */
18704 #else
18705  vuint16_t FRLBEF:1; /* deprecated name - please avoid */
18706 #endif
18707 #ifndef USE_FIELD_ALIASES_FR
18708  vuint16_t FRLA_EF:1; /* FRAME LOST CHANNEL A ERROR FLAG */
18709 #else
18710  vuint16_t FRLAEF:1; /* deprecated name - please avoid */
18711 #endif
18712 #ifndef USE_FIELD_ALIASES_FR
18713  vuint16_t PCMI_EF:1; /* PROTOCOL COMMAND IGNORED ERROR FLAG */
18714 #else
18715  vuint16_t PCMIEF:1; /* deprecated name - please avoid */
18716 #endif
18717 #ifndef USE_FIELD_ALIASES_FR
18718  vuint16_t FOVB_EF:1; /* RECEIVE FIFO OVERRUN CHANNEL B ERROR FLAG */
18719 #else
18720  vuint16_t FOVBEF:1; /* deprecated name - please avoid */
18721 #endif
18722 #ifndef USE_FIELD_ALIASES_FR
18723  vuint16_t FOVA_EF:1; /* RECEIVE FIFO OVERRUN CHANNEL A ERROR FLAG */
18724 #else
18725  vuint16_t FOVAEF:1; /* deprecated name - please avoid */
18726 #endif
18727 #ifndef USE_FIELD_ALIASES_FR
18728  vuint16_t MBS_EF:1; /* MESSAGE BUFFER SEARCH ERROR FLAG */
18729 #else
18730  vuint16_t MSBEF:1; /* deprecated name - please avoid */
18731 #endif
18732 #ifndef USE_FIELD_ALIASES_FR
18733  vuint16_t MBU_EF:1; /* MESSAGE BUFFER UTILIZATION ERROR FLAG */
18734 #else
18735  vuint16_t MBUEF:1; /* deprecated name - please avoid */
18736 #endif
18737 #ifndef USE_FIELD_ALIASES_FR
18738  vuint16_t LCK_EF:1; /* LOCK ERROR FLAG */
18739 #else
18740  vuint16_t LCKEF:1; /* deprecated name - please avoid */
18741 #endif
18742 #ifndef USE_FIELD_ALIASES_FR
18743  vuint16_t DBL_EF:1; /* DOUBLE TRANSMIT MESSAGE BUFFER LOCK ERROR FLAG */
18744 #else
18745  vuint16_t DBLEF:1; /* deprecated name - please avoid */
18746 #endif
18747 #ifndef USE_FIELD_ALIASES_FR
18748  vuint16_t SBCF_EF:1; /* SYSTEM BUS COMMUNICATION FAILURE ERROR FLAG */
18749 #else
18750  vuint16_t SBCFEF:1; /* deprecated name - please avoid */
18751 #endif
18752 #ifndef USE_FIELD_ALIASES_FR
18753  vuint16_t FID_EF:1; /* FRAME ID ERROR FLAG */
18754 #else
18755  vuint16_t FIDEF:1; /* deprecated name - please avoid */
18756 #endif
18757 #ifndef USE_FIELD_ALIASES_FR
18758  vuint16_t DPL_EF:1; /* DYNAMIC PAYLOAD LENGTH ERROR FLAG */
18759 #else
18760  vuint16_t DPLEF:1; /* deprecated name - please avoid */
18761 #endif
18762 #ifndef USE_FIELD_ALIASES_FR
18763  vuint16_t SPL_EF:1; /* STATIC PAYLOAD LENGTH ERROR FLAG */
18764 #else
18765  vuint16_t SPLEF:1; /* deprecated name - please avoid */
18766 #endif
18767 #ifndef USE_FIELD_ALIASES_FR
18768  vuint16_t NML_EF:1; /* NETWORK MANAGEMENT LENGTH ERROR FLAG */
18769 #else
18770  vuint16_t NMLEF:1; /* deprecated name - please avoid */
18771 #endif
18772 #ifndef USE_FIELD_ALIASES_FR
18773  vuint16_t NMF_EF:1; /* NETWORK MANAGEMENT FRAME ERROR FLAG */
18774 #else
18775  vuint16_t NMFEF:1; /* deprecated name - please avoid */
18776 #endif
18777 #ifndef USE_FIELD_ALIASES_FR
18778  vuint16_t ILSA_EF:1; /* ILLEGAL SYSTEM MEMORY ACCESS ERROR FLAG */
18779 #else
18780  vuint16_t ILSAEF:1; /* deprecated name - please avoid */
18781 #endif
18782  } B;
18783  } FR_CHIERFR_16B_tag;
18784 
18785  typedef union { /* Message Buffer Interrupt Vector Register */
18786  vuint16_t R;
18787  struct {
18788  vuint16_t:2;
18789  vuint16_t TBIVEC:6; /* Transmit Buffer Interrupt Vector */
18790  vuint16_t:2;
18791  vuint16_t RBIVEC:6; /* Receive Buffer Interrupt Vector */
18792  } B;
18793  } FR_MBIVEC_16B_tag;
18794 
18795  typedef union { /* Channel A Status Error Counter Register */
18796  vuint16_t R;
18797  struct {
18798  vuint16_t STATUS_ERR_CNT:16; /* Channel Status Error Counter */
18799  } B;
18800  } FR_CASERCR_16B_tag;
18801 
18802  typedef union { /* Channel B Status Error Counter Register */
18803  vuint16_t R;
18804  struct {
18805  vuint16_t STATUS_ERR_CNT:16; /* Channel Status Error Counter */
18806  } B;
18807  } FR_CBSERCR_16B_tag;
18808 
18809  typedef union { /* Protocol Status Register 0 */
18810  vuint16_t R;
18811  struct {
18812  vuint16_t ERRMODE:2; /* Error Mode */
18813  vuint16_t SLOTMODE:2; /* Slot Mode */
18814  vuint16_t:1;
18815  vuint16_t PROTSTATE:3; /* Protocol State */
18816 #ifndef USE_FIELD_ALIASES_FR
18817  vuint16_t STARTUPSTATE:4; /* Startup State */
18818 #else
18819  vuint16_t SUBSTATE:4; /* deprecated name - please avoid */
18820 #endif
18821  vuint16_t WAKEUPSTATE:4; /* Wakeup Status */
18822  } B;
18823  } FR_PSR0_16B_tag;
18824 
18825  typedef union { /* Protocol Status Register 1 */
18826  vuint16_t R;
18827  struct {
18828  vuint16_t CSAA:1; /* Coldstart Attempt Aborted Flag */
18829 #ifndef USE_FIELD_ALIASES_FR
18830  vuint16_t CSP:1; /* Leading Coldstart Path */
18831 #else
18832  vuint16_t SCP:1; /* deprecated name - please avoid */
18833 #endif
18834  vuint16_t:1;
18835  vuint16_t REMCSAT:5; /* Remaining Coldstart Attempts */
18836  vuint16_t CPN:1; /* Leading Coldstart Path Noise */
18837  vuint16_t HHR:1; /* Host Halt Request Pending */
18838  vuint16_t FRZ:1; /* Freeze Occurred */
18839  vuint16_t APTAC:5; /* Allow Passive to Active Counter */
18840  } B;
18841  } FR_PSR1_16B_tag;
18842 
18843  typedef union { /* Protocol Status Register 2 */
18844  vuint16_t R;
18845  struct {
18846  vuint16_t NBVB:1; /* NIT Boundary Violation on Channel B */
18847  vuint16_t NSEB:1; /* NIT Syntax Error on Channel B */
18848  vuint16_t STCB:1; /* Symbol Window Transmit Conflict on Channel B */
18849 #ifndef USE_FIELD_ALIASES_FR
18850  vuint16_t SSVB:1; /* Symbol Window Boundary Violation on Channel B */
18851 #else
18852  vuint16_t SBVB:1; /* deprecated name - please avoid */
18853 #endif
18854  vuint16_t SSEB:1; /* Symbol Window Syntax Error on Channel B */
18855  vuint16_t MTB:1; /* Media Access Test Symbol MTS Received on Channel B */
18856  vuint16_t NBVA:1; /* NIT Boundary Violation on Channel A */
18857  vuint16_t NSEA:1; /* NIT Syntax Error on Channel A */
18858  vuint16_t STCA:1; /* Symbol Window Transmit Conflict on Channel A */
18859  vuint16_t SBVA:1; /* Symbol Window Boundary Violation on Channel A */
18860  vuint16_t SSEA:1; /* Symbol Window Syntax Error on Channel A */
18861  vuint16_t MTA:1; /* Media Access Test Symbol MTS Received on Channel A */
18862  vuint16_t CLKCORRFAILCNT:4; /* Clock Correction Failed Counter */
18863  } B;
18864  } FR_PSR2_16B_tag;
18865 
18866  typedef union { /* Protocol Status Register 3 */
18867  vuint16_t R;
18868  struct {
18869  vuint16_t:2;
18870  vuint16_t WUB:1; /* Wakeup Symbol Received on Channel B */
18871  vuint16_t ABVB:1; /* Aggregated Boundary Violation on Channel B */
18872  vuint16_t AACB:1; /* Aggregated Additional Communication on Channel B */
18873  vuint16_t ACEB:1; /* Aggregated Content Error on Channel B */
18874  vuint16_t ASEB:1; /* Aggregated Syntax Error on Channel B */
18875  vuint16_t AVFB:1; /* Aggregated Valid Frame on Channel B */
18876  vuint16_t:2;
18877  vuint16_t WUA:1; /* Wakeup Symbol Received on Channel A */
18878  vuint16_t ABVA:1; /* Aggregated Boundary Violation on Channel A */
18879  vuint16_t AACA:1; /* Aggregated Additional Communication on Channel A */
18880  vuint16_t ACEA:1; /* Aggregated Content Error on Channel A */
18881  vuint16_t ASEA:1; /* Aggregated Syntax Error on Channel A */
18882  vuint16_t AVFA:1; /* Aggregated Valid Frame on Channel A */
18883  } B;
18884  } FR_PSR3_16B_tag;
18885 
18886  typedef union { /* Macrotick Counter Register */
18887  vuint16_t R;
18888  struct {
18889  vuint16_t:2;
18890  vuint16_t MTCT:14; /* Macrotick Counter */
18891  } B;
18892  } FR_MTCTR_16B_tag;
18893 
18894  typedef union { /* Cycle Counter Register */
18895  vuint16_t R;
18896  struct {
18897  vuint16_t:10;
18898  vuint16_t CYCCNT:6; /* Cycle Counter */
18899  } B;
18900  } FR_CYCTR_16B_tag;
18901 
18902  typedef union { /* Slot Counter Channel A Register */
18903  vuint16_t R;
18904  struct {
18905  vuint16_t:5;
18906  vuint16_t SLOTCNTA:11; /* Slot Counter Value for Channel A */
18907  } B;
18908  } FR_SLTCTAR_16B_tag;
18909 
18910  typedef union { /* Slot Counter Channel B Register */
18911  vuint16_t R;
18912  struct {
18913  vuint16_t:5;
18914  vuint16_t SLOTCNTB:11; /* Slot Counter Value for Channel B */
18915  } B;
18916  } FR_SLTCTBR_16B_tag;
18917 
18918  typedef union { /* Rate Correction Value Register */
18919  vuint16_t R;
18920  struct {
18921  vuint16_t RATECORR:16; /* Rate Correction Value */
18922  } B;
18923  } FR_RTCORVR_16B_tag;
18924 
18925  typedef union { /* Offset Correction Value Register */
18926  vuint16_t R;
18927  struct {
18928  vuint16_t:6;
18929  vuint16_t OFFSETCORR:10; /* Offset Correction Value */
18930  } B;
18931  } FR_OFCORVR_16B_tag;
18932 
18933  typedef union { /* Combined Interrupt Flag Register */
18934  vuint16_t R;
18935  struct {
18936  vuint16_t:8;
18937 #ifndef USE_FIELD_ALIASES_FR
18938  vuint16_t MIF:1; /* Module Interrupt Flag */
18939 #else
18940  vuint16_t MIFR:1; /* deprecated name - please avoid */
18941 #endif
18942 #ifndef USE_FIELD_ALIASES_FR
18943  vuint16_t PRIF:1; /* Protocol Interrupt Flag */
18944 #else
18945  vuint16_t PRIFR:1; /* deprecated name - please avoid */
18946 #endif
18947 #ifndef USE_FIELD_ALIASES_FR
18948  vuint16_t CHIF:1; /* CHI Interrupt Flag */
18949 #else
18950  vuint16_t CHIFR:1; /* deprecated name - please avoid */
18951 #endif
18952 #ifndef USE_FIELD_ALIASES_FR
18953  vuint16_t WUPIF:1; /* Wakeup Interrupt Flag */
18954 #else
18955  vuint16_t WUPIFR:1; /* deprecated name - please avoid */
18956 #endif
18957 #ifndef USE_FIELD_ALIASES_FR
18958  vuint16_t FAFBIF:1; /* Receive FIFO channel B Almost Full Interrupt Flag */
18959 #else
18960  vuint16_t FNEBIFR:1; /* deprecated name - please avoid */
18961 #endif
18962 #ifndef USE_FIELD_ALIASES_FR
18963  vuint16_t FAFAIF:1; /* Receive FIFO channel A Almost Full Interrupt Flag */
18964 #else
18965  vuint16_t FNEAIFR:1; /* deprecated name - please avoid */
18966 #endif
18967 #ifndef USE_FIELD_ALIASES_FR
18968  vuint16_t RBIF:1; /* Receive Message Buffer Interrupt Flag */
18969 #else
18970  vuint16_t RBIFR:1; /* deprecated name - please avoid */
18971 #endif
18972 #ifndef USE_FIELD_ALIASES_FR
18973  vuint16_t TBIF:1; /* Transmit Message Buffer Interrupt Flag */
18974 #else
18975  vuint16_t TBIFR:1; /* deprecated name - please avoid */
18976 #endif
18977  } B;
18978  } FR_CIFR_16B_tag;
18979 
18980  typedef union { /* System Memory Access Time-Out Register */
18981  vuint16_t R;
18982  struct {
18983  vuint16_t:8;
18984  vuint16_t TIMEOUT:8; /* Time-Out */
18985  } B;
18986  } FR_SYMATOR_16B_tag;
18987 
18988  typedef union { /* Sync Frame Counter Register */
18989  vuint16_t R;
18990  struct {
18991  vuint16_t SFEVB:4; /* Sync Frames Channel B, even cycle */
18992  vuint16_t SFEVA:4; /* Sync Frames Channel A, even cycle */
18993  vuint16_t SFODB:4; /* Sync Frames Channel B, odd cycle */
18994  vuint16_t SFODA:4; /* Sync Frames Channel A, odd cycle */
18995  } B;
18996  } FR_SFCNTR_16B_tag;
18997 
18998  typedef union { /* Sync Frame Table Offset Register */
18999  vuint16_t R;
19000  struct {
19001  vuint16_t SFT_OFFSET_15_1:15; /* Sync Frame Table Offset */
19002  vuint16_t:1;
19003  } B;
19004  } FR_SFTOR_16B_tag;
19005 
19006  typedef union { /* Sync Frame Table Configuration, Control, Status Register */
19007  vuint16_t R;
19008  struct {
19009  vuint16_t ELKT:1; /* Even Cycle Tables Lock/Unlock Trigger */
19010  vuint16_t OLKT:1; /* Odd Cycle Tables Lock/Unlock Trigger */
19011  vuint16_t CYCNUM:6; /* Cycle Number */
19012  vuint16_t ELKS:1; /* Even Cycle Tables Lock Status */
19013  vuint16_t OLKS:1; /* Odd Cycle Tables Lock Status */
19014  vuint16_t EVAL:1; /* Even Cycle Tables Valid */
19015  vuint16_t OVAL:1; /* Odd Cycle Tables Valid */
19016  vuint16_t:1;
19017  vuint16_t OPT:1; /* One Pair Trigger */
19018  vuint16_t SDVEN:1; /* Sync Frame Deviation Table Enable */
19019 #ifndef USE_FIELD_ALIASES_FR
19020  vuint16_t SIVEN:1; /* Sync Frame ID Table Enable */
19021 #else
19022  vuint16_t SIDEN:1; /* deprecated name - please avoid */
19023 #endif
19024  } B;
19025  } FR_SFTCCSR_16B_tag;
19026 
19027  typedef union { /* Sync Frame ID Rejection Filter */
19028  vuint16_t R;
19029  struct {
19030  vuint16_t:6;
19031  vuint16_t SYNFRID:10; /* Sync Frame Rejection ID */
19032  } B;
19033  } FR_SFIDRFR_16B_tag;
19034 
19035  typedef union { /* Sync Frame ID Acceptance Filter Value Register */
19036  vuint16_t R;
19037  struct {
19038  vuint16_t:6;
19039  vuint16_t FVAL:10; /* Filter Value */
19040  } B;
19041  } FR_SFIDAFVR_16B_tag;
19042 
19043  typedef union { /* Sync Frame ID Acceptance Filter Mask Register */
19044  vuint16_t R;
19045  struct {
19046  vuint16_t:6;
19047  vuint16_t FMSK:10; /* Filter Mask */
19048  } B;
19049  } FR_SFIDAFMR_16B_tag;
19050 
19051  typedef union { /* Network Management Vector Register0 */
19052  vuint16_t R;
19053  struct {
19054  vuint16_t NMVP_15_8:8; /* Network Management Vector Part */
19055  vuint16_t NMVP_7_0:8; /* Network Management Vector Part */
19056  } B;
19057  } FR_NMVR0_16B_tag;
19058 
19059  typedef union { /* Network Management Vector Register1 */
19060  vuint16_t R;
19061  struct {
19062  vuint16_t NMVP_15_8:8; /* Network Management Vector Part */
19063  vuint16_t NMVP_7_0:8; /* Network Management Vector Part */
19064  } B;
19065  } FR_NMVR1_16B_tag;
19066 
19067  typedef union { /* Network Management Vector Register2 */
19068  vuint16_t R;
19069  struct {
19070  vuint16_t NMVP_15_8:8; /* Network Management Vector Part */
19071  vuint16_t NMVP_7_0:8; /* Network Management Vector Part */
19072  } B;
19073  } FR_NMVR2_16B_tag;
19074 
19075  typedef union { /* Network Management Vector Register3 */
19076  vuint16_t R;
19077  struct {
19078  vuint16_t NMVP_15_8:8; /* Network Management Vector Part */
19079  vuint16_t NMVP_7_0:8; /* Network Management Vector Part */
19080  } B;
19081  } FR_NMVR3_16B_tag;
19082 
19083  typedef union { /* Network Management Vector Register4 */
19084  vuint16_t R;
19085  struct {
19086  vuint16_t NMVP_15_8:8; /* Network Management Vector Part */
19087  vuint16_t NMVP_7_0:8; /* Network Management Vector Part */
19088  } B;
19089  } FR_NMVR4_16B_tag;
19090 
19091  typedef union { /* Network Management Vector Register5 */
19092  vuint16_t R;
19093  struct {
19094  vuint16_t NMVP_15_8:8; /* Network Management Vector Part */
19095  vuint16_t NMVP_7_0:8; /* Network Management Vector Part */
19096  } B;
19097  } FR_NMVR5_16B_tag;
19098 
19099  typedef union { /* Network Management Vector Length Register */
19100  vuint16_t R;
19101  struct {
19102  vuint16_t:12;
19103  vuint16_t NMVL:4; /* Network Management Vector Length */
19104  } B;
19105  } FR_NMVLR_16B_tag;
19106 
19107  typedef union { /* Timer Configuration and Control Register */
19108  vuint16_t R;
19109  struct {
19110  vuint16_t:2;
19111 #ifndef USE_FIELD_ALIASES_FR
19112  vuint16_t T2_CFG:1; /* Timer T2 Configuration */
19113 #else
19114  vuint16_t T2CFG:1; /* Timer T2 Configuration */
19115 #endif
19116 #ifndef USE_FIELD_ALIASES_FR
19117  vuint16_t T2_REP:1; /* Timer T2 Repetitive Mode */
19118 #else
19119  vuint16_t T2REP:1; /* Timer T2 Configuration */
19120 #endif
19121  vuint16_t:1;
19122  vuint16_t T2SP:1; /* Timer T2 Stop */
19123  vuint16_t T2TR:1; /* Timer T2 Trigger */
19124  vuint16_t T2ST:1; /* Timer T2 State */
19125  vuint16_t:3;
19126 #ifndef USE_FIELD_ALIASES_FR
19127  vuint16_t T1_REP:1; /* Timer T1 Repetitive Mode */
19128 #else
19129  vuint16_t T1REP:1;
19130 #endif
19131  vuint16_t:1;
19132  vuint16_t T1SP:1; /* Timer T1 Stop */
19133  vuint16_t T1TR:1; /* Timer T1 Trigger */
19134  vuint16_t T1ST:1; /* Timer T1 State */
19135  } B;
19136  } FR_TICCR_16B_tag;
19137 
19138  typedef union { /* Timer 1 Cycle Set Register */
19139  vuint16_t R;
19140  struct {
19141  vuint16_t:2;
19142 #ifndef USE_FIELD_ALIASES_FR
19143  vuint16_t T1_CYC_VAL:6; /* Timer T1 Cycle Filter Value */
19144 #else
19145  vuint16_t TI1CYCVAL:1; /* Timer T1 Cycle Filter Value */
19146 #endif
19147  vuint16_t:2;
19148 #ifndef USE_FIELD_ALIASES_FR
19149  vuint16_t T1_CYC_MSK:6; /* Timer T1 Cycle Filter Mask */
19150 #else
19151  vuint16_t TI1CYCMSK:1; /* Timer T1 Cycle Filter Mask */
19152 #endif
19153  } B;
19154  } FR_TI1CYSR_16B_tag;
19155 
19156  typedef union { /* Timer 1 Macrotick Offset Register */
19157  vuint16_t R;
19158  struct {
19159  vuint16_t:2;
19160  vuint16_t T1_MTOFFSET:14; /* Timer 1 Macrotick Offset */
19161  } B;
19162  } FR_TI1MTOR_16B_tag;
19163 
19164  typedef union { /* Timer 2 Configuration Register 0 */
19165  vuint16_t R;
19166  struct {
19167  vuint16_t:2;
19168  vuint16_t T2_CYC_VAL:6; /* Timer T2 Cycle Filter Value */
19169  vuint16_t:2;
19170  vuint16_t T2_CYC_MSK:6; /* Timer T2 Cycle Filter Mask */
19171  } B;
19172  } FR_TI2CR0_16B_tag;
19173 
19174  typedef union { /* Timer 2 Configuration Register 1 */
19175  vuint16_t R;
19176  struct {
19177  vuint16_t T2_MTCNT:16; /* Timer T2 Macrotick Offset */
19178  } B;
19179  } FR_TI2CR1_16B_tag;
19180 
19181  typedef union { /* Slot Status Selection Register */
19182  vuint16_t R;
19183  struct {
19184  vuint16_t WMD:1; /* Write Mode */
19185  vuint16_t:1;
19186  vuint16_t SEL:2; /* Selector */
19187  vuint16_t:1;
19188  vuint16_t SLOTNUMBER:11; /* Slot Number */
19189  } B;
19190  } FR_SSSR_16B_tag;
19191 
19192  typedef union { /* Slot Status Counter Condition Register */
19193  vuint16_t R;
19194  struct {
19195  vuint16_t WMD:1; /* Write Mode */
19196  vuint16_t:1;
19197  vuint16_t SEL:2; /* Selector */
19198  vuint16_t:1;
19199  vuint16_t CNTCFG:2; /* Counter Configuration */
19200  vuint16_t MCY:1; /* Multi Cycle Selection */
19201  vuint16_t VFR:1; /* Valid Frame Restriction */
19202  vuint16_t SYF:1; /* Sync Frame Restriction */
19203  vuint16_t NUF:1; /* Null Frame Restriction */
19204  vuint16_t SUF:1; /* Startup Frame Restriction */
19205  vuint16_t STATUSMASK:4; /* Slot Status Mask */
19206  } B;
19207  } FR_SSCCR_16B_tag;
19208 
19209  typedef union { /* Slot Status Register0 */
19210  vuint16_t R;
19211  struct {
19212  vuint16_t VFB:1; /* Valid Frame on Channel B */
19213  vuint16_t SYB:1; /* Sync Frame Indicator Channel B */
19214  vuint16_t NFB:1; /* Null Frame Indicator Channel B */
19215  vuint16_t SUB:1; /* Startup Frame Indicator Channel B */
19216  vuint16_t SEB:1; /* Syntax Error on Channel B */
19217  vuint16_t CEB:1; /* Content Error on Channel B */
19218  vuint16_t BVB:1; /* Boundary Violation on Channel B */
19219  vuint16_t TCB:1; /* Transmission Conflict on Channel B */
19220  vuint16_t VFA:1; /* Valid Frame on Channel A */
19221  vuint16_t SYA:1; /* Sync Frame Indicator Channel A */
19222  vuint16_t NFA:1; /* Null Frame Indicator Channel A */
19223  vuint16_t SUA:1; /* Startup Frame Indicator Channel A */
19224  vuint16_t SEA:1; /* Syntax Error on Channel A */
19225  vuint16_t CEA:1; /* Content Error on Channel A */
19226  vuint16_t BVA:1; /* Boundary Violation on Channel A */
19227  vuint16_t TCA:1; /* Transmission Conflict on Channel A */
19228  } B;
19229  } FR_SSR_16B_tag;
19230 
19231 
19232 
19233  typedef union { /* Slot Status Counter Register0 */
19234  vuint16_t R;
19235  struct {
19236  vuint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */
19237  } B;
19238  } FR_SSCR0_16B_tag;
19239 
19240  typedef union { /* Slot Status Counter Register1 */
19241  vuint16_t R;
19242  struct {
19243  vuint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */
19244  } B;
19245  } FR_SSCR1_16B_tag;
19246 
19247  typedef union { /* Slot Status Counter Register2 */
19248  vuint16_t R;
19249  struct {
19250  vuint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */
19251  } B;
19252  } FR_SSCR2_16B_tag;
19253 
19254  typedef union { /* Slot Status Counter Register3 */
19255  vuint16_t R;
19256  struct {
19257  vuint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */
19258  } B;
19259  } FR_SSCR3_16B_tag;
19260 
19261  typedef union { /* MTS A Configuration Register */
19262  vuint16_t R;
19263  struct {
19264  vuint16_t MTE:1; /* Media Access Test Symbol Transmission Enable */
19265  vuint16_t:1;
19266  vuint16_t CYCCNTMSK:6; /* Cycle Counter Mask */
19267  vuint16_t:2;
19268  vuint16_t CYCCNTVAL:6; /* Cycle Counter Value */
19269  } B;
19270  } FR_MTSACFR_16B_tag;
19271 
19272  typedef union { /* MTS B Configuration Register */
19273  vuint16_t R;
19274  struct {
19275  vuint16_t MTE:1; /* Media Access Test Symbol Transmission Enable */
19276  vuint16_t:1;
19277  vuint16_t CYCCNTMSK:6; /* Cycle Counter Mask */
19278  vuint16_t:2;
19279  vuint16_t CYCCNTVAL:6; /* Cycle Counter Value */
19280  } B;
19281  } FR_MTSBCFR_16B_tag;
19282 
19283  typedef union { /* Receive Shadow Buffer Index Register */
19284  vuint16_t R;
19285  struct {
19286  vuint16_t WMD:1; /* Write Mode */
19287  vuint16_t:1;
19288  vuint16_t SEL:2; /* Selector */
19289  vuint16_t:5;
19290  vuint16_t RSBIDX:7; /* Receive Shadow Buffer Index */
19291  } B;
19292  } FR_RSBIR_16B_tag;
19293 
19294  typedef union { /* Receive FIFO Watermark and Selection Register */
19295  vuint16_t R;
19296  struct {
19297  vuint16_t WM:8; /* Watermark Value */
19298  vuint16_t:7;
19299  vuint16_t SEL:1; /* Select */
19300  } B;
19301  } FR_RFWMSR_16B_tag;
19302 
19303  typedef union { /* Receive FIFO Start Index Register */
19304  vuint16_t R;
19305  struct {
19306  vuint16_t:6;
19307  vuint16_t SIDX:10; /* Start Index */
19308  } B;
19309  } FR_RF_RFSIR_16B_tag;
19310 
19311  typedef union { /* Receive FIFO Depth and Size Register */
19312  vuint16_t R;
19313  struct {
19314 #ifndef USE_FIELD_ALIASES_FR
19315  vuint16_t FIFO_DEPTH:8; /* FIFO Depth */
19316 #else
19317  vuint16_t FIFODEPTH:8; /* deprecated name - please avoid */
19318 #endif
19319  vuint16_t:1;
19320 #ifndef USE_FIELD_ALIASES_FR
19321  vuint16_t ENTRY_SIZE:7; /* Entry Size */
19322 #else
19323  vuint16_t ENTRYSIZE:7; /* deprecated name - please avoid */
19324 #endif
19325  } B;
19326  } FR_RFDSR_16B_tag;
19327 
19328  typedef union { /* Receive FIFO A Read Index Register */
19329  vuint16_t R;
19330  struct {
19331  vuint16_t:6;
19332  vuint16_t RDIDX:10; /* Read Index */
19333  } B;
19334  } FR_RFARIR_16B_tag;
19335 
19336  typedef union { /* Receive FIFO B Read Index Register */
19337  vuint16_t R;
19338  struct {
19339  vuint16_t:6;
19340  vuint16_t RDIDX:10; /* Read Index */
19341  } B;
19342  } FR_RFBRIR_16B_tag;
19343 
19344  typedef union { /* Receive FIFO Message ID Acceptance Filter Value Register */
19345  vuint16_t R;
19346  struct {
19347  vuint16_t MIDAFVAL:16; /* Message ID Acceptance Filter Value */
19348  } B;
19349  } FR_RFMIDAFVR_16B_tag;
19350 
19351  typedef union { /* Receive FIFO Message ID Acceptance Filter Mask Register */
19352  vuint16_t R;
19353  struct {
19354  vuint16_t MIDAFMSK:16; /* Message ID Acceptance Filter Mask */
19355  } B;
19356  } FR_RFMIDAFMR_16B_tag;
19357 
19358  typedef union { /* Receive FIFO Frame ID Rejection Filter Value Register */
19359  vuint16_t R;
19360  struct {
19361  vuint16_t:5;
19362  vuint16_t FIDRFVAL:11; /* Frame ID Rejection Filter Value */
19363  } B;
19364  } FR_RFFIDRFVR_16B_tag;
19365 
19366  typedef union { /* Receive FIFO Frame ID Rejection Filter Mask Register */
19367  vuint16_t R;
19368  struct {
19369  vuint16_t:5;
19370  vuint16_t FIDRFMSK:11; /* Frame ID Rejection Filter Mask */
19371  } B;
19372  } FR_RFFIDRFMR_16B_tag;
19373 
19374  typedef union { /* Receive FIFO Range Filter Configuration Register */
19375  vuint16_t R;
19376  struct {
19377  vuint16_t WMD:1; /* Write Mode */
19378  vuint16_t IBD:1; /* Interval Boundary */
19379  vuint16_t SEL:2; /* Filter Selector */
19380  vuint16_t:1;
19381  vuint16_t SID:11; /* Slot ID */
19382  } B;
19383  } FR_RFRFCFR_16B_tag;
19384 
19385  typedef union { /* Receive FIFO Range Filter Control Register */
19386  vuint16_t R;
19387  struct {
19388  vuint16_t:4;
19389  vuint16_t F3MD:1; /* Range Filter 3 Mode */
19390  vuint16_t F2MD:1; /* Range Filter 2 Mode */
19391  vuint16_t F1MD:1; /* Range Filter 1 Mode */
19392  vuint16_t F0MD:1; /* Range Filter 0 Mode */
19393  vuint16_t:4;
19394  vuint16_t F3EN:1; /* Range Filter 3 Enable */
19395  vuint16_t F2EN:1; /* Range Filter 2 Enable */
19396  vuint16_t F1EN:1; /* Range Filter 1 Enable */
19397  vuint16_t F0EN:1; /* Range Filter 0 Enable */
19398  } B;
19399  } FR_RFRFCTR_16B_tag;
19400 
19401  typedef union { /* Last Dynamic Transmit Slot Channel A Register */
19402  vuint16_t R;
19403  struct {
19404  vuint16_t:5;
19405  vuint16_t LASTDYNTXSLOTA:11; /* Last Dynamic Transmission Slot Channel A */
19406  } B;
19407  } FR_LDTXSLAR_16B_tag;
19408 
19409  typedef union { /* Last Dynamic Transmit Slot Channel B Register */
19410  vuint16_t R;
19411  struct {
19412  vuint16_t:5;
19413  vuint16_t LASTDYNTXSLOTB:11; /* Last Dynamic Transmission Slot Channel B */
19414  } B;
19415  } FR_LDTXSLBR_16B_tag;
19416 
19417  typedef union { /* Protocol Configuration Register 0 */
19418  vuint16_t R;
19419  struct {
19420  vuint16_t ACTION_POINT_OFFSET:6; /* gdActionPointOffset - 1 */
19421  vuint16_t STATIC_SLOT_LENGTH:10; /* gdStaticSlot */
19422  } B;
19423  } FR_PCR0_16B_tag;
19424 
19425  typedef union { /* Protocol Configuration Register 1 */
19426  vuint16_t R;
19427  struct {
19428  vuint16_t:2;
19429  vuint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14; /* gMacroPerCycle - gdStaticSlot */
19430  } B;
19431  } FR_PCR1_16B_tag;
19432 
19433  typedef union { /* Protocol Configuration Register 2 */
19434  vuint16_t R;
19435  struct {
19436  vuint16_t MINISLOT_AFTER_ACTION_POINT:6; /* gdMinislot - gdMinislotActionPointOffset - 1 */
19437  vuint16_t NUMBER_OF_STATIC_SLOTS:10; /* gNumberOfStaticSlots */
19438  } B;
19439  } FR_PCR2_16B_tag;
19440 
19441  typedef union { /* Protocol Configuration Register 3 */
19442  vuint16_t R;
19443  struct {
19444  vuint16_t WAKEUP_SYMBOL_RX_LOW:6; /* gdWakeupSymbolRxLow */
19445 #ifndef USE_FIELD_ALIASES_FR
19446  vuint16_t MINISLOT_ACTION_POINT_OFFSET_4_0:5; /* gdMinislotActionPointOffset - 1 */
19447 #else
19448  vuint16_t MINISLOT_ACTION_POINT_OFFSET:5; /* deprecated name - please avoid */
19449 #endif
19450  vuint16_t COLDSTART_ATTEMPTS:5; /* gColdstartAttempts */
19451  } B;
19452  } FR_PCR3_16B_tag;
19453 
19454  typedef union { /* Protocol Configuration Register 4 */
19455  vuint16_t R;
19456  struct {
19457  vuint16_t CAS_RX_LOW_MAX:7; /* gdCASRxLowMax - 1 */
19458  vuint16_t WAKEUP_SYMBOL_RX_WINDOW:9; /* gdWakeupSymbolRxWindow */
19459  } B;
19460  } FR_PCR4_16B_tag;
19461 
19462  typedef union { /* Protocol Configuration Register 5 */
19463  vuint16_t R;
19464  struct {
19465  vuint16_t TSS_TRANSMITTER:4; /* gdTSSTransmitter */
19466  vuint16_t WAKEUP_SYMBOL_TX_LOW:6; /* gdWakeupSymbolTxLow */
19467  vuint16_t WAKEUP_SYMBOL_RX_IDLE:6; /* gdWakeupSymbolRxIdle */
19468  } B;
19469  } FR_PCR5_16B_tag;
19470 
19471  typedef union { /* Protocol Configuration Register 6 */
19472  vuint16_t R;
19473  struct {
19474  vuint16_t:1;
19475  vuint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8; /* gdSymbolWindow - gdActionPointOffset - 1 */
19476 #ifndef USE_FIELD_ALIASES_FR
19477  vuint16_t MACRO_INITIAL_OFFSET_A:7; /* pMacroInitialOffset[A] */
19478 #else
19479  vuint16_t MICRO_INITIAL_OFFSET_A:7; /* deprecated name - please avoid */
19480 #endif
19481  } B;
19482  } FR_PCR6_16B_tag;
19483 
19484  typedef union { /* Protocol Configuration Register 7 */
19485  vuint16_t R;
19486  struct {
19487  vuint16_t DECODING_CORRECTION_B:9; /* pDecodingCorrection + pDelayCompensation[B] + 2 */
19488  vuint16_t MICRO_PER_MACRO_NOM_HALF:7; /* round(pMicroPerMacroNom / 2) */
19489  } B;
19490  } FR_PCR7_16B_tag;
19491 
19492  typedef union { /* Protocol Configuration Register 8 */
19493  vuint16_t R;
19494  struct {
19495  vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4; /* gMaxWithoutClockCorrectionFatal */
19496  vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4; /* gMaxWithoutClockCorrectionPassive */
19497  vuint16_t WAKEUP_SYMBOL_TX_IDLE:8; /* gdWakeupSymbolTxIdle */
19498  } B;
19499  } FR_PCR8_16B_tag;
19500 
19501  typedef union { /* Protocol Configuration Register 9 */
19502  vuint16_t R;
19503  struct {
19504  vuint16_t MINISLOT_EXISTS:1; /* gNumberOfMinislots!=0 */
19505  vuint16_t SYMBOL_WINDOW_EXISTS:1; /* gdSymbolWindow!=0 */
19506  vuint16_t OFFSET_CORRECTION_OUT:14; /* pOffsetCorrectionOut */
19507  } B;
19508  } FR_PCR9_16B_tag;
19509 
19510  typedef union { /* Protocol Configuration Register 10 */
19511  vuint16_t R;
19512  struct {
19513  vuint16_t SINGLE_SLOT_ENABLED:1; /* pSingleSlotEnabled */
19514  vuint16_t WAKEUP_CHANNEL:1; /* pWakeupChannel */
19515  vuint16_t MACRO_PER_CYCLE:14; /* pMicroPerCycle */
19516  } B;
19517  } FR_PCR10_16B_tag;
19518 
19519  typedef union { /* Protocol Configuration Register 11 */
19520  vuint16_t R;
19521  struct {
19522  vuint16_t KEY_SLOT_USED_FOR_STARTUP:1; /* pKeySlotUsedForStartup */
19523  vuint16_t KEY_SLOT_USED_FOR_SYNC:1; /* pKeySlotUsedForSync */
19524  vuint16_t OFFSET_CORRECTION_START:14; /* gOffsetCorrectionStart */
19525  } B;
19526  } FR_PCR11_16B_tag;
19527 
19528  typedef union { /* Protocol Configuration Register 12 */
19529  vuint16_t R;
19530  struct {
19531  vuint16_t ALLOW_PASSIVE_TO_ACTIVE:5; /* pAllowPassiveToActive */
19532  vuint16_t KEY_SLOT_HEADER_CRC:11; /* header CRC for key slot */
19533  } B;
19534  } FR_PCR12_16B_tag;
19535 
19536  typedef union { /* Protocol Configuration Register 13 */
19537  vuint16_t R;
19538  struct {
19539  vuint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6; /* max(gdActionPointOffset,gdMinislotActionPointOffset) - 1 */
19540  vuint16_t STATIC_SLOT_AFTER_ACTION_POINT:10; /* gdStaticSlot - gdActionPointOffset - 1 */
19541  } B;
19542  } FR_PCR13_16B_tag;
19543 
19544  typedef union { /* Protocol Configuration Register 14 */
19545  vuint16_t R;
19546  struct {
19547  vuint16_t RATE_CORRECTION_OUT:11; /* pRateCorrectionOut */
19548 #ifndef USE_FIELD_ALIASES_FR
19549  vuint16_t LISTEN_TIMEOUT_20_16:5; /* pdListenTimeout - 1 */
19550 #else
19551  vuint16_t LISTEN_TIMEOUT_H:5; /* deprecated name - please avoid */
19552 #endif
19553  } B;
19554  } FR_PCR14_16B_tag;
19555 
19556  typedef union { /* Protocol Configuration Register 15 */
19557  vuint16_t R;
19558  struct {
19559 #ifndef USE_FIELD_ALIASES_FR
19560  vuint16_t LISTEN_TIMEOUT_15_0:16; /* pdListenTimeout - 1 */
19561 #else
19562  vuint16_t LISTEN_TIMEOUT_L:16; /* deprecated name - please avoid */
19563 #endif
19564  } B;
19565  } FR_PCR15_16B_tag;
19566 
19567  typedef union { /* Protocol Configuration Register 16 */
19568  vuint16_t R;
19569  struct {
19570 #ifndef USE_FIELD_ALIASES_FR
19571  vuint16_t MACRO_INITIAL_OFFSET_B:7; /* pMacroInitialOffset[B] */
19572 #else
19573  vuint16_t MICRO_INITIAL_OFFSET_B:7; /* deprecated name - please avoid */
19574 #endif
19575 #ifndef USE_FIELD_ALIASES_FR
19576  vuint16_t NOISE_LISTEN_TIMEOUT_24_16:9; /* (gListenNoise * pdListenTimeout) - 1 */
19577 #else
19578  vuint16_t NOISE_LISTEN_TIMEOUT_H:9; /* deprecated name - please avoid */
19579 #endif
19580  } B;
19581  } FR_PCR16_16B_tag;
19582 
19583  typedef union { /* Protocol Configuration Register 17 */
19584  vuint16_t R;
19585  struct {
19586 #ifndef USE_FIELD_ALIASES_FR
19587  vuint16_t NOISE_LISTEN_TIMEOUT_15_0:16; /* (gListenNoise * pdListenTimeout) - 1 */
19588 #else
19589  vuint16_t NOISE_LISTEN_TIMEOUT_L:16; /* deprecated name - please avoid */
19590 #endif
19591  } B;
19592  } FR_PCR17_16B_tag;
19593 
19594  typedef union { /* Protocol Configuration Register 18 */
19595  vuint16_t R;
19596  struct {
19597  vuint16_t WAKEUP_PATTERN:6; /* pWakeupPattern */
19598  vuint16_t KEY_SLOT_ID:10; /* pKeySlotId */
19599  } B;
19600  } FR_PCR18_16B_tag;
19601 
19602  typedef union { /* Protocol Configuration Register 19 */
19603  vuint16_t R;
19604  struct {
19605  vuint16_t DECODING_CORRECTION_A:9; /* pDecodingCorrection + pDelayCompensation[A] + 2 */
19606  vuint16_t PAYLOAD_LENGTH_STATIC:7; /* gPayloadLengthStatic */
19607  } B;
19608  } FR_PCR19_16B_tag;
19609 
19610  typedef union { /* Protocol Configuration Register 20 */
19611  vuint16_t R;
19612  struct {
19613 #ifndef USE_FIELD_ALIASES_FR
19614  vuint16_t MACRO_INITIAL_OFFSET_B:8; /* pMicroInitialOffset[B] */
19615 #else
19616  vuint16_t MICRO_INITIAL_OFFSET_B:8; /* deprecated name - please avoid */
19617 #endif
19618 #ifndef USE_FIELD_ALIASES_FR
19619  vuint16_t MACRO_INITIAL_OFFSET_A:8; /* pMicroInitialOffset[A] */
19620 #else
19621  vuint16_t MICRO_INITIAL_OFFSET_A:8; /* deprecated name - please avoid */
19622 #endif
19623  } B;
19624  } FR_PCR20_16B_tag;
19625 
19626  typedef union { /* Protocol Configuration Register 21 */
19627  vuint16_t R;
19628  struct {
19629  vuint16_t EXTERN_RATE_CORRECTION:3; /* pExternRateCorrection */
19630  vuint16_t LATEST_TX:13; /* gNumberOfMinislots - pLatestTx */
19631  } B;
19632  } FR_PCR21_16B_tag;
19633 
19634  typedef union { /* Protocol Configuration Register 22 */
19635  vuint16_t R;
19636  struct {
19637  vuint16_t R:1; /* Reserved bit */
19638 #ifndef USE_FIELD_ALIASES_FR
19639  vuint16_t COMP_ACCEPTED_STARRUP_RANGE_A:11; /* pdAcceptedStartupRange - pDelayCompensationChA */
19640 #else
19641  vuint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11; /* deprecated name - please avoid */
19642 #endif
19643 #ifndef USE_FIELD_ALIASES_FR
19644  vuint16_t MICRO_PER_CYCLE_19_16:4; /* gMicroPerCycle */
19645 #else
19646  vuint16_t MICRO_PER_CYCLE_H:4; /* deprecated name - please avoid */
19647 #endif
19648  } B;
19649  } FR_PCR22_16B_tag;
19650 
19651  typedef union { /* Protocol Configuration Register 23 */
19652  vuint16_t R;
19653  struct {
19654 #ifndef USE_FIELD_ALIASES_FR
19655  vuint16_t MICRO_PER_CYCLE_15_0:16; /* pMicroPerCycle */
19656 #else
19657  vuint16_t micro_per_cycle_l:16; /* deprecated name - please avoid */
19658 #endif
19659  } B;
19660  } FR_PCR23_16B_tag;
19661 
19662  typedef union { /* Protocol Configuration Register 24 */
19663  vuint16_t R;
19664  struct {
19665  vuint16_t CLUSTER_DRIFT_DAMPING:5; /* pClusterDriftDamping */
19666  vuint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7; /* pPayloadLengthDynMax */
19667 #ifndef USE_FIELD_ALIASES_FR
19668  vuint16_t MICRO_PER_CYCLE_MIN_19_16:4; /* pMicroPerCycle - pdMaxDrift */
19669 #else
19670  vuint16_t MICRO_PER_CYCLE_MIN_H:4; /* deprecated name - please avoid */
19671 #endif
19672  } B;
19673  } FR_PCR24_16B_tag;
19674 
19675  typedef union { /* Protocol Configuration Register 25 */
19676  vuint16_t R;
19677  struct {
19678 #ifndef USE_FIELD_ALIASES_FR
19679  vuint16_t MICRO_PER_CYCLE_MIN_15_0:16; /* pMicroPerCycle - pdMaxDrift */
19680 #else
19681  vuint16_t MICRO_PER_CYCLE_MIN_L:16; /* deprecated name - please avoid */
19682 #endif
19683  } B;
19684  } FR_PCR25_16B_tag;
19685 
19686  typedef union { /* Protocol Configuration Register 26 */
19687  vuint16_t R;
19688  struct {
19689  vuint16_t ALLOW_HALT_DUE_TO_CLOCK:1; /* pAllowHaltDueToClock */
19690  vuint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11; /* pdAcceptedStartupRange - pDelayCompensationChB */
19691 #ifndef USE_FIELD_ALIASES_FR
19692  vuint16_t MICRO_PER_CYCLE_MAX_19_16:4; /* pMicroPerCycle + pdMaxDrift */
19693 #else
19694  vuint16_t MICRO_PER_CYCLE_MAX_H:4; /* deprecated name - please avoid */
19695 #endif
19696  } B;
19697  } FR_PCR26_16B_tag;
19698 
19699  typedef union { /* Protocol Configuration Register 27 */
19700  vuint16_t R;
19701  struct {
19702 #ifndef USE_FIELD_ALIASES_FR
19703  vuint16_t MICRO_PER_CYCLE_MAX_15_0:16; /* pMicroPerCycle + pdMaxDrift */
19704 #else
19705  vuint16_t MICRO_PER_CYCLE_MAX_L:16; /* deprecated name - please avoid */
19706 #endif
19707  } B;
19708  } FR_PCR27_16B_tag;
19709 
19710  typedef union { /* Protocol Configuration Register 28 */
19711  vuint16_t R;
19712  struct {
19713  vuint16_t DYNAMIC_SLOT_IDLE_PHASE:2; /* gdDynamicSlotIdlePhase */
19714  vuint16_t MACRO_AFTER_OFFSET_CORRECTION:14; /* gMacroPerCycle - gOffsetCorrectionStart */
19715  } B;
19716  } FR_PCR28_16B_tag;
19717 
19718  typedef union { /* Protocol Configuration Register 29 */
19719  vuint16_t R;
19720  struct {
19721  vuint16_t EXTERN_OFFSET_CORRECTION:3; /* pExternOffsetCorrection */
19722  vuint16_t MINISLOTS_MAX:13; /* gNumberOfMinislots - 1 */
19723  } B;
19724  } FR_PCR29_16B_tag;
19725 
19726  typedef union { /* Protocol Configuration Register 30 */
19727  vuint16_t R;
19728  struct {
19729  vuint16_t:12;
19730  vuint16_t SYNC_NODE_MAX:4; /* gSyncNodeMax */
19731  } B;
19732  } FR_PCR30_16B_tag;
19733 
19734  typedef union { /* Receive FIFO System Memory Base Address High Register */
19735  vuint16_t R;
19736  struct {
19737  vuint16_t SMBA_31_16:16; /* System Memory Base Address */
19738  } B;
19739  } FR_RFSYMBHADR_16B_tag;
19740 
19741  typedef union { /* Receive FIFO System Memory Base Address Low Register */
19742  vuint16_t R;
19743  struct {
19744  vuint16_t:4;
19745  vuint16_t SMBA_15_4:12; /* System Memory Base Address */
19746  } B;
19747  } FR_RFSYMBLADR_16B_tag;
19748 
19749  typedef union { /* Receive FIFO Periodic Timer Register */
19750  vuint16_t R;
19751  struct {
19752  vuint16_t:2;
19753  vuint16_t PTD:14; /* Periodic Timer Duration */
19754  } B;
19755  } FR_RFPTR_16B_tag;
19756 
19757  typedef union { /* Receive FIFO Fill Level and Pop Count Register */
19758  vuint16_t R;
19759  struct {
19760  vuint16_t FLPCB:8; /* Fill Level and Pop Count Channel B */
19761  vuint16_t FLPCA:8; /* Fill Level and Pop Count Channel A */
19762  } B;
19763  } FR_RFFLPCR_16B_tag;
19764 
19765  typedef union { /* ECC Error Interrupt Flag and Enable Register */
19766  vuint16_t R;
19767  struct {
19768  vuint16_t LRNE_OF:1; /* LRAM Non-Corrected Error Overflow Flag */
19769  vuint16_t LRCE_OF:1; /* LRAM Corrected Error Overflow Flag */
19770  vuint16_t DRNE_OF:1; /* DRAM Non-Corrected Error Overflow Flag */
19771  vuint16_t DRCE_OF:1; /* DRAM Corrected Error Overflow Flag */
19772  vuint16_t LRNE_IF:1; /* LRAM Non-Corrected Error Interrupt Flag */
19773  vuint16_t LRCE_IF:1; /* LRAM Corrected Error Interrupt Flag */
19774  vuint16_t DRNE_IF:1; /* DRAM Non-Corrected Error Interrupt Flag */
19775  vuint16_t DRCE_IF:1; /* DRAM Corrected Error Interrupt Flag */
19776  vuint16_t:4;
19777  vuint16_t LRNE_IE:1; /* LRAM Non-Corrected Error Interrupt Enable */
19778  vuint16_t LRCE_IE:1; /* LRAM Corrected Error Interrupt Enable */
19779  vuint16_t DRNE_IE:1; /* DRAM Non-Corrected Error Interrupt Enable */
19780  vuint16_t DRCE_IE:1; /* DRAM Corrected Error Interrupt Enable */
19781  } B;
19782  } FR_EEIFER_16B_tag;
19783 
19784  typedef union { /* ECC Error Report and Injection Control Register */
19785  vuint16_t R;
19786  struct {
19787  vuint16_t BSY:1; /* Register Update Busy */
19788  vuint16_t:5;
19789  vuint16_t ERS:2; /* Error Report Select */
19790  vuint16_t:3;
19791  vuint16_t ERM:1; /* Error Report Mode */
19792  vuint16_t:2;
19793  vuint16_t EIM:1; /* Error Injection Mode */
19794  vuint16_t EIE:1; /* Error Injection Enable */
19795  } B;
19796  } FR_EERICR_16B_tag;
19797 
19798  typedef union { /* ECC Error Report Adress Register */
19799  vuint16_t R;
19800  struct {
19801  vuint16_t MID:1; /* Memory Identifier */
19802  vuint16_t BANK:3; /* Memory Bank */
19803  vuint16_t ADDR:12; /* Memory Address */
19804  } B;
19805  } FR_EERAR_16B_tag;
19806 
19807  typedef union { /* ECC Error Report Data Register */
19808  vuint16_t R;
19809  struct {
19810  vuint16_t DATA:16; /* Data */
19811  } B;
19812  } FR_EERDR_16B_tag;
19813 
19814  typedef union { /* ECC Error Report Code Register */
19815  vuint16_t R;
19816  struct {
19817  vuint16_t:11;
19818  vuint16_t CODE:5; /* Code */
19819  } B;
19820  } FR_EERCR_16B_tag;
19821 
19822  typedef union { /* ECC Error Injection Address Register */
19823  vuint16_t R;
19824  struct {
19825  vuint16_t MID:1; /* Memory Identifier */
19826  vuint16_t BANK:3; /* Memory Bank */
19827  vuint16_t ADDR:12; /* Memory Address */
19828  } B;
19829  } FR_EEIAR_16B_tag;
19830 
19831  typedef union { /* ECC Error Injection Data Register */
19832  vuint16_t R;
19833  struct {
19834  vuint16_t DATA:16; /* Data */
19835  } B;
19836  } FR_EEIDR_16B_tag;
19837 
19838  typedef union { /* ECC Error Injection Code Register */
19839  vuint16_t R;
19840  struct {
19841  vuint16_t:11;
19842  vuint16_t CODE:5; /* Code */
19843  } B;
19844  } FR_EEICR_16B_tag;
19845 
19846 
19847  /* Register layout for all registers MBCCSR... */
19848 
19849  typedef union { /* Message Buffer Configuration Control Status Register */
19850  vuint16_t R;
19851  struct {
19852  vuint16_t:1;
19853  vuint16_t MCM:1; /* Message Buffer Commit Mode */
19854  vuint16_t MBT:1; /* Message Buffer Type */
19855  vuint16_t MTD:1; /* Message Buffer Transfer Direction */
19856  vuint16_t CMT:1; /* Commit for Transmission */
19857  vuint16_t EDT:1; /* Enable/Disable Trigger */
19858  vuint16_t LCKT:1; /* Lock/Unlock Trigger */
19859  vuint16_t MBIE:1; /* Message Buffer Interrupt Enable */
19860  vuint16_t:3;
19861  vuint16_t DUP:1; /* Data Updated */
19862  vuint16_t DVAL:1; /* DataValid */
19863  vuint16_t EDS:1; /* Enable/Disable Status */
19864  vuint16_t LCKS:1; /* LockStatus */
19865  vuint16_t MBIF:1; /* Message Buffer Interrupt Flag */
19866  } B;
19867  } FR_MBCCSR_16B_tag;
19868 
19869 
19870  /* Register layout for all registers MBCCFR... */
19871 
19872  typedef union { /* Message Buffer Cycle Counter Filter Register */
19873  vuint16_t R;
19874  struct {
19875  vuint16_t MTM:1; /* Message Buffer Transmission Mode */
19876 #ifndef USE_FIELD_ALIASES_FR
19877  vuint16_t CHA:1; /* Channel Assignment */
19878 #else
19879  vuint16_t CHNLA:1; /* deprecated name - please avoid */
19880 #endif
19881 #ifndef USE_FIELD_ALIASES_FR
19882  vuint16_t CHB:1; /* Channel Assignment */
19883 #else
19884  vuint16_t CHNLB:1; /* deprecated name - please avoid */
19885 #endif
19886  vuint16_t CCFE:1; /* Cycle Counter Filtering Enable */
19887  vuint16_t CCFMSK:6; /* Cycle Counter Filtering Mask */
19888  vuint16_t CCFVAL:6; /* Cycle Counter Filtering Value */
19889  } B;
19890  } FR_MBCCFR_16B_tag;
19891 
19892 
19893  /* Register layout for all registers MBFIDR... */
19894 
19895  typedef union { /* Message Buffer Frame ID Register */
19896  vuint16_t R;
19897  struct {
19898  vuint16_t:5;
19899  vuint16_t FID:11; /* Frame ID */
19900  } B;
19901  } FR_MBFIDR_16B_tag;
19902 
19903 
19904  /* Register layout for all registers MBIDXR... */
19905 
19906  typedef union { /* Message Buffer Index Register */
19907  vuint16_t R;
19908  struct {
19909  vuint16_t:9;
19910  vuint16_t MBIDX:7; /* Message Buffer Index */
19911  } B;
19912  } FR_MBIDXR_16B_tag;
19913 
19914 
19915  /* Register layout for generated register(s) NMVR... */
19916 
19917  typedef union { /* */
19918  vuint16_t R;
19919  } FR_NMVR_16B_tag;
19920 
19921 
19922 
19923 
19924  /* Register layout for generated register(s) SSCR... */
19925 
19926  typedef union { /* */
19927  vuint16_t R;
19928  } FR_SSCR_16B_tag;
19929 
19930 
19931  typedef struct FR_MB_struct_tag {
19932 
19933  /* Message Buffer Configuration Control Status Register */
19934  FR_MBCCSR_16B_tag MBCCSR; /* relative offset: 0x0000 */
19935  /* Message Buffer Cycle Counter Filter Register */
19936  FR_MBCCFR_16B_tag MBCCFR; /* relative offset: 0x0002 */
19937  /* Message Buffer Frame ID Register */
19938  FR_MBFIDR_16B_tag MBFIDR; /* relative offset: 0x0004 */
19939  /* Message Buffer Index Register */
19940  FR_MBIDXR_16B_tag MBIDXR; /* relative offset: 0x0006 */
19941 
19942  } FR_MB_tag;
19943 
19944 
19945  typedef struct FR_struct_tag { /* start of FR_tag */
19946  /* Module Version Number */
19947  FR_MVR_16B_tag MVR; /* offset: 0x0000 size: 16 bit */
19948  /* Module Configuration Register */
19949  FR_MCR_16B_tag MCR; /* offset: 0x0002 size: 16 bit */
19950  union {
19951  FR_SYMBADHR_16B_tag SYSBADHR; /* deprecated - please avoid */
19952 
19953  /* SYSTEM MEMORY BASE ADD HIGH REG */
19954  FR_SYMBADHR_16B_tag SYMBADHR; /* offset: 0x0004 size: 16 bit */
19955 
19956  };
19957  union {
19958  FR_SYMBADLR_16B_tag SYSBADLR; /* deprecated - please avoid */
19959 
19960  /* SYSTEM MEMORY BASE ADD LOW REG */
19961  FR_SYMBADLR_16B_tag SYMBADLR; /* offset: 0x0006 size: 16 bit */
19962 
19963  };
19964  /* STROBE SIGNAL CONTROL REGISTER */
19965  FR_STBSCR_16B_tag STBSCR; /* offset: 0x0008 size: 16 bit */
19966  int8_t FR_reserved_000A[2];
19967  /* MESSAGE BUFFER DATA SIZE REGISTER */
19968  FR_MBDSR_16B_tag MBDSR; /* offset: 0x000C size: 16 bit */
19969  /* MESS. BUFFER SEG. SIZE & UTILISATION REG */
19970  FR_MBSSUTR_16B_tag MBSSUTR; /* offset: 0x000E size: 16 bit */
19971  union {
19972  /* PE DRAM ACCESS REGISTER */
19973  FR_PEDRAR_16B_tag PEDRAR; /* offset: 0x0010 size: 16 bit */
19974 
19975  FR_PEDRAR_16B_tag PADR; /* deprecated - please avoid */
19976 
19977  };
19978  union {
19979  /* PE DRAM DATA REGISTER */
19980  FR_PEDRDR_16B_tag PEDRDR; /* offset: 0x0012 size: 16 bit */
19981 
19982  FR_PEDRDR_16B_tag PDAR; /* deprecated - please avoid */
19983 
19984  };
19985  /* PROTOCOL OPERATION CONTROL REG */
19986  FR_POCR_16B_tag POCR; /* offset: 0x0014 size: 16 bit */
19987  /* GLOBAL INTERRUPT FLAG & ENABLE REG */
19988  FR_GIFER_16B_tag GIFER; /* offset: 0x0016 size: 16 bit */
19989  /* PROTOCOL INTERRUPT FLAG REGISTER 0 */
19990  FR_PIFR0_16B_tag PIFR0; /* offset: 0x0018 size: 16 bit */
19991  /* PROTOCOL INTERRUPT FLAG REGISTER 1 */
19992  FR_PIFR1_16B_tag PIFR1; /* offset: 0x001A size: 16 bit */
19993  /* PROTOCOL INTERRUPT ENABLE REGISTER 0 */
19994  FR_PIER0_16B_tag PIER0; /* offset: 0x001C size: 16 bit */
19995  /* PROTOCOL INTERRUPT ENABLE REGISTER 1 */
19996  FR_PIER1_16B_tag PIER1; /* offset: 0x001E size: 16 bit */
19997  /* CHI ERROR FLAG REGISTER */
19998  FR_CHIERFR_16B_tag CHIERFR; /* offset: 0x0020 size: 16 bit */
19999  /* Message Buffer Interrupt Vector Register */
20000  FR_MBIVEC_16B_tag MBIVEC; /* offset: 0x0022 size: 16 bit */
20001  /* Channel A Status Error Counter Register */
20002  FR_CASERCR_16B_tag CASERCR; /* offset: 0x0024 size: 16 bit */
20003  /* Channel B Status Error Counter Register */
20004  FR_CBSERCR_16B_tag CBSERCR; /* offset: 0x0026 size: 16 bit */
20005  /* Protocol Status Register 0 */
20006  FR_PSR0_16B_tag PSR0; /* offset: 0x0028 size: 16 bit */
20007  /* Protocol Status Register 1 */
20008  FR_PSR1_16B_tag PSR1; /* offset: 0x002A size: 16 bit */
20009  /* Protocol Status Register 2 */
20010  FR_PSR2_16B_tag PSR2; /* offset: 0x002C size: 16 bit */
20011  /* Protocol Status Register 3 */
20012  FR_PSR3_16B_tag PSR3; /* offset: 0x002E size: 16 bit */
20013  /* Macrotick Counter Register */
20014  FR_MTCTR_16B_tag MTCTR; /* offset: 0x0030 size: 16 bit */
20015  /* Cycle Counter Register */
20016  FR_CYCTR_16B_tag CYCTR; /* offset: 0x0032 size: 16 bit */
20017  /* Slot Counter Channel A Register */
20018  FR_SLTCTAR_16B_tag SLTCTAR; /* offset: 0x0034 size: 16 bit */
20019  /* Slot Counter Channel B Register */
20020  FR_SLTCTBR_16B_tag SLTCTBR; /* offset: 0x0036 size: 16 bit */
20021  /* Rate Correction Value Register */
20022  FR_RTCORVR_16B_tag RTCORVR; /* offset: 0x0038 size: 16 bit */
20023  /* Offset Correction Value Register */
20024  FR_OFCORVR_16B_tag OFCORVR; /* offset: 0x003A size: 16 bit */
20025  union {
20026  FR_CIFR_16B_tag CIFRR; /* deprecated - please avoid */
20027 
20028  /* Combined Interrupt Flag Register */
20029  FR_CIFR_16B_tag CIFR; /* offset: 0x003C size: 16 bit */
20030 
20031  };
20032  /* System Memory Access Time-Out Register */
20033  FR_SYMATOR_16B_tag SYMATOR; /* offset: 0x003E size: 16 bit */
20034  /* Sync Frame Counter Register */
20035  FR_SFCNTR_16B_tag SFCNTR; /* offset: 0x0040 size: 16 bit */
20036  /* Sync Frame Table Offset Register */
20037  FR_SFTOR_16B_tag SFTOR; /* offset: 0x0042 size: 16 bit */
20038  /* Sync Frame Table Configuration, Control, Status Register */
20039  FR_SFTCCSR_16B_tag SFTCCSR; /* offset: 0x0044 size: 16 bit */
20040  /* Sync Frame ID Rejection Filter */
20041  FR_SFIDRFR_16B_tag SFIDRFR; /* offset: 0x0046 size: 16 bit */
20042  /* Sync Frame ID Acceptance Filter Value Register */
20043  FR_SFIDAFVR_16B_tag SFIDAFVR; /* offset: 0x0048 size: 16 bit */
20044  /* Sync Frame ID Acceptance Filter Mask Register */
20045  FR_SFIDAFMR_16B_tag SFIDAFMR; /* offset: 0x004A size: 16 bit */
20046  union {
20047  FR_NMVR_16B_tag NMVR[6]; /* offset: 0x004C (0x0002 x 6) */
20048 
20049  struct {
20050  /* Network Management Vector Register0 */
20051  FR_NMVR0_16B_tag NMVR0; /* offset: 0x004C size: 16 bit */
20052  /* Network Management Vector Register1 */
20053  FR_NMVR1_16B_tag NMVR1; /* offset: 0x004E size: 16 bit */
20054  /* Network Management Vector Register2 */
20055  FR_NMVR2_16B_tag NMVR2; /* offset: 0x0050 size: 16 bit */
20056  /* Network Management Vector Register3 */
20057  FR_NMVR3_16B_tag NMVR3; /* offset: 0x0052 size: 16 bit */
20058  /* Network Management Vector Register4 */
20059  FR_NMVR4_16B_tag NMVR4; /* offset: 0x0054 size: 16 bit */
20060  /* Network Management Vector Register5 */
20061  FR_NMVR5_16B_tag NMVR5; /* offset: 0x0056 size: 16 bit */
20062  };
20063 
20064  };
20065  /* Network Management Vector Length Register */
20066  FR_NMVLR_16B_tag NMVLR; /* offset: 0x0058 size: 16 bit */
20067  /* Timer Configuration and Control Register */
20068  FR_TICCR_16B_tag TICCR; /* offset: 0x005A size: 16 bit */
20069  /* Timer 1 Cycle Set Register */
20070  FR_TI1CYSR_16B_tag TI1CYSR; /* offset: 0x005C size: 16 bit */
20071  union {
20072  /* Timer 1 Macrotick Offset Register */
20073  FR_TI1MTOR_16B_tag TI1MTOR; /* offset: 0x005E size: 16 bit */
20074 
20075  FR_TI1MTOR_16B_tag T1MTOR; /* deprecated - please avoid */
20076 
20077  };
20078  /* Timer 2 Configuration Register 0 */
20079  FR_TI2CR0_16B_tag TI2CR0; /* offset: 0x0060 size: 16 bit */
20080  /* Timer 2 Configuration Register 1 */
20081  FR_TI2CR1_16B_tag TI2CR1; /* offset: 0x0062 size: 16 bit */
20082  /* Slot Status Selection Register */
20083  FR_SSSR_16B_tag SSSR; /* offset: 0x0064 size: 16 bit */
20084  /* Slot Status Counter Condition Register */
20085  FR_SSCCR_16B_tag SSCCR; /* offset: 0x0066 size: 16 bit */
20086  union {
20087  FR_SSR_16B_tag SSR[8]; /* offset: 0x0068 (0x0002 x 8) */
20088 
20089  struct {
20090  /* Slot Status Register0 */
20091  FR_SSR_16B_tag SSR0; /* offset: 0x0068 size: 16 bit */
20092  /* Slot Status Register1 */
20093  FR_SSR_16B_tag SSR1; /* offset: 0x006A size: 16 bit */
20094  /* Slot Status Register2 */
20095  FR_SSR_16B_tag SSR2; /* offset: 0x006C size: 16 bit */
20096  /* Slot Status Register3 */
20097  FR_SSR_16B_tag SSR3; /* offset: 0x006E size: 16 bit */
20098  /* Slot Status Register4 */
20099  FR_SSR_16B_tag SSR4; /* offset: 0x0070 size: 16 bit */
20100  /* Slot Status Register5 */
20101  FR_SSR_16B_tag SSR5; /* offset: 0x0072 size: 16 bit */
20102  /* Slot Status Register6 */
20103  FR_SSR_16B_tag SSR6; /* offset: 0x0074 size: 16 bit */
20104  /* Slot Status Register7 */
20105  FR_SSR_16B_tag SSR7; /* offset: 0x0076 size: 16 bit */
20106  };
20107 
20108  };
20109  union {
20110  FR_SSCR_16B_tag SSCR[4]; /* offset: 0x0078 (0x0002 x 4) */
20111 
20112  struct {
20113  /* Slot Status Counter Register0 */
20114  FR_SSCR0_16B_tag SSCR0; /* offset: 0x0078 size: 16 bit */
20115  /* Slot Status Counter Register1 */
20116  FR_SSCR1_16B_tag SSCR1; /* offset: 0x007A size: 16 bit */
20117  /* Slot Status Counter Register2 */
20118  FR_SSCR2_16B_tag SSCR2; /* offset: 0x007C size: 16 bit */
20119  /* Slot Status Counter Register3 */
20120  FR_SSCR3_16B_tag SSCR3; /* offset: 0x007E size: 16 bit */
20121  };
20122 
20123  };
20124  /* MTS A Configuration Register */
20125  FR_MTSACFR_16B_tag MTSACFR; /* offset: 0x0080 size: 16 bit */
20126  /* MTS B Configuration Register */
20127  FR_MTSBCFR_16B_tag MTSBCFR; /* offset: 0x0082 size: 16 bit */
20128  /* Receive Shadow Buffer Index Register */
20129  FR_RSBIR_16B_tag RSBIR; /* offset: 0x0084 size: 16 bit */
20130  union {
20131  /* Receive FIFO Watermark and Selection Register */
20132  FR_RFWMSR_16B_tag RFWMSR; /* offset: 0x0086 size: 16 bit */
20133 
20134  FR_RFWMSR_16B_tag RFSR; /* deprecated - please avoid */
20135 
20136  };
20137  union {
20138  FR_RF_RFSIR_16B_tag RFSIR; /* deprecated - please avoid */
20139 
20140  /* Receive FIFO Start Index Register */
20141  FR_RF_RFSIR_16B_tag RF_RFSIR; /* offset: 0x0088 size: 16 bit */
20142 
20143  };
20144  /* Receive FIFO Depth and Size Register */
20145  FR_RFDSR_16B_tag RFDSR; /* offset: 0x008A size: 16 bit */
20146  /* Receive FIFO A Read Index Register */
20147  FR_RFARIR_16B_tag RFARIR; /* offset: 0x008C size: 16 bit */
20148  /* Receive FIFO B Read Index Register */
20149  FR_RFBRIR_16B_tag RFBRIR; /* offset: 0x008E size: 16 bit */
20150  /* Receive FIFO Message ID Acceptance Filter Value Register */
20151  FR_RFMIDAFVR_16B_tag RFMIDAFVR; /* offset: 0x0090 size: 16 bit */
20152  union {
20153  /* Receive FIFO Message ID Acceptance Filter Mask Register */
20154  FR_RFMIDAFMR_16B_tag RFMIDAFMR; /* offset: 0x0092 size: 16 bit */
20155 
20156  FR_RFMIDAFMR_16B_tag RFMIAFMR; /* deprecated - please avoid */
20157 
20158  };
20159  /* Receive FIFO Frame ID Rejection Filter Value Register */
20160  FR_RFFIDRFVR_16B_tag RFFIDRFVR; /* offset: 0x0094 size: 16 bit */
20161  /* Receive FIFO Frame ID Rejection Filter Mask Register */
20162  FR_RFFIDRFMR_16B_tag RFFIDRFMR; /* offset: 0x0096 size: 16 bit */
20163  /* Receive FIFO Range Filter Configuration Register */
20164  FR_RFRFCFR_16B_tag RFRFCFR; /* offset: 0x0098 size: 16 bit */
20165  /* Receive FIFO Range Filter Control Register */
20166  FR_RFRFCTR_16B_tag RFRFCTR; /* offset: 0x009A size: 16 bit */
20167  /* Last Dynamic Transmit Slot Channel A Register */
20168  FR_LDTXSLAR_16B_tag LDTXSLAR; /* offset: 0x009C size: 16 bit */
20169  /* Last Dynamic Transmit Slot Channel B Register */
20170  FR_LDTXSLBR_16B_tag LDTXSLBR; /* offset: 0x009E size: 16 bit */
20171  /* Protocol Configuration Register 0 */
20172  FR_PCR0_16B_tag PCR0; /* offset: 0x00A0 size: 16 bit */
20173  /* Protocol Configuration Register 1 */
20174  FR_PCR1_16B_tag PCR1; /* offset: 0x00A2 size: 16 bit */
20175  /* Protocol Configuration Register 2 */
20176  FR_PCR2_16B_tag PCR2; /* offset: 0x00A4 size: 16 bit */
20177  /* Protocol Configuration Register 3 */
20178  FR_PCR3_16B_tag PCR3; /* offset: 0x00A6 size: 16 bit */
20179  /* Protocol Configuration Register 4 */
20180  FR_PCR4_16B_tag PCR4; /* offset: 0x00A8 size: 16 bit */
20181  /* Protocol Configuration Register 5 */
20182  FR_PCR5_16B_tag PCR5; /* offset: 0x00AA size: 16 bit */
20183  /* Protocol Configuration Register 6 */
20184  FR_PCR6_16B_tag PCR6; /* offset: 0x00AC size: 16 bit */
20185  /* Protocol Configuration Register 7 */
20186  FR_PCR7_16B_tag PCR7; /* offset: 0x00AE size: 16 bit */
20187  /* Protocol Configuration Register 8 */
20188  FR_PCR8_16B_tag PCR8; /* offset: 0x00B0 size: 16 bit */
20189  /* Protocol Configuration Register 9 */
20190  FR_PCR9_16B_tag PCR9; /* offset: 0x00B2 size: 16 bit */
20191  /* Protocol Configuration Register 10 */
20192  FR_PCR10_16B_tag PCR10; /* offset: 0x00B4 size: 16 bit */
20193  /* Protocol Configuration Register 11 */
20194  FR_PCR11_16B_tag PCR11; /* offset: 0x00B6 size: 16 bit */
20195  /* Protocol Configuration Register 12 */
20196  FR_PCR12_16B_tag PCR12; /* offset: 0x00B8 size: 16 bit */
20197  /* Protocol Configuration Register 13 */
20198  FR_PCR13_16B_tag PCR13; /* offset: 0x00BA size: 16 bit */
20199  /* Protocol Configuration Register 14 */
20200  FR_PCR14_16B_tag PCR14; /* offset: 0x00BC size: 16 bit */
20201  /* Protocol Configuration Register 15 */
20202  FR_PCR15_16B_tag PCR15; /* offset: 0x00BE size: 16 bit */
20203  /* Protocol Configuration Register 16 */
20204  FR_PCR16_16B_tag PCR16; /* offset: 0x00C0 size: 16 bit */
20205  /* Protocol Configuration Register 17 */
20206  FR_PCR17_16B_tag PCR17; /* offset: 0x00C2 size: 16 bit */
20207  /* Protocol Configuration Register 18 */
20208  FR_PCR18_16B_tag PCR18; /* offset: 0x00C4 size: 16 bit */
20209  /* Protocol Configuration Register 19 */
20210  FR_PCR19_16B_tag PCR19; /* offset: 0x00C6 size: 16 bit */
20211  /* Protocol Configuration Register 20 */
20212  FR_PCR20_16B_tag PCR20; /* offset: 0x00C8 size: 16 bit */
20213  /* Protocol Configuration Register 21 */
20214  FR_PCR21_16B_tag PCR21; /* offset: 0x00CA size: 16 bit */
20215  /* Protocol Configuration Register 22 */
20216  FR_PCR22_16B_tag PCR22; /* offset: 0x00CC size: 16 bit */
20217  /* Protocol Configuration Register 23 */
20218  FR_PCR23_16B_tag PCR23; /* offset: 0x00CE size: 16 bit */
20219  /* Protocol Configuration Register 24 */
20220  FR_PCR24_16B_tag PCR24; /* offset: 0x00D0 size: 16 bit */
20221  /* Protocol Configuration Register 25 */
20222  FR_PCR25_16B_tag PCR25; /* offset: 0x00D2 size: 16 bit */
20223  /* Protocol Configuration Register 26 */
20224  FR_PCR26_16B_tag PCR26; /* offset: 0x00D4 size: 16 bit */
20225  /* Protocol Configuration Register 27 */
20226  FR_PCR27_16B_tag PCR27; /* offset: 0x00D6 size: 16 bit */
20227  /* Protocol Configuration Register 28 */
20228  FR_PCR28_16B_tag PCR28; /* offset: 0x00D8 size: 16 bit */
20229  /* Protocol Configuration Register 29 */
20230  FR_PCR29_16B_tag PCR29; /* offset: 0x00DA size: 16 bit */
20231  /* Protocol Configuration Register 30 */
20232  FR_PCR30_16B_tag PCR30; /* offset: 0x00DC size: 16 bit */
20233  int8_t FR_reserved_00DE[10];
20234  /* Receive FIFO System Memory Base Address High Register */
20235  FR_RFSYMBHADR_16B_tag RFSYMBHADR; /* offset: 0x00E8 size: 16 bit */
20236  /* Receive FIFO System Memory Base Address Low Register */
20237  FR_RFSYMBLADR_16B_tag RFSYMBLADR; /* offset: 0x00EA size: 16 bit */
20238  /* Receive FIFO Periodic Timer Register */
20239  FR_RFPTR_16B_tag RFPTR; /* offset: 0x00EC size: 16 bit */
20240  /* Receive FIFO Fill Level and Pop Count Register */
20241  FR_RFFLPCR_16B_tag RFFLPCR; /* offset: 0x00EE size: 16 bit */
20242  /* ECC Error Interrupt Flag and Enable Register */
20243  FR_EEIFER_16B_tag EEIFER; /* offset: 0x00F0 size: 16 bit */
20244  /* ECC Error Report and Injection Control Register */
20245  FR_EERICR_16B_tag EERICR; /* offset: 0x00F2 size: 16 bit */
20246  /* ECC Error Report Adress Register */
20247  FR_EERAR_16B_tag EERAR; /* offset: 0x00F4 size: 16 bit */
20248  /* ECC Error Report Data Register */
20249  FR_EERDR_16B_tag EERDR; /* offset: 0x00F6 size: 16 bit */
20250  /* ECC Error Report Code Register */
20251  FR_EERCR_16B_tag EERCR; /* offset: 0x00F8 size: 16 bit */
20252  /* ECC Error Injection Address Register */
20253  FR_EEIAR_16B_tag EEIAR; /* offset: 0x00FA size: 16 bit */
20254  /* ECC Error Injection Data Register */
20255  FR_EEIDR_16B_tag EEIDR; /* offset: 0x00FC size: 16 bit */
20256  /* ECC Error Injection Code Register */
20257  FR_EEICR_16B_tag EEICR; /* offset: 0x00FE size: 16 bit */
20258  union {
20259  /* Register set MB */
20260  FR_MB_tag MB[64]; /* offset: 0x0100 (0x0008 x 64) */
20261 
20262  struct {
20263  /* Message Buffer Configuration Control Status Register */
20264  FR_MBCCSR_16B_tag MBCCSR0; /* offset: 0x0100 size: 16 bit */
20265  /* Message Buffer Cycle Counter Filter Register */
20266  FR_MBCCFR_16B_tag MBCCFR0; /* offset: 0x0102 size: 16 bit */
20267  /* Message Buffer Frame ID Register */
20268  FR_MBFIDR_16B_tag MBFIDR0; /* offset: 0x0104 size: 16 bit */
20269  /* Message Buffer Index Register */
20270  FR_MBIDXR_16B_tag MBIDXR0; /* offset: 0x0106 size: 16 bit */
20271  /* Message Buffer Configuration Control Status Register */
20272  FR_MBCCSR_16B_tag MBCCSR1; /* offset: 0x0108 size: 16 bit */
20273  /* Message Buffer Cycle Counter Filter Register */
20274  FR_MBCCFR_16B_tag MBCCFR1; /* offset: 0x010A size: 16 bit */
20275  /* Message Buffer Frame ID Register */
20276  FR_MBFIDR_16B_tag MBFIDR1; /* offset: 0x010C size: 16 bit */
20277  /* Message Buffer Index Register */
20278  FR_MBIDXR_16B_tag MBIDXR1; /* offset: 0x010E size: 16 bit */
20279  /* Message Buffer Configuration Control Status Register */
20280  FR_MBCCSR_16B_tag MBCCSR2; /* offset: 0x0110 size: 16 bit */
20281  /* Message Buffer Cycle Counter Filter Register */
20282  FR_MBCCFR_16B_tag MBCCFR2; /* offset: 0x0112 size: 16 bit */
20283  /* Message Buffer Frame ID Register */
20284  FR_MBFIDR_16B_tag MBFIDR2; /* offset: 0x0114 size: 16 bit */
20285  /* Message Buffer Index Register */
20286  FR_MBIDXR_16B_tag MBIDXR2; /* offset: 0x0116 size: 16 bit */
20287  /* Message Buffer Configuration Control Status Register */
20288  FR_MBCCSR_16B_tag MBCCSR3; /* offset: 0x0118 size: 16 bit */
20289  /* Message Buffer Cycle Counter Filter Register */
20290  FR_MBCCFR_16B_tag MBCCFR3; /* offset: 0x011A size: 16 bit */
20291  /* Message Buffer Frame ID Register */
20292  FR_MBFIDR_16B_tag MBFIDR3; /* offset: 0x011C size: 16 bit */
20293  /* Message Buffer Index Register */
20294  FR_MBIDXR_16B_tag MBIDXR3; /* offset: 0x011E size: 16 bit */
20295  /* Message Buffer Configuration Control Status Register */
20296  FR_MBCCSR_16B_tag MBCCSR4; /* offset: 0x0120 size: 16 bit */
20297  /* Message Buffer Cycle Counter Filter Register */
20298  FR_MBCCFR_16B_tag MBCCFR4; /* offset: 0x0122 size: 16 bit */
20299  /* Message Buffer Frame ID Register */
20300  FR_MBFIDR_16B_tag MBFIDR4; /* offset: 0x0124 size: 16 bit */
20301  /* Message Buffer Index Register */
20302  FR_MBIDXR_16B_tag MBIDXR4; /* offset: 0x0126 size: 16 bit */
20303  /* Message Buffer Configuration Control Status Register */
20304  FR_MBCCSR_16B_tag MBCCSR5; /* offset: 0x0128 size: 16 bit */
20305  /* Message Buffer Cycle Counter Filter Register */
20306  FR_MBCCFR_16B_tag MBCCFR5; /* offset: 0x012A size: 16 bit */
20307  /* Message Buffer Frame ID Register */
20308  FR_MBFIDR_16B_tag MBFIDR5; /* offset: 0x012C size: 16 bit */
20309  /* Message Buffer Index Register */
20310  FR_MBIDXR_16B_tag MBIDXR5; /* offset: 0x012E size: 16 bit */
20311  /* Message Buffer Configuration Control Status Register */
20312  FR_MBCCSR_16B_tag MBCCSR6; /* offset: 0x0130 size: 16 bit */
20313  /* Message Buffer Cycle Counter Filter Register */
20314  FR_MBCCFR_16B_tag MBCCFR6; /* offset: 0x0132 size: 16 bit */
20315  /* Message Buffer Frame ID Register */
20316  FR_MBFIDR_16B_tag MBFIDR6; /* offset: 0x0134 size: 16 bit */
20317  /* Message Buffer Index Register */
20318  FR_MBIDXR_16B_tag MBIDXR6; /* offset: 0x0136 size: 16 bit */
20319  /* Message Buffer Configuration Control Status Register */
20320  FR_MBCCSR_16B_tag MBCCSR7; /* offset: 0x0138 size: 16 bit */
20321  /* Message Buffer Cycle Counter Filter Register */
20322  FR_MBCCFR_16B_tag MBCCFR7; /* offset: 0x013A size: 16 bit */
20323  /* Message Buffer Frame ID Register */
20324  FR_MBFIDR_16B_tag MBFIDR7; /* offset: 0x013C size: 16 bit */
20325  /* Message Buffer Index Register */
20326  FR_MBIDXR_16B_tag MBIDXR7; /* offset: 0x013E size: 16 bit */
20327  /* Message Buffer Configuration Control Status Register */
20328  FR_MBCCSR_16B_tag MBCCSR8; /* offset: 0x0140 size: 16 bit */
20329  /* Message Buffer Cycle Counter Filter Register */
20330  FR_MBCCFR_16B_tag MBCCFR8; /* offset: 0x0142 size: 16 bit */
20331  /* Message Buffer Frame ID Register */
20332  FR_MBFIDR_16B_tag MBFIDR8; /* offset: 0x0144 size: 16 bit */
20333  /* Message Buffer Index Register */
20334  FR_MBIDXR_16B_tag MBIDXR8; /* offset: 0x0146 size: 16 bit */
20335  /* Message Buffer Configuration Control Status Register */
20336  FR_MBCCSR_16B_tag MBCCSR9; /* offset: 0x0148 size: 16 bit */
20337  /* Message Buffer Cycle Counter Filter Register */
20338  FR_MBCCFR_16B_tag MBCCFR9; /* offset: 0x014A size: 16 bit */
20339  /* Message Buffer Frame ID Register */
20340  FR_MBFIDR_16B_tag MBFIDR9; /* offset: 0x014C size: 16 bit */
20341  /* Message Buffer Index Register */
20342  FR_MBIDXR_16B_tag MBIDXR9; /* offset: 0x014E size: 16 bit */
20343  /* Message Buffer Configuration Control Status Register */
20344  FR_MBCCSR_16B_tag MBCCSR10; /* offset: 0x0150 size: 16 bit */
20345  /* Message Buffer Cycle Counter Filter Register */
20346  FR_MBCCFR_16B_tag MBCCFR10; /* offset: 0x0152 size: 16 bit */
20347  /* Message Buffer Frame ID Register */
20348  FR_MBFIDR_16B_tag MBFIDR10; /* offset: 0x0154 size: 16 bit */
20349  /* Message Buffer Index Register */
20350  FR_MBIDXR_16B_tag MBIDXR10; /* offset: 0x0156 size: 16 bit */
20351  /* Message Buffer Configuration Control Status Register */
20352  FR_MBCCSR_16B_tag MBCCSR11; /* offset: 0x0158 size: 16 bit */
20353  /* Message Buffer Cycle Counter Filter Register */
20354  FR_MBCCFR_16B_tag MBCCFR11; /* offset: 0x015A size: 16 bit */
20355  /* Message Buffer Frame ID Register */
20356  FR_MBFIDR_16B_tag MBFIDR11; /* offset: 0x015C size: 16 bit */
20357  /* Message Buffer Index Register */
20358  FR_MBIDXR_16B_tag MBIDXR11; /* offset: 0x015E size: 16 bit */
20359  /* Message Buffer Configuration Control Status Register */
20360  FR_MBCCSR_16B_tag MBCCSR12; /* offset: 0x0160 size: 16 bit */
20361  /* Message Buffer Cycle Counter Filter Register */
20362  FR_MBCCFR_16B_tag MBCCFR12; /* offset: 0x0162 size: 16 bit */
20363  /* Message Buffer Frame ID Register */
20364  FR_MBFIDR_16B_tag MBFIDR12; /* offset: 0x0164 size: 16 bit */
20365  /* Message Buffer Index Register */
20366  FR_MBIDXR_16B_tag MBIDXR12; /* offset: 0x0166 size: 16 bit */
20367  /* Message Buffer Configuration Control Status Register */
20368  FR_MBCCSR_16B_tag MBCCSR13; /* offset: 0x0168 size: 16 bit */
20369  /* Message Buffer Cycle Counter Filter Register */
20370  FR_MBCCFR_16B_tag MBCCFR13; /* offset: 0x016A size: 16 bit */
20371  /* Message Buffer Frame ID Register */
20372  FR_MBFIDR_16B_tag MBFIDR13; /* offset: 0x016C size: 16 bit */
20373  /* Message Buffer Index Register */
20374  FR_MBIDXR_16B_tag MBIDXR13; /* offset: 0x016E size: 16 bit */
20375  /* Message Buffer Configuration Control Status Register */
20376  FR_MBCCSR_16B_tag MBCCSR14; /* offset: 0x0170 size: 16 bit */
20377  /* Message Buffer Cycle Counter Filter Register */
20378  FR_MBCCFR_16B_tag MBCCFR14; /* offset: 0x0172 size: 16 bit */
20379  /* Message Buffer Frame ID Register */
20380  FR_MBFIDR_16B_tag MBFIDR14; /* offset: 0x0174 size: 16 bit */
20381  /* Message Buffer Index Register */
20382  FR_MBIDXR_16B_tag MBIDXR14; /* offset: 0x0176 size: 16 bit */
20383  /* Message Buffer Configuration Control Status Register */
20384  FR_MBCCSR_16B_tag MBCCSR15; /* offset: 0x0178 size: 16 bit */
20385  /* Message Buffer Cycle Counter Filter Register */
20386  FR_MBCCFR_16B_tag MBCCFR15; /* offset: 0x017A size: 16 bit */
20387  /* Message Buffer Frame ID Register */
20388  FR_MBFIDR_16B_tag MBFIDR15; /* offset: 0x017C size: 16 bit */
20389  /* Message Buffer Index Register */
20390  FR_MBIDXR_16B_tag MBIDXR15; /* offset: 0x017E size: 16 bit */
20391  /* Message Buffer Configuration Control Status Register */
20392  FR_MBCCSR_16B_tag MBCCSR16; /* offset: 0x0180 size: 16 bit */
20393  /* Message Buffer Cycle Counter Filter Register */
20394  FR_MBCCFR_16B_tag MBCCFR16; /* offset: 0x0182 size: 16 bit */
20395  /* Message Buffer Frame ID Register */
20396  FR_MBFIDR_16B_tag MBFIDR16; /* offset: 0x0184 size: 16 bit */
20397  /* Message Buffer Index Register */
20398  FR_MBIDXR_16B_tag MBIDXR16; /* offset: 0x0186 size: 16 bit */
20399  /* Message Buffer Configuration Control Status Register */
20400  FR_MBCCSR_16B_tag MBCCSR17; /* offset: 0x0188 size: 16 bit */
20401  /* Message Buffer Cycle Counter Filter Register */
20402  FR_MBCCFR_16B_tag MBCCFR17; /* offset: 0x018A size: 16 bit */
20403  /* Message Buffer Frame ID Register */
20404  FR_MBFIDR_16B_tag MBFIDR17; /* offset: 0x018C size: 16 bit */
20405  /* Message Buffer Index Register */
20406  FR_MBIDXR_16B_tag MBIDXR17; /* offset: 0x018E size: 16 bit */
20407  /* Message Buffer Configuration Control Status Register */
20408  FR_MBCCSR_16B_tag MBCCSR18; /* offset: 0x0190 size: 16 bit */
20409  /* Message Buffer Cycle Counter Filter Register */
20410  FR_MBCCFR_16B_tag MBCCFR18; /* offset: 0x0192 size: 16 bit */
20411  /* Message Buffer Frame ID Register */
20412  FR_MBFIDR_16B_tag MBFIDR18; /* offset: 0x0194 size: 16 bit */
20413  /* Message Buffer Index Register */
20414  FR_MBIDXR_16B_tag MBIDXR18; /* offset: 0x0196 size: 16 bit */
20415  /* Message Buffer Configuration Control Status Register */
20416  FR_MBCCSR_16B_tag MBCCSR19; /* offset: 0x0198 size: 16 bit */
20417  /* Message Buffer Cycle Counter Filter Register */
20418  FR_MBCCFR_16B_tag MBCCFR19; /* offset: 0x019A size: 16 bit */
20419  /* Message Buffer Frame ID Register */
20420  FR_MBFIDR_16B_tag MBFIDR19; /* offset: 0x019C size: 16 bit */
20421  /* Message Buffer Index Register */
20422  FR_MBIDXR_16B_tag MBIDXR19; /* offset: 0x019E size: 16 bit */
20423  /* Message Buffer Configuration Control Status Register */
20424  FR_MBCCSR_16B_tag MBCCSR20; /* offset: 0x01A0 size: 16 bit */
20425  /* Message Buffer Cycle Counter Filter Register */
20426  FR_MBCCFR_16B_tag MBCCFR20; /* offset: 0x01A2 size: 16 bit */
20427  /* Message Buffer Frame ID Register */
20428  FR_MBFIDR_16B_tag MBFIDR20; /* offset: 0x01A4 size: 16 bit */
20429  /* Message Buffer Index Register */
20430  FR_MBIDXR_16B_tag MBIDXR20; /* offset: 0x01A6 size: 16 bit */
20431  /* Message Buffer Configuration Control Status Register */
20432  FR_MBCCSR_16B_tag MBCCSR21; /* offset: 0x01A8 size: 16 bit */
20433  /* Message Buffer Cycle Counter Filter Register */
20434  FR_MBCCFR_16B_tag MBCCFR21; /* offset: 0x01AA size: 16 bit */
20435  /* Message Buffer Frame ID Register */
20436  FR_MBFIDR_16B_tag MBFIDR21; /* offset: 0x01AC size: 16 bit */
20437  /* Message Buffer Index Register */
20438  FR_MBIDXR_16B_tag MBIDXR21; /* offset: 0x01AE size: 16 bit */
20439  /* Message Buffer Configuration Control Status Register */
20440  FR_MBCCSR_16B_tag MBCCSR22; /* offset: 0x01B0 size: 16 bit */
20441  /* Message Buffer Cycle Counter Filter Register */
20442  FR_MBCCFR_16B_tag MBCCFR22; /* offset: 0x01B2 size: 16 bit */
20443  /* Message Buffer Frame ID Register */
20444  FR_MBFIDR_16B_tag MBFIDR22; /* offset: 0x01B4 size: 16 bit */
20445  /* Message Buffer Index Register */
20446  FR_MBIDXR_16B_tag MBIDXR22; /* offset: 0x01B6 size: 16 bit */
20447  /* Message Buffer Configuration Control Status Register */
20448  FR_MBCCSR_16B_tag MBCCSR23; /* offset: 0x01B8 size: 16 bit */
20449  /* Message Buffer Cycle Counter Filter Register */
20450  FR_MBCCFR_16B_tag MBCCFR23; /* offset: 0x01BA size: 16 bit */
20451  /* Message Buffer Frame ID Register */
20452  FR_MBFIDR_16B_tag MBFIDR23; /* offset: 0x01BC size: 16 bit */
20453  /* Message Buffer Index Register */
20454  FR_MBIDXR_16B_tag MBIDXR23; /* offset: 0x01BE size: 16 bit */
20455  /* Message Buffer Configuration Control Status Register */
20456  FR_MBCCSR_16B_tag MBCCSR24; /* offset: 0x01C0 size: 16 bit */
20457  /* Message Buffer Cycle Counter Filter Register */
20458  FR_MBCCFR_16B_tag MBCCFR24; /* offset: 0x01C2 size: 16 bit */
20459  /* Message Buffer Frame ID Register */
20460  FR_MBFIDR_16B_tag MBFIDR24; /* offset: 0x01C4 size: 16 bit */
20461  /* Message Buffer Index Register */
20462  FR_MBIDXR_16B_tag MBIDXR24; /* offset: 0x01C6 size: 16 bit */
20463  /* Message Buffer Configuration Control Status Register */
20464  FR_MBCCSR_16B_tag MBCCSR25; /* offset: 0x01C8 size: 16 bit */
20465  /* Message Buffer Cycle Counter Filter Register */
20466  FR_MBCCFR_16B_tag MBCCFR25; /* offset: 0x01CA size: 16 bit */
20467  /* Message Buffer Frame ID Register */
20468  FR_MBFIDR_16B_tag MBFIDR25; /* offset: 0x01CC size: 16 bit */
20469  /* Message Buffer Index Register */
20470  FR_MBIDXR_16B_tag MBIDXR25; /* offset: 0x01CE size: 16 bit */
20471  /* Message Buffer Configuration Control Status Register */
20472  FR_MBCCSR_16B_tag MBCCSR26; /* offset: 0x01D0 size: 16 bit */
20473  /* Message Buffer Cycle Counter Filter Register */
20474  FR_MBCCFR_16B_tag MBCCFR26; /* offset: 0x01D2 size: 16 bit */
20475  /* Message Buffer Frame ID Register */
20476  FR_MBFIDR_16B_tag MBFIDR26; /* offset: 0x01D4 size: 16 bit */
20477  /* Message Buffer Index Register */
20478  FR_MBIDXR_16B_tag MBIDXR26; /* offset: 0x01D6 size: 16 bit */
20479  /* Message Buffer Configuration Control Status Register */
20480  FR_MBCCSR_16B_tag MBCCSR27; /* offset: 0x01D8 size: 16 bit */
20481  /* Message Buffer Cycle Counter Filter Register */
20482  FR_MBCCFR_16B_tag MBCCFR27; /* offset: 0x01DA size: 16 bit */
20483  /* Message Buffer Frame ID Register */
20484  FR_MBFIDR_16B_tag MBFIDR27; /* offset: 0x01DC size: 16 bit */
20485  /* Message Buffer Index Register */
20486  FR_MBIDXR_16B_tag MBIDXR27; /* offset: 0x01DE size: 16 bit */
20487  /* Message Buffer Configuration Control Status Register */
20488  FR_MBCCSR_16B_tag MBCCSR28; /* offset: 0x01E0 size: 16 bit */
20489  /* Message Buffer Cycle Counter Filter Register */
20490  FR_MBCCFR_16B_tag MBCCFR28; /* offset: 0x01E2 size: 16 bit */
20491  /* Message Buffer Frame ID Register */
20492  FR_MBFIDR_16B_tag MBFIDR28; /* offset: 0x01E4 size: 16 bit */
20493  /* Message Buffer Index Register */
20494  FR_MBIDXR_16B_tag MBIDXR28; /* offset: 0x01E6 size: 16 bit */
20495  /* Message Buffer Configuration Control Status Register */
20496  FR_MBCCSR_16B_tag MBCCSR29; /* offset: 0x01E8 size: 16 bit */
20497  /* Message Buffer Cycle Counter Filter Register */
20498  FR_MBCCFR_16B_tag MBCCFR29; /* offset: 0x01EA size: 16 bit */
20499  /* Message Buffer Frame ID Register */
20500  FR_MBFIDR_16B_tag MBFIDR29; /* offset: 0x01EC size: 16 bit */
20501  /* Message Buffer Index Register */
20502  FR_MBIDXR_16B_tag MBIDXR29; /* offset: 0x01EE size: 16 bit */
20503  /* Message Buffer Configuration Control Status Register */
20504  FR_MBCCSR_16B_tag MBCCSR30; /* offset: 0x01F0 size: 16 bit */
20505  /* Message Buffer Cycle Counter Filter Register */
20506  FR_MBCCFR_16B_tag MBCCFR30; /* offset: 0x01F2 size: 16 bit */
20507  /* Message Buffer Frame ID Register */
20508  FR_MBFIDR_16B_tag MBFIDR30; /* offset: 0x01F4 size: 16 bit */
20509  /* Message Buffer Index Register */
20510  FR_MBIDXR_16B_tag MBIDXR30; /* offset: 0x01F6 size: 16 bit */
20511  /* Message Buffer Configuration Control Status Register */
20512  FR_MBCCSR_16B_tag MBCCSR31; /* offset: 0x01F8 size: 16 bit */
20513  /* Message Buffer Cycle Counter Filter Register */
20514  FR_MBCCFR_16B_tag MBCCFR31; /* offset: 0x01FA size: 16 bit */
20515  /* Message Buffer Frame ID Register */
20516  FR_MBFIDR_16B_tag MBFIDR31; /* offset: 0x01FC size: 16 bit */
20517  /* Message Buffer Index Register */
20518  FR_MBIDXR_16B_tag MBIDXR31; /* offset: 0x01FE size: 16 bit */
20519  /* Message Buffer Configuration Control Status Register */
20520  FR_MBCCSR_16B_tag MBCCSR32; /* offset: 0x0200 size: 16 bit */
20521  /* Message Buffer Cycle Counter Filter Register */
20522  FR_MBCCFR_16B_tag MBCCFR32; /* offset: 0x0202 size: 16 bit */
20523  /* Message Buffer Frame ID Register */
20524  FR_MBFIDR_16B_tag MBFIDR32; /* offset: 0x0204 size: 16 bit */
20525  /* Message Buffer Index Register */
20526  FR_MBIDXR_16B_tag MBIDXR32; /* offset: 0x0206 size: 16 bit */
20527  /* Message Buffer Configuration Control Status Register */
20528  FR_MBCCSR_16B_tag MBCCSR33; /* offset: 0x0208 size: 16 bit */
20529  /* Message Buffer Cycle Counter Filter Register */
20530  FR_MBCCFR_16B_tag MBCCFR33; /* offset: 0x020A size: 16 bit */
20531  /* Message Buffer Frame ID Register */
20532  FR_MBFIDR_16B_tag MBFIDR33; /* offset: 0x020C size: 16 bit */
20533  /* Message Buffer Index Register */
20534  FR_MBIDXR_16B_tag MBIDXR33; /* offset: 0x020E size: 16 bit */
20535  /* Message Buffer Configuration Control Status Register */
20536  FR_MBCCSR_16B_tag MBCCSR34; /* offset: 0x0210 size: 16 bit */
20537  /* Message Buffer Cycle Counter Filter Register */
20538  FR_MBCCFR_16B_tag MBCCFR34; /* offset: 0x0212 size: 16 bit */
20539  /* Message Buffer Frame ID Register */
20540  FR_MBFIDR_16B_tag MBFIDR34; /* offset: 0x0214 size: 16 bit */
20541  /* Message Buffer Index Register */
20542  FR_MBIDXR_16B_tag MBIDXR34; /* offset: 0x0216 size: 16 bit */
20543  /* Message Buffer Configuration Control Status Register */
20544  FR_MBCCSR_16B_tag MBCCSR35; /* offset: 0x0218 size: 16 bit */
20545  /* Message Buffer Cycle Counter Filter Register */
20546  FR_MBCCFR_16B_tag MBCCFR35; /* offset: 0x021A size: 16 bit */
20547  /* Message Buffer Frame ID Register */
20548  FR_MBFIDR_16B_tag MBFIDR35; /* offset: 0x021C size: 16 bit */
20549  /* Message Buffer Index Register */
20550  FR_MBIDXR_16B_tag MBIDXR35; /* offset: 0x021E size: 16 bit */
20551  /* Message Buffer Configuration Control Status Register */
20552  FR_MBCCSR_16B_tag MBCCSR36; /* offset: 0x0220 size: 16 bit */
20553  /* Message Buffer Cycle Counter Filter Register */
20554  FR_MBCCFR_16B_tag MBCCFR36; /* offset: 0x0222 size: 16 bit */
20555  /* Message Buffer Frame ID Register */
20556  FR_MBFIDR_16B_tag MBFIDR36; /* offset: 0x0224 size: 16 bit */
20557  /* Message Buffer Index Register */
20558  FR_MBIDXR_16B_tag MBIDXR36; /* offset: 0x0226 size: 16 bit */
20559  /* Message Buffer Configuration Control Status Register */
20560  FR_MBCCSR_16B_tag MBCCSR37; /* offset: 0x0228 size: 16 bit */
20561  /* Message Buffer Cycle Counter Filter Register */
20562  FR_MBCCFR_16B_tag MBCCFR37; /* offset: 0x022A size: 16 bit */
20563  /* Message Buffer Frame ID Register */
20564  FR_MBFIDR_16B_tag MBFIDR37; /* offset: 0x022C size: 16 bit */
20565  /* Message Buffer Index Register */
20566  FR_MBIDXR_16B_tag MBIDXR37; /* offset: 0x022E size: 16 bit */
20567  /* Message Buffer Configuration Control Status Register */
20568  FR_MBCCSR_16B_tag MBCCSR38; /* offset: 0x0230 size: 16 bit */
20569  /* Message Buffer Cycle Counter Filter Register */
20570  FR_MBCCFR_16B_tag MBCCFR38; /* offset: 0x0232 size: 16 bit */
20571  /* Message Buffer Frame ID Register */
20572  FR_MBFIDR_16B_tag MBFIDR38; /* offset: 0x0234 size: 16 bit */
20573  /* Message Buffer Index Register */
20574  FR_MBIDXR_16B_tag MBIDXR38; /* offset: 0x0236 size: 16 bit */
20575  /* Message Buffer Configuration Control Status Register */
20576  FR_MBCCSR_16B_tag MBCCSR39; /* offset: 0x0238 size: 16 bit */
20577  /* Message Buffer Cycle Counter Filter Register */
20578  FR_MBCCFR_16B_tag MBCCFR39; /* offset: 0x023A size: 16 bit */
20579  /* Message Buffer Frame ID Register */
20580  FR_MBFIDR_16B_tag MBFIDR39; /* offset: 0x023C size: 16 bit */
20581  /* Message Buffer Index Register */
20582  FR_MBIDXR_16B_tag MBIDXR39; /* offset: 0x023E size: 16 bit */
20583  /* Message Buffer Configuration Control Status Register */
20584  FR_MBCCSR_16B_tag MBCCSR40; /* offset: 0x0240 size: 16 bit */
20585  /* Message Buffer Cycle Counter Filter Register */
20586  FR_MBCCFR_16B_tag MBCCFR40; /* offset: 0x0242 size: 16 bit */
20587  /* Message Buffer Frame ID Register */
20588  FR_MBFIDR_16B_tag MBFIDR40; /* offset: 0x0244 size: 16 bit */
20589  /* Message Buffer Index Register */
20590  FR_MBIDXR_16B_tag MBIDXR40; /* offset: 0x0246 size: 16 bit */
20591  /* Message Buffer Configuration Control Status Register */
20592  FR_MBCCSR_16B_tag MBCCSR41; /* offset: 0x0248 size: 16 bit */
20593  /* Message Buffer Cycle Counter Filter Register */
20594  FR_MBCCFR_16B_tag MBCCFR41; /* offset: 0x024A size: 16 bit */
20595  /* Message Buffer Frame ID Register */
20596  FR_MBFIDR_16B_tag MBFIDR41; /* offset: 0x024C size: 16 bit */
20597  /* Message Buffer Index Register */
20598  FR_MBIDXR_16B_tag MBIDXR41; /* offset: 0x024E size: 16 bit */
20599  /* Message Buffer Configuration Control Status Register */
20600  FR_MBCCSR_16B_tag MBCCSR42; /* offset: 0x0250 size: 16 bit */
20601  /* Message Buffer Cycle Counter Filter Register */
20602  FR_MBCCFR_16B_tag MBCCFR42; /* offset: 0x0252 size: 16 bit */
20603  /* Message Buffer Frame ID Register */
20604  FR_MBFIDR_16B_tag MBFIDR42; /* offset: 0x0254 size: 16 bit */
20605  /* Message Buffer Index Register */
20606  FR_MBIDXR_16B_tag MBIDXR42; /* offset: 0x0256 size: 16 bit */
20607  /* Message Buffer Configuration Control Status Register */
20608  FR_MBCCSR_16B_tag MBCCSR43; /* offset: 0x0258 size: 16 bit */
20609  /* Message Buffer Cycle Counter Filter Register */
20610  FR_MBCCFR_16B_tag MBCCFR43; /* offset: 0x025A size: 16 bit */
20611  /* Message Buffer Frame ID Register */
20612  FR_MBFIDR_16B_tag MBFIDR43; /* offset: 0x025C size: 16 bit */
20613  /* Message Buffer Index Register */
20614  FR_MBIDXR_16B_tag MBIDXR43; /* offset: 0x025E size: 16 bit */
20615  /* Message Buffer Configuration Control Status Register */
20616  FR_MBCCSR_16B_tag MBCCSR44; /* offset: 0x0260 size: 16 bit */
20617  /* Message Buffer Cycle Counter Filter Register */
20618  FR_MBCCFR_16B_tag MBCCFR44; /* offset: 0x0262 size: 16 bit */
20619  /* Message Buffer Frame ID Register */
20620  FR_MBFIDR_16B_tag MBFIDR44; /* offset: 0x0264 size: 16 bit */
20621  /* Message Buffer Index Register */
20622  FR_MBIDXR_16B_tag MBIDXR44; /* offset: 0x0266 size: 16 bit */
20623  /* Message Buffer Configuration Control Status Register */
20624  FR_MBCCSR_16B_tag MBCCSR45; /* offset: 0x0268 size: 16 bit */
20625  /* Message Buffer Cycle Counter Filter Register */
20626  FR_MBCCFR_16B_tag MBCCFR45; /* offset: 0x026A size: 16 bit */
20627  /* Message Buffer Frame ID Register */
20628  FR_MBFIDR_16B_tag MBFIDR45; /* offset: 0x026C size: 16 bit */
20629  /* Message Buffer Index Register */
20630  FR_MBIDXR_16B_tag MBIDXR45; /* offset: 0x026E size: 16 bit */
20631  /* Message Buffer Configuration Control Status Register */
20632  FR_MBCCSR_16B_tag MBCCSR46; /* offset: 0x0270 size: 16 bit */
20633  /* Message Buffer Cycle Counter Filter Register */
20634  FR_MBCCFR_16B_tag MBCCFR46; /* offset: 0x0272 size: 16 bit */
20635  /* Message Buffer Frame ID Register */
20636  FR_MBFIDR_16B_tag MBFIDR46; /* offset: 0x0274 size: 16 bit */
20637  /* Message Buffer Index Register */
20638  FR_MBIDXR_16B_tag MBIDXR46; /* offset: 0x0276 size: 16 bit */
20639  /* Message Buffer Configuration Control Status Register */
20640  FR_MBCCSR_16B_tag MBCCSR47; /* offset: 0x0278 size: 16 bit */
20641  /* Message Buffer Cycle Counter Filter Register */
20642  FR_MBCCFR_16B_tag MBCCFR47; /* offset: 0x027A size: 16 bit */
20643  /* Message Buffer Frame ID Register */
20644  FR_MBFIDR_16B_tag MBFIDR47; /* offset: 0x027C size: 16 bit */
20645  /* Message Buffer Index Register */
20646  FR_MBIDXR_16B_tag MBIDXR47; /* offset: 0x027E size: 16 bit */
20647  /* Message Buffer Configuration Control Status Register */
20648  FR_MBCCSR_16B_tag MBCCSR48; /* offset: 0x0280 size: 16 bit */
20649  /* Message Buffer Cycle Counter Filter Register */
20650  FR_MBCCFR_16B_tag MBCCFR48; /* offset: 0x0282 size: 16 bit */
20651  /* Message Buffer Frame ID Register */
20652  FR_MBFIDR_16B_tag MBFIDR48; /* offset: 0x0284 size: 16 bit */
20653  /* Message Buffer Index Register */
20654  FR_MBIDXR_16B_tag MBIDXR48; /* offset: 0x0286 size: 16 bit */
20655  /* Message Buffer Configuration Control Status Register */
20656  FR_MBCCSR_16B_tag MBCCSR49; /* offset: 0x0288 size: 16 bit */
20657  /* Message Buffer Cycle Counter Filter Register */
20658  FR_MBCCFR_16B_tag MBCCFR49; /* offset: 0x028A size: 16 bit */
20659  /* Message Buffer Frame ID Register */
20660  FR_MBFIDR_16B_tag MBFIDR49; /* offset: 0x028C size: 16 bit */
20661  /* Message Buffer Index Register */
20662  FR_MBIDXR_16B_tag MBIDXR49; /* offset: 0x028E size: 16 bit */
20663  /* Message Buffer Configuration Control Status Register */
20664  FR_MBCCSR_16B_tag MBCCSR50; /* offset: 0x0290 size: 16 bit */
20665  /* Message Buffer Cycle Counter Filter Register */
20666  FR_MBCCFR_16B_tag MBCCFR50; /* offset: 0x0292 size: 16 bit */
20667  /* Message Buffer Frame ID Register */
20668  FR_MBFIDR_16B_tag MBFIDR50; /* offset: 0x0294 size: 16 bit */
20669  /* Message Buffer Index Register */
20670  FR_MBIDXR_16B_tag MBIDXR50; /* offset: 0x0296 size: 16 bit */
20671  /* Message Buffer Configuration Control Status Register */
20672  FR_MBCCSR_16B_tag MBCCSR51; /* offset: 0x0298 size: 16 bit */
20673  /* Message Buffer Cycle Counter Filter Register */
20674  FR_MBCCFR_16B_tag MBCCFR51; /* offset: 0x029A size: 16 bit */
20675  /* Message Buffer Frame ID Register */
20676  FR_MBFIDR_16B_tag MBFIDR51; /* offset: 0x029C size: 16 bit */
20677  /* Message Buffer Index Register */
20678  FR_MBIDXR_16B_tag MBIDXR51; /* offset: 0x029E size: 16 bit */
20679  /* Message Buffer Configuration Control Status Register */
20680  FR_MBCCSR_16B_tag MBCCSR52; /* offset: 0x02A0 size: 16 bit */
20681  /* Message Buffer Cycle Counter Filter Register */
20682  FR_MBCCFR_16B_tag MBCCFR52; /* offset: 0x02A2 size: 16 bit */
20683  /* Message Buffer Frame ID Register */
20684  FR_MBFIDR_16B_tag MBFIDR52; /* offset: 0x02A4 size: 16 bit */
20685  /* Message Buffer Index Register */
20686  FR_MBIDXR_16B_tag MBIDXR52; /* offset: 0x02A6 size: 16 bit */
20687  /* Message Buffer Configuration Control Status Register */
20688  FR_MBCCSR_16B_tag MBCCSR53; /* offset: 0x02A8 size: 16 bit */
20689  /* Message Buffer Cycle Counter Filter Register */
20690  FR_MBCCFR_16B_tag MBCCFR53; /* offset: 0x02AA size: 16 bit */
20691  /* Message Buffer Frame ID Register */
20692  FR_MBFIDR_16B_tag MBFIDR53; /* offset: 0x02AC size: 16 bit */
20693  /* Message Buffer Index Register */
20694  FR_MBIDXR_16B_tag MBIDXR53; /* offset: 0x02AE size: 16 bit */
20695  /* Message Buffer Configuration Control Status Register */
20696  FR_MBCCSR_16B_tag MBCCSR54; /* offset: 0x02B0 size: 16 bit */
20697  /* Message Buffer Cycle Counter Filter Register */
20698  FR_MBCCFR_16B_tag MBCCFR54; /* offset: 0x02B2 size: 16 bit */
20699  /* Message Buffer Frame ID Register */
20700  FR_MBFIDR_16B_tag MBFIDR54; /* offset: 0x02B4 size: 16 bit */
20701  /* Message Buffer Index Register */
20702  FR_MBIDXR_16B_tag MBIDXR54; /* offset: 0x02B6 size: 16 bit */
20703  /* Message Buffer Configuration Control Status Register */
20704  FR_MBCCSR_16B_tag MBCCSR55; /* offset: 0x02B8 size: 16 bit */
20705  /* Message Buffer Cycle Counter Filter Register */
20706  FR_MBCCFR_16B_tag MBCCFR55; /* offset: 0x02BA size: 16 bit */
20707  /* Message Buffer Frame ID Register */
20708  FR_MBFIDR_16B_tag MBFIDR55; /* offset: 0x02BC size: 16 bit */
20709  /* Message Buffer Index Register */
20710  FR_MBIDXR_16B_tag MBIDXR55; /* offset: 0x02BE size: 16 bit */
20711  /* Message Buffer Configuration Control Status Register */
20712  FR_MBCCSR_16B_tag MBCCSR56; /* offset: 0x02C0 size: 16 bit */
20713  /* Message Buffer Cycle Counter Filter Register */
20714  FR_MBCCFR_16B_tag MBCCFR56; /* offset: 0x02C2 size: 16 bit */
20715  /* Message Buffer Frame ID Register */
20716  FR_MBFIDR_16B_tag MBFIDR56; /* offset: 0x02C4 size: 16 bit */
20717  /* Message Buffer Index Register */
20718  FR_MBIDXR_16B_tag MBIDXR56; /* offset: 0x02C6 size: 16 bit */
20719  /* Message Buffer Configuration Control Status Register */
20720  FR_MBCCSR_16B_tag MBCCSR57; /* offset: 0x02C8 size: 16 bit */
20721  /* Message Buffer Cycle Counter Filter Register */
20722  FR_MBCCFR_16B_tag MBCCFR57; /* offset: 0x02CA size: 16 bit */
20723  /* Message Buffer Frame ID Register */
20724  FR_MBFIDR_16B_tag MBFIDR57; /* offset: 0x02CC size: 16 bit */
20725  /* Message Buffer Index Register */
20726  FR_MBIDXR_16B_tag MBIDXR57; /* offset: 0x02CE size: 16 bit */
20727  /* Message Buffer Configuration Control Status Register */
20728  FR_MBCCSR_16B_tag MBCCSR58; /* offset: 0x02D0 size: 16 bit */
20729  /* Message Buffer Cycle Counter Filter Register */
20730  FR_MBCCFR_16B_tag MBCCFR58; /* offset: 0x02D2 size: 16 bit */
20731  /* Message Buffer Frame ID Register */
20732  FR_MBFIDR_16B_tag MBFIDR58; /* offset: 0x02D4 size: 16 bit */
20733  /* Message Buffer Index Register */
20734  FR_MBIDXR_16B_tag MBIDXR58; /* offset: 0x02D6 size: 16 bit */
20735  /* Message Buffer Configuration Control Status Register */
20736  FR_MBCCSR_16B_tag MBCCSR59; /* offset: 0x02D8 size: 16 bit */
20737  /* Message Buffer Cycle Counter Filter Register */
20738  FR_MBCCFR_16B_tag MBCCFR59; /* offset: 0x02DA size: 16 bit */
20739  /* Message Buffer Frame ID Register */
20740  FR_MBFIDR_16B_tag MBFIDR59; /* offset: 0x02DC size: 16 bit */
20741  /* Message Buffer Index Register */
20742  FR_MBIDXR_16B_tag MBIDXR59; /* offset: 0x02DE size: 16 bit */
20743  /* Message Buffer Configuration Control Status Register */
20744  FR_MBCCSR_16B_tag MBCCSR60; /* offset: 0x02E0 size: 16 bit */
20745  /* Message Buffer Cycle Counter Filter Register */
20746  FR_MBCCFR_16B_tag MBCCFR60; /* offset: 0x02E2 size: 16 bit */
20747  /* Message Buffer Frame ID Register */
20748  FR_MBFIDR_16B_tag MBFIDR60; /* offset: 0x02E4 size: 16 bit */
20749  /* Message Buffer Index Register */
20750  FR_MBIDXR_16B_tag MBIDXR60; /* offset: 0x02E6 size: 16 bit */
20751  /* Message Buffer Configuration Control Status Register */
20752  FR_MBCCSR_16B_tag MBCCSR61; /* offset: 0x02E8 size: 16 bit */
20753  /* Message Buffer Cycle Counter Filter Register */
20754  FR_MBCCFR_16B_tag MBCCFR61; /* offset: 0x02EA size: 16 bit */
20755  /* Message Buffer Frame ID Register */
20756  FR_MBFIDR_16B_tag MBFIDR61; /* offset: 0x02EC size: 16 bit */
20757  /* Message Buffer Index Register */
20758  FR_MBIDXR_16B_tag MBIDXR61; /* offset: 0x02EE size: 16 bit */
20759  /* Message Buffer Configuration Control Status Register */
20760  FR_MBCCSR_16B_tag MBCCSR62; /* offset: 0x02F0 size: 16 bit */
20761  /* Message Buffer Cycle Counter Filter Register */
20762  FR_MBCCFR_16B_tag MBCCFR62; /* offset: 0x02F2 size: 16 bit */
20763  /* Message Buffer Frame ID Register */
20764  FR_MBFIDR_16B_tag MBFIDR62; /* offset: 0x02F4 size: 16 bit */
20765  /* Message Buffer Index Register */
20766  FR_MBIDXR_16B_tag MBIDXR62; /* offset: 0x02F6 size: 16 bit */
20767  /* Message Buffer Configuration Control Status Register */
20768  FR_MBCCSR_16B_tag MBCCSR63; /* offset: 0x02F8 size: 16 bit */
20769  /* Message Buffer Cycle Counter Filter Register */
20770  FR_MBCCFR_16B_tag MBCCFR63; /* offset: 0x02FA size: 16 bit */
20771  /* Message Buffer Frame ID Register */
20772  FR_MBFIDR_16B_tag MBFIDR63; /* offset: 0x02FC size: 16 bit */
20773  /* Message Buffer Index Register */
20774  FR_MBIDXR_16B_tag MBIDXR63; /* offset: 0x02FE size: 16 bit */
20775  };
20776 
20777  };
20778  } FR_tag;
20779 
20780 
20781 #define FR (*(volatile FR_tag *) 0xFFFE0000UL)
20782 
20783 
20784 
20785 
20786 
20787 #ifdef __MWERKS__
20788 #pragma pop
20789 #endif
20790 
20791 #ifdef __cplusplus
20792 }
20793 #endif
20794 #endif /* _leopard_H_*/
20795 /* End of file */
20796 
CTU_COTR_16B_tag
Definition: xpc56el.h:7964
LINFLEX_LINCFR_32B_tag
Definition: xpc56el.h:10236
mcPWM_DTCNT1_16B_tag
Definition: xpc56el.h:9150
mcPWM_CTRL1_16B_tag
Definition: xpc56el.h:8948
RGM_DES_16B_tag
Definition: xpc56el.h:4963
FLEXCAN_ESR_32B_tag
Definition: xpc56el.h:17161
FR_SSCR_16B_tag
Definition: xpc56el.h:19926
LINFLEX_IFMI_32B_tag
Definition: xpc56el.h:10299
ADC_THRHLR7_32B_tag
Definition: xpc56el.h:6600
FCCU_CFS_CFG3_32B_tag
Definition: xpc56el.h:10966
FR_SSCR3_16B_tag
Definition: xpc56el.h:19254
SPP_DMA2_TCDWORD8__32B_tag
Definition: xpc56el.h:14507
SEMA4_CP0INE_16B_tag
Definition: xpc56el.h:13609
mcTIMER_DREQ2_16B_tag
Definition: xpc56el.h:8591
FR_SFTOR_16B_tag
Definition: xpc56el.h:18998
AIPS_OPACR16_23_32B_tag
Definition: xpc56el.h:12565
FCCU_NCF_CFG2_32B_tag
Definition: xpc56el.h:10824
SIUL_IRER_32B_tag
Definition: xpc56el.h:724
SWT_SR_32B_tag
Definition: xpc56el.h:13765
FCCU_CFS_CFG7_32B_tag
Definition: xpc56el.h:11054
SIUL_PCR_16B_tag
Definition: xpc56el.h:879
ME_tag
Definition: xpc560bc.h:2370
mcPWM_CVAL2_16B_tag
Definition: xpc56el.h:9298
ADC_STCR3_32B_tag
Definition: xpc56el.h:6812
CTU_FL_32B_tag
Definition: xpc56el.h:7792
FCCU_CF_CFG0_32B_tag
Definition: xpc56el.h:10596
SPP_DMA2_TCDWORD28__32B_tag
Definition: xpc56el.h:14563
CGM_tag
Definition: xpc560bc.h:648
ADC_CWSELR_32B_tag
Definition: xpc56el.h:6693
FR_PCR7_16B_tag
Definition: xpc56el.h:19484
PMUCTRL_IRQE_32B_tag
Definition: xpc56el.h:5331
CTU_CLCR2_32B_tag
Definition: xpc56el.h:7465
FCCU_CTRLK_32B_tag
Definition: xpc56el.h:10576
SSCM_STATUS_16B_tag
Definition: xpc56el.h:3549
DSPI_MCR_32B_tag
Definition: xpc56el.h:16651
ADC_STDR2_32B_tag
Definition: xpc56el.h:6895
ME_MCTL_32B_tag
Definition: xpc56el.h:3755
ADC_PSR2_32B_tag
Definition: xpc56el.h:6238
ME_MEN_32B_tag
Definition: xpc56el.h:3764
FCCU_NCF_CFG_32B_tag
Definition: xpc56el.h:12016
FR_PCR23_16B_tag
Definition: xpc56el.h:19651
SPP_MCM_PFEDRH_32B_tag
Definition: xpc56el.h:14104
WKPU_IRER_32B_tag
Definition: xpc56el.h:3470
FR_SFTCCSR_16B_tag
Definition: xpc56el.h:19006
CFLASH_LMS_32B_tag
Definition: xpc56el.h:323
FCCU_NCFF_32B_tag
Definition: xpc56el.h:11951
LINFLEX_IFCR_32B_tag
Definition: xpc56el.h:10318
SPP_DMA2_DMAGPOR_32B_tag
Definition: xpc56el.h:14460
ME_PS2_32B_tag
Definition: xpc56el.h:4164
FCCU_CFK_32B_tag
Definition: xpc56el.h:11404
FCCU_CFS_CFG_32B_tag
Definition: xpc56el.h:12023
CFLASH_SHADOW_BIU_DEFAULTS_struct_tag
Definition: xpc56el.h:175
MPU_RGDAAC_32B_tag
Definition: xpc56el.h:13344
SPP_DMA2_DMASSRT_8B_tag
Definition: xpc56el.h:14402
SIUL_MPGPDO_32B_tag
Definition: xpc56el.h:1007
FR_RSBIR_16B_tag
Definition: xpc56el.h:19283
FR_EEIDR_16B_tag
Definition: xpc56el.h:19831
ADC_THRHLR11_32B_tag
Definition: xpc56el.h:6640
FCCU_IRQ_STAT_32B_tag
Definition: xpc56el.h:11959
SWT_TO_32B_tag
Definition: xpc56el.h:13751
SPP_DMA2_DMASERQ_8B_tag
Definition: xpc56el.h:14354
CMU_FDR_32B_tag
Definition: xpc56el.h:4665
vuint8_t
volatile uint8_t vuint8_t
Definition: chtypes.h:47
CTU_TH2_32B_tag
Definition: xpc56el.h:7711
CFLASH_SHADOW_NVLML_32B_tag
Definition: xpc56el.h:145
ADC_STAW5R_32B_tag
Definition: xpc56el.h:6972
CFLASH_SHADOW_NVBIU_32B_tag
Definition: xpc56el.h:160
CGM_SC_DC0_3_32B_tag
Definition: xpc56el.h:4780
CFLASH_SHADOW_struct_tag
Definition: xpc56el.h:184
FCCU_NCFE1_32B_tag
Definition: xpc56el.h:11602
LINFLEX_DMATXE_32B_tag
Definition: xpc56el.h:10359
LINFLEX_UARTCR_32B_tag
Definition: xpc56el.h:10123
FCCU_CFS3_32B_tag
Definition: xpc56el.h:11366
CFLASH_HBS_32B_tag
Definition: xpc56el.h:333
ADC_WTIMR_32B_tag
Definition: xpc56el.h:5968
FR_PCR27_16B_tag
Definition: xpc56el.h:19699
RC_CTL_32B_tag
Definition: xpc56el.h:4565
FR_MBSSUTR_16B_tag
Definition: xpc56el.h:18345
FCCU_CFF_32B_tag
Definition: xpc56el.h:11943
SPP_MCM_ECR_8B_tag
Definition: xpc56el.h:14004
AIPS_OPACR56_63_32B_tag
Definition: xpc56el.h:12755
FCCU_NCF_TO_32B_tag
Definition: xpc56el.h:11868
PIT_RTI_TFLG_32B_tag
Definition: xpc56el.h:5433
mcPWM_CVAL3CYC_16B_tag
Definition: xpc56el.h:9329
CTU_CTUCR_16B_tag
Definition: xpc56el.h:7976
SPP_DMA2_DMAERRH_32B_tag
Definition: xpc56el.h:14432
FCCU_NCFS_CFG4_32B_tag
Definition: xpc56el.h:11164
SPP_DMA2_DMAHRSH_32B_tag
Definition: xpc56el.h:14446
FR_RFSYMBHADR_16B_tag
Definition: xpc56el.h:19734
FR_RF_RFSIR_16B_tag
Definition: xpc56el.h:19303
ADC_THRHLR_32B_tag
Definition: xpc56el.h:6124
WKPU_WIFEER_32B_tag
Definition: xpc56el.h:3491
SPP_MCM_PLREV_16B_tag
Definition: xpc56el.h:13948
FR_MBFIDR_16B_tag
Definition: xpc56el.h:19895
FR_PSR3_16B_tag
Definition: xpc56el.h:18866
ADC_STCR1_32B_tag
Definition: xpc56el.h:6774
ADC_PSCR_32B_tag
Definition: xpc56el.h:6147
OSC_struct_tag
Definition: xpc56el.h:4549
mcTIMER_CCCTRL_16B_tag
Definition: xpc56el.h:8481
SPP_DMA2_DMACDNE_8B_tag
Definition: xpc56el.h:14410
CTU_struct_tag
Definition: xpc56el.h:8100
mcPWM_VAL_3_16B_tag
Definition: xpc56el.h:8992
CTU_STS_32B_tag
Definition: xpc56el.h:7737
SSCM_MEMCONFIG_16B_tag
Definition: xpc56el.h:3570
PLLD_struct_tag
Definition: xpc56el.h:4631
FR_PCR17_16B_tag
Definition: xpc56el.h:19583
ADC_JCMR0_32B_tag
Definition: xpc56el.h:6411
FR_SYMBADLR_16B_tag
Definition: xpc56el.h:18314
FR_MTSACFR_16B_tag
Definition: xpc56el.h:19261
FR_CBSERCR_16B_tag
Definition: xpc56el.h:18802
FR_MBIVEC_16B_tag
Definition: xpc56el.h:18785
ME_PS_32B_tag
Definition: xpc56el.h:4223
ADC_STAW2R_32B_tag
Definition: xpc56el.h:6939
MPU_CESR_32B_tag
Definition: xpc56el.h:13240
FCCU_CFG_32B_tag
Definition: xpc56el.h:10580
ADC_THRHLR6_32B_tag
Definition: xpc56el.h:6590
mcPWM_CAPTCTRLB_16B_tag
Definition: xpc56el.h:9190
LINFLEX_IFER_32B_tag
Definition: xpc56el.h:10291
AIPS_OPACR24_31_32B_tag
Definition: xpc56el.h:12603
PMUCTRL_FAULT_32B_tag
Definition: xpc56el.h:5298
SPP_MCM_MRSR_8B_tag
Definition: xpc56el.h:13962
SSCM_DPMKEY_32B_tag
Definition: xpc56el.h:3620
STM_CNT_32B_tag
Definition: xpc56el.h:13829
FCCU_NCFK_32B_tag
Definition: xpc56el.h:11560
FR_RFDSR_16B_tag
Definition: xpc56el.h:19311
RGM_FESS_16B_tag
Definition: xpc56el.h:5052
FLEXCAN_IFLAG2_32B_tag
Definition: xpc56el.h:17357
SPP_MCM_IOPMC_32B_tag
Definition: xpc56el.h:13955
FR_SSCR1_16B_tag
Definition: xpc56el.h:19240
FLEXCAN_CTRL_32B_tag
Definition: xpc56el.h:17066
ADC_THRHLR15_32B_tag
Definition: xpc56el.h:6680
ME_DMTS_32B_tag
Definition: xpc56el.h:3848
CFLASH_SHADOW_NVPWD_32B_tag
Definition: xpc56el.h:127
LINFLEX_tag
Definition: xpc560bc.h:2101
SIUL_PGPDO_16B_tag
Definition: xpc56el.h:993
FR_SYMATOR_16B_tag
Definition: xpc56el.h:18980
ME_STANDBY0_MC_32B_tag
Definition: xpc56el.h:4086
ADC_CEOCFR2_32B_tag
Definition: xpc56el.h:5787
DSPI_TCR_32B_tag
Definition: xpc56el.h:16681
FR_PCR6_16B_tag
Definition: xpc56el.h:19471
SPP_DMA2_TCDWORD24__32B_tag
Definition: xpc56el.h:14553
SIUL_PSMI_8B_tag
Definition: xpc56el.h:909
CFLASH_SHADOW_NVSCI_32B_tag
Definition: xpc56el.h:137
SPP_DMA2_DMAERQH_32B_tag
Definition: xpc56el.h:14326
SWT_tag
Definition: xpc560bc.h:3551
mcPWM_CVAL4CYC_16B_tag
Definition: xpc56el.h:9350
FCCU_NAFS_32B_tag
Definition: xpc56el.h:11900
SSCM_UOPS_32B_tag
Definition: xpc56el.h:3627
mcPWM_SUBMOD_struct_tag
Definition: xpc56el.h:9544
FR_SSCCR_16B_tag
Definition: xpc56el.h:19192
ADC_NCMR0_32B_tag
Definition: xpc56el.h:6297
ADC_STAW3R_32B_tag
Definition: xpc56el.h:6948
ADC_JCMR1_32B_tag
Definition: xpc56el.h:6449
FR_CHIERFR_16B_tag
Definition: xpc56el.h:18699
MPU_RGD_WORD3_32B_tag
Definition: xpc56el.h:13331
FR_PCR21_16B_tag
Definition: xpc56el.h:19626
ADC_CTR_32B_tag
Definition: xpc56el.h:6279
AIPS_OPACR72_79_32B_tag
Definition: xpc56el.h:12831
ME_PCTL_8B_tag
Definition: xpc56el.h:4208
FLEXCAN_MSG_DATA_32B_tag
Definition: xpc56el.h:17505
ADC_THRHLR9_32B_tag
Definition: xpc56el.h:6620
SIUL_MIDR2_32B_tag
Definition: xpc56el.h:666
CRC_OUTP_32B_tag
Definition: xpc56el.h:10497
FR_NMVR0_16B_tag
Definition: xpc56el.h:19051
CTU_FCR_32B_tag
Definition: xpc56el.h:7647
PMUCTRL_STATEREG_32B_tag
Definition: xpc56el.h:5260
SIUL_ISR_32B_tag
Definition: xpc56el.h:686
PIT_RTI_CVAL_32B_tag
Definition: xpc56el.h:5411
ME_LP_PC_32B_tag
Definition: xpc56el.h:4194
SWT_SK_32B_tag
Definition: xpc56el.h:13780
FR_MBCCSR_16B_tag
Definition: xpc56el.h:19849
FCCU_CFS_CFG5_32B_tag
Definition: xpc56el.h:11010
mcPWM_CVAL1CYC_16B_tag
Definition: xpc56el.h:9287
FCCU_NCFS_CFG2_32B_tag
Definition: xpc56el.h:11120
FCCU_NCF_CFG0_32B_tag
Definition: xpc56el.h:10748
mcTIMER_DREQ_16B_tag
Definition: xpc56el.h:8610
mcTIMER_COMP2_16B_tag
Definition: xpc56el.h:8305
FCCU_CF_CFG2_32B_tag
Definition: xpc56el.h:10672
FR_PIER1_16B_tag
Definition: xpc56el.h:18652
DSPI_tag
Definition: xpc560bc.h:1057
FR_PCR9_16B_tag
Definition: xpc56el.h:19501
SWT_IR_32B_tag
Definition: xpc56el.h:13743
FCCU_XTMR_32B_tag
Definition: xpc56el.h:11977
DSPI_ASDR_32B_tag
Definition: xpc56el.h:16883
LINFLEX_LINCR2_32B_tag
Definition: xpc56el.h:10244
mcPWM_CVAL0_16B_tag
Definition: xpc56el.h:9256
mcPWM_FRACA_16B_tag
Definition: xpc56el.h:9013
mcPWM_VAL_5_16B_tag
Definition: xpc56el.h:9006
mcPWM_CAPTCMPX_16B_tag
Definition: xpc56el.h:9245
mcPWM_CTRL2_16B_tag
Definition: xpc56el.h:8919
CFLASH_tag
Definition: xpc560bc.h:457
mcPWM_struct_tag
Definition: xpc56el.h:9668
FR_PCR11_16B_tag
Definition: xpc56el.h:19519
ADC_ISR_32B_tag
Definition: xpc56el.h:5569
ADC_NCMR1_32B_tag
Definition: xpc56el.h:6335
SPP_DMA2_DMAEEIH_32B_tag
Definition: xpc56el.h:14340
PCU_PSTAT_32B_tag
Definition: xpc56el.h:5160
DSPI_SR_32B_tag
Definition: xpc56el.h:16715
SPP_MCM_struct_tag
Definition: xpc56el.h:14163
SSCM_tag
Definition: xpc560bc.h:3444
RGM_FEAR_16B_tag
Definition: xpc56el.h:5030
SPP_MCM_PFEAT_8B_tag
Definition: xpc56el.h:14083
SPP_MCM_MIR_8B_tag
Definition: xpc56el.h:13984
MPU_RGD_WORD0_32B_tag
Definition: xpc56el.h:13280
FR_PCR30_16B_tag
Definition: xpc56el.h:19726
AIPS_PACR24_31_32B_tag
Definition: xpc56el.h:12451
mcTIMER_HOLD_16B_tag
Definition: xpc56el.h:8345
ADC_THRHLR4_32B_tag
Definition: xpc56el.h:6570
mcTIMER_struct_tag
Definition: xpc56el.h:8656
SPP_MCM_PFEAR_32B_tag
Definition: xpc56el.h:14075
CMU_struct_tag
Definition: xpc56el.h:4714
SPP_DMA2_DMAINTL_32B_tag
Definition: xpc56el.h:14425
FLEXCAN_IMASK1_32B_tag
Definition: xpc56el.h:17279
CTU_CTUIFR_16B_tag
Definition: xpc56el.h:7844
SSCM_PWCMPH_32B_tag
Definition: xpc56el.h:3597
AIPS_PACR16_23_32B_tag
Definition: xpc56el.h:12413
FCCU_CFS_CFG2_32B_tag
Definition: xpc56el.h:10944
ME_RUN_PC_32B_tag
Definition: xpc56el.h:4176
SIUL_IFER_32B_tag
Definition: xpc56el.h:838
FCCU_NCFS_CFG_32B_tag
Definition: xpc56el.h:12030
FR_PSR2_16B_tag
Definition: xpc56el.h:18843
FCCU_NCF_CFG3_32B_tag
Definition: xpc56el.h:10862
CTU_TCR_16B_tag
Definition: xpc56el.h:7429
CFLASH_UM_32B_tag
Definition: xpc56el.h:525
ADC_STCR2_32B_tag
Definition: xpc56el.h:6786
ME_GS_32B_tag
Definition: xpc56el.h:3719
FR_PCR4_16B_tag
Definition: xpc56el.h:19454
FR_SFIDAFMR_16B_tag
Definition: xpc56el.h:19043
mcPWM_CVAL3_16B_tag
Definition: xpc56el.h:9319
FR_MVR_16B_tag
Definition: xpc56el.h:18271
FCCU_NCF_TOE_32B_tag
Definition: xpc56el.h:12058
ME_RUN_MC_32B_tag
Definition: xpc56el.h:3992
SPP_DMA2_DMACINT_8B_tag
Definition: xpc56el.h:14386
FCCU_STAT_32B_tag
Definition: xpc56el.h:11892
SPP_MCM_PREAT_8B_tag
Definition: xpc56el.h:14132
SPP_DMA2_DMASEEI_8B_tag
Definition: xpc56el.h:14370
FR_PCR25_16B_tag
Definition: xpc56el.h:19675
PMUCTRL_STATHVD_32B_tag
Definition: xpc56el.h:5226
CGM_SC_SS_32B_tag
Definition: xpc56el.h:4768
SPP_MCM_MUDCR_32B_tag
Definition: xpc56el.h:13997
FR_MBCCFR_16B_tag
Definition: xpc56el.h:19872
MPU_RGD_WORD1_32B_tag
Definition: xpc56el.h:13291
ADC_MSR_32B_tag
Definition: xpc56el.h:5546
WKPU_WIPUER_32B_tag
Definition: xpc56el.h:3505
DSPI_DSICR1_32B_tag
Definition: xpc56el.h:16907
mcTIMER_ENBL_16B_tag
Definition: xpc56el.h:8567
SGENDIG_struct_tag
Definition: xpc56el.h:12281
FR_NMVR2_16B_tag
Definition: xpc56el.h:19067
SPP_DMA2_TCDWORD0__32B_tag
Definition: xpc56el.h:14483
CFLASH_PFAPR_32B_tag
Definition: xpc56el.h:473
SPP_MCM_PFEMR_8B_tag
Definition: xpc56el.h:14079
PCU_PCONF_32B_tag
Definition: xpc56el.h:5140
mcTIMER_CNTR_16B_tag
Definition: xpc56el.h:8355
FR_SFIDAFVR_16B_tag
Definition: xpc56el.h:19035
FCCU_NCF_TOE0_32B_tag
Definition: xpc56el.h:11716
FIFO
Definition: fifo.hpp:35
SPP_DMA2_TCDWORD20__32B_tag
Definition: xpc56el.h:14540
ADC_THRALT_32B_tag
Definition: xpc56el.h:6137
mcPWM_VAL_1_16B_tag
Definition: xpc56el.h:8978
FR_TI1MTOR_16B_tag
Definition: xpc56el.h:19156
FCCU_NCFS_CFG6_32B_tag
Definition: xpc56el.h:11208
FR_PCR15_16B_tag
Definition: xpc56el.h:19556
ADC_JCMR2_32B_tag
Definition: xpc56el.h:6487
FR_CASERCR_16B_tag
Definition: xpc56el.h:18795
FR_TI2CR0_16B_tag
Definition: xpc56el.h:19164
FR_PCR24_16B_tag
Definition: xpc56el.h:19662
ME_SAFE_MC_32B_tag
Definition: xpc56el.h:3913
FLEXCAN_tag
Definition: xpc560bc.h:1680
FR_SSR_16B_tag
Definition: xpc56el.h:19209
LINFLEX_IFMR_32B_tag
Definition: xpc56el.h:10307
FR_EEICR_16B_tag
Definition: xpc56el.h:19838
SWT_CO_32B_tag
Definition: xpc56el.h:13773
FR_SLTCTBR_16B_tag
Definition: xpc56el.h:18910
mcPWM_FSTS_16B_tag
Definition: xpc56el.h:9516
FR_RFFIDRFVR_16B_tag
Definition: xpc56el.h:19358
FR_RFRFCFR_16B_tag
Definition: xpc56el.h:19374
INTC_EOIR_PRC1_32B_tag
Definition: xpc56el.h:15834
SPP_MCM_PREMR_8B_tag
Definition: xpc56el.h:14120
LINFLEX_LINTOCR_32B_tag
Definition: xpc56el.h:10202
mcTIMER_DREQ1_16B_tag
Definition: xpc56el.h:8583
CFLASH_UT0_32B_tag
Definition: xpc56el.h:497
SEMA4_CP0NTF_16B_tag
Definition: xpc56el.h:13623
STM_struct_tag
Definition: xpc56el.h:13876
DSPI_DSICR_32B_tag
Definition: xpc56el.h:16850
FCCU_NCFS_CFG1_32B_tag
Definition: xpc56el.h:11098
mcTIMER_CTRL2_16B_tag
Definition: xpc56el.h:8380
ME_IM_32B_tag
Definition: xpc56el.h:3809
FR_EERAR_16B_tag
Definition: xpc56el.h:19798
ADC_CEOCFR0_32B_tag
Definition: xpc56el.h:5583
FR_PCR0_16B_tag
Definition: xpc56el.h:19417
STM_CHANNEL_tag
Definition: xpc560bc.h:3500
FCCU_NCF_TOE3_32B_tag
Definition: xpc56el.h:11830
FCCU_IRQ_EN_32B_tag
Definition: xpc56el.h:11969
SIUL_PSMI_32B_tag
Definition: xpc56el.h:920
FLEXCAN_ECR_32B_tag
Definition: xpc56el.h:17144
CFLASH_SHADOW_NVSLL_32B_tag
Definition: xpc56el.h:153
FR_PCR14_16B_tag
Definition: xpc56el.h:19544
ADC_NCMR2_32B_tag
Definition: xpc56el.h:6373
PLLD_CR_32B_tag
Definition: xpc56el.h:4596
mcPWM_CAPTCTRLA_16B_tag
Definition: xpc56el.h:9161
STM_tag
Definition: xpc560bc.h:3526
CMU_LFREFR_A_32B_tag
Definition: xpc56el.h:4681
CTU_CTUEFR_16B_tag
Definition: xpc56el.h:7804
OSC_CTL_32B_tag
Definition: xpc56el.h:4532
FLEXCAN_MB_struct_tag
Definition: xpc56el.h:17528
DSPI_COMPR_32B_tag
Definition: xpc56el.h:16891
ADC_THRHLR12_32B_tag
Definition: xpc56el.h:6650
CTU_THCR1_32B_tag
Definition: xpc56el.h:7479
mcTIMER_FFILT_16B_tag
Definition: xpc56el.h:8550
FR_NMVR_16B_tag
Definition: xpc56el.h:19917
PMUCTRL_STATIREG_32B_tag
Definition: xpc56el.h:5252
INTC_SSCIR4_7_32B_tag
Definition: xpc56el.h:15868
INTC_CPR_PRC0_32B_tag
Definition: xpc56el.h:15788
FR_PSR1_16B_tag
Definition: xpc56el.h:18825
LINFLEX_BDRL_32B_tag
Definition: xpc56el.h:10271
mcPWM_CAPTCMPB_16B_tag
Definition: xpc56el.h:9208
FCCU_NCFS2_32B_tag
Definition: xpc56el.h:11484
MAX_SGPCR_32B_tag
Definition: xpc56el.h:13028
FCCU_SCFS_32B_tag
Definition: xpc56el.h:11934
SEMA4_struct_tag
Definition: xpc56el.h:13661
CFLASH_UT_32B_tag
Definition: xpc56el.h:539
mcPWM_STS_16B_tag
Definition: xpc56el.h:9057
FCCU_CFS2_32B_tag
Definition: xpc56el.h:11328
FR_MB_struct_tag
Definition: xpc56el.h:19931
ADC_tag
Definition: xpc560bc.h:53
AIPS_MPROT_32B_tag
Definition: xpc56el.h:12299
SPP_MCM_PCT_16B_tag
Definition: xpc56el.h:13941
CMU_CSR_32B_tag
Definition: xpc56el.h:4652
SPP_DMA2_DMAES_32B_tag
Definition: xpc56el.h:14306
mcPWM_DTCNT0_16B_tag
Definition: xpc56el.h:9139
MPU_RGD_WORD2_32B_tag
Definition: xpc56el.h:13302
mcTIMER_WDTOL_16B_tag
Definition: xpc56el.h:8515
FR_RFARIR_16B_tag
Definition: xpc56el.h:19328
FCCU_AFFS_32B_tag
Definition: xpc56el.h:11908
SIUL_IFCPR_32B_tag
Definition: xpc56el.h:1026
SPP_MCM_EEGR_16B_tag
Definition: xpc56el.h:14060
FR_RFFLPCR_16B_tag
Definition: xpc56el.h:19757
STM_CIR_32B_tag
Definition: xpc56el.h:13847
SPP_MCM_PRESR_8B_tag
Definition: xpc56el.h:14116
mcTIMER_WDTOH_16B_tag
Definition: xpc56el.h:8522
CTU_TGSCCR_16B_tag
Definition: xpc56el.h:7433
FR_PIFR1_16B_tag
Definition: xpc56el.h:18508
SSCM_TF_INFO1_32B_tag
Definition: xpc56el.h:3651
FCCU_CFS_CFG0_32B_tag
Definition: xpc56el.h:10900
FR_RTCORVR_16B_tag
Definition: xpc56el.h:18918
PIT_RTI_struct_tag
Definition: xpc56el.h:5456
CRC_struct_tag
Definition: xpc56el.h:10519
LINFLEX_UARTPTO_32B_tag
Definition: xpc56el.h:10343
SPP_DMA2_DMAERQL_32B_tag
Definition: xpc56el.h:14333
ADC_STAW4R_32B_tag
Definition: xpc56el.h:6960
RGM_FES_16B_tag
Definition: xpc56el.h:4937
CRC_CNTX_struct_tag
Definition: xpc56el.h:10505
mcPWM_FRACB_16B_tag
Definition: xpc56el.h:9025
STM_CMP_32B_tag
Definition: xpc56el.h:13858
LINFLEX_GCR_32B_tag
Definition: xpc56el.h:10330
DMA_CH_MUX_struct_tag
Definition: xpc56el.h:18232
mcPWM_CVAL5_16B_tag
Definition: xpc56el.h:9361
AIPS_OPACR64_71_32B_tag
Definition: xpc56el.h:12793
WKPU_WISR_32B_tag
Definition: xpc56el.h:3463
ADC_DSDR_32B_tag
Definition: xpc56el.h:6539
ADC_PSR1_32B_tag
Definition: xpc56el.h:6200
SPP_MCM_ESR_8B_tag
Definition: xpc56el.h:14032
SIUL_struct_tag
Definition: xpc56el.h:1036
MPU_REGION_struct_tag
Definition: xpc56el.h:13380
SIUL_IFMC_32B_tag
Definition: xpc56el.h:1018
INTC_PSR_32B_tag
Definition: xpc56el.h:15901
MAX_struct_tag
Definition: xpc56el.h:13113
PMUCTRL_STATUS_32B_tag
Definition: xpc56el.h:5268
SWT_struct_tag
Definition: xpc56el.h:13790
mcTIMER_FSTS_16B_tag
Definition: xpc56el.h:8540
ME_PS1_32B_tag
Definition: xpc56el.h:4140
mcTIMER_CAPT2_16B_tag
Definition: xpc56el.h:8325
SSCM_struct_tag
Definition: xpc56el.h:3674
FR_TI1CYSR_16B_tag
Definition: xpc56el.h:19138
mcTIMER_LOAD_16B_tag
Definition: xpc56el.h:8335
ADC_THRHLR10_32B_tag
Definition: xpc56el.h:6630
RGM_struct_tag
Definition: xpc56el.h:5106
FLEXCAN_IFLAG1_32B_tag
Definition: xpc56el.h:17395
CTU_TH1_32B_tag
Definition: xpc56el.h:7685
FR_LDTXSLBR_16B_tag
Definition: xpc56el.h:19409
FR_RFRFCTR_16B_tag
Definition: xpc56el.h:19385
WKPU_WIFER_32B_tag
Definition: xpc56el.h:3498
SPP_DMA2_DMAEEIL_32B_tag
Definition: xpc56el.h:14347
MAX_MPR_32B_tag
Definition: xpc56el.h:13000
FCCU_NCFE2_32B_tag
Definition: xpc56el.h:11640
ADC_struct_tag
Definition: xpc56el.h:6984
CFLASH_struct_tag
Definition: xpc56el.h:552
SPP_MCM_PFEDR_32B_tag
Definition: xpc56el.h:14108
FR_PCR13_16B_tag
Definition: xpc56el.h:19536
SPP_DMA2_DMACERR_8B_tag
Definition: xpc56el.h:14394
ADC_PSR0_32B_tag
Definition: xpc56el.h:6162
mcTIMER_CMPLD2_16B_tag
Definition: xpc56el.h:8471
mcPWM_VAL_16B_tag
Definition: xpc56el.h:9539
FCCU_NCF_TOE2_32B_tag
Definition: xpc56el.h:11792
FR_PCR28_16B_tag
Definition: xpc56el.h:19710
MAX_MGPCR_32B_tag
Definition: xpc56el.h:13080
SWT_CR_32B_tag
Definition: xpc56el.h:13718
PMUCTRL_STATLVD_32B_tag
Definition: xpc56el.h:5239
ADC_STAW1BR_32B_tag
Definition: xpc56el.h:6929
mcTIMER_DREQ3_16B_tag
Definition: xpc56el.h:8599
CFLASH_UT2_32B_tag
Definition: xpc56el.h:518
LINFLEX_BIDR_32B_tag
Definition: xpc56el.h:10259
mcPWM_OUTEN_16B_tag
Definition: xpc56el.h:9379
ADC_IMR_32B_tag
Definition: xpc56el.h:5825
FCCU_NCFS_CFG3_32B_tag
Definition: xpc56el.h:11142
CTU_THCR2_32B_tag
Definition: xpc56el.h:7517
SPP_DMA2_DMACERQ_8B_tag
Definition: xpc56el.h:14362
mcTIMER_COMP1_16B_tag
Definition: xpc56el.h:8295
FCCU_CF_CFG1_32B_tag
Definition: xpc56el.h:10634
FCCU_NCFS3_32B_tag
Definition: xpc56el.h:11522
typedefs.h
Dummy typedefs file.
FLEXCAN_MCR_32B_tag
Definition: xpc56el.h:17001
MPU_EAR_32B_tag
Definition: xpc56el.h:13256
FR_RFSYMBLADR_16B_tag
Definition: xpc56el.h:19741
INTC_tag
Definition: xpc560bc.h:2034
ADC_CDR_32B_tag
Definition: xpc56el.h:6558
SGENDIG_IRQE_32B_tag
Definition: xpc56el.h:12268
FR_SFCNTR_16B_tag
Definition: xpc56el.h:18988
AIPS_OPACR40_47_32B_tag
Definition: xpc56el.h:12679
mcPWM_INTEN_16B_tag
Definition: xpc56el.h:9077
CTU_EXPECTED_A_16B_tag
Definition: xpc56el.h:8062
RC_struct_tag
Definition: xpc56el.h:4580
FR_NMVR3_16B_tag
Definition: xpc56el.h:19075
SPP_DMA2_TCDWORD12__32B_tag
Definition: xpc56el.h:14520
CFLASH_SHADOW_NVUSRO_32B_tag
Definition: xpc56el.h:167
INTC_SSCIR0_3_32B_tag
Definition: xpc56el.h:15850
mcPWM_DTSRCSEL_16B_tag
Definition: xpc56el.h:9446
SEMA4_CP1INE_16B_tag
Definition: xpc56el.h:13616
FR_PEDRDR_16B_tag
Definition: xpc56el.h:18364
DSPI_POPR_32B_tag
Definition: xpc56el.h:16808
ADC_THRHLR14_32B_tag
Definition: xpc56el.h:6670
FR_RFWMSR_16B_tag
Definition: xpc56el.h:19294
CFLASH_ADR_32B_tag
Definition: xpc56el.h:341
WKPU_NSR_32B_tag
Definition: xpc56el.h:3411
CTU_FR_32B_tag
Definition: xpc56el.h:7778
FCCU_FAFS_32B_tag
Definition: xpc56el.h:11926
FLEXCAN_RXGMASK_32B_tag
Definition: xpc56el.h:17117
FCCU_NCFS0_32B_tag
Definition: xpc56el.h:11408
ADC_STSR3_32B_tag
Definition: xpc56el.h:6864
RGM_tag
Definition: xpc560bc.h:3005
FR_MBDSR_16B_tag
Definition: xpc56el.h:18335
INTC_IACKR_PRC0_32B_tag
Definition: xpc56el.h:15804
CTU_TGSCRR_16B_tag
Definition: xpc56el.h:7442
ADC_TRC_32B_tag
Definition: xpc56el.h:6109
vuint16_t
volatile uint16_t vuint16_t
Definition: chtypes.h:49
FCCU_CFS0_32B_tag
Definition: xpc56el.h:11252
FR_MTSBCFR_16B_tag
Definition: xpc56el.h:19272
PIT_RTI_LDVAL_32B_tag
Definition: xpc56el.h:5401
mcPWM_CAPTCTRLX_16B_tag
Definition: xpc56el.h:9219
MPU_EDR_32B_tag
Definition: xpc56el.h:13266
ADC_THRHLR8_32B_tag
Definition: xpc56el.h:6610
FR_EERDR_16B_tag
Definition: xpc56el.h:19807
mcPWM_INIT_16B_tag
Definition: xpc56el.h:8912
MAX_SLAVE_PORT_struct_tag
Definition: xpc56el.h:13089
AIPS_struct_tag
Definition: xpc56el.h:12947
FCCU_CFG_TO_32B_tag
Definition: xpc56el.h:11872
mcPWM_DISMAP_16B_tag
Definition: xpc56el.h:9126
LINFLEX_LINFBRR_32B_tag
Definition: xpc56el.h:10212
CTU_CR_16B_tag
Definition: xpc56el.h:7593
FCCU_CFS_CFG6_32B_tag
Definition: xpc56el.h:11032
ME_IMTS_32B_tag
Definition: xpc56el.h:3836
CTU_FILTER_16B_tag
Definition: xpc56el.h:8050
FCCU_MCS_32B_tag
Definition: xpc56el.h:11984
FR_PCR8_16B_tag
Definition: xpc56el.h:19492
DSPI_RSER_32B_tag
Definition: xpc56el.h:16737
CTU_CLR_SCM_16B_tag
Definition: xpc56el.h:7575
DSPI_CTAR_32B_tag
Definition: xpc56el.h:16696
mcPWM_CVAL5CYC_16B_tag
Definition: xpc56el.h:9371
FCCU_NCFE3_32B_tag
Definition: xpc56el.h:11678
INTC_IACKR_PRC1_32B_tag
Definition: xpc56el.h:15821
MPU_SLAVE_PORT_struct_tag
Definition: xpc56el.h:13371
LINFLEX_UARTCTO_32B_tag
Definition: xpc56el.h:10351
SIUL_PGPDI_16B_tag
Definition: xpc56el.h:1000
RGM_FBRE_16B_tag
Definition: xpc56el.h:5078
ADC_STAW0R_32B_tag
Definition: xpc56el.h:6906
STM_CR_32B_tag
Definition: xpc56el.h:13818
SSCM_SCTR_32B_tag
Definition: xpc56el.h:3634
ADC_MCR_32B_tag
Definition: xpc56el.h:5513
PIT_RTI_PITMCR_32B_tag
Definition: xpc56el.h:5389
CGM_AC_SC_32B_tag
Definition: xpc56el.h:4808
FCCU_NCFE_32B_tag
Definition: xpc56el.h:12051
FLEXCAN_MSG_DATA2_32B_tag
Definition: xpc56el.h:17511
ADC_DMAR0_32B_tag
Definition: xpc56el.h:5992
DSPI_DDR_32B_tag
Definition: xpc56el.h:16899
FR_SSCR0_16B_tag
Definition: xpc56el.h:19233
FLEXCAN_struct_tag
Definition: xpc56el.h:17555
mcPWM_CVAL2CYC_16B_tag
Definition: xpc56el.h:9308
mcTIMER_CTRL1_16B_tag
Definition: xpc56el.h:8365
PCU_tag
Definition: xpc560bc.h:2908
FR_TICCR_16B_tag
Definition: xpc56el.h:19107
AIPS_OPACR48_55_32B_tag
Definition: xpc56el.h:12717
LINFLEX_LINOCR_32B_tag
Definition: xpc56el.h:10193
CTU_CNT_RANGE_16B_tag
Definition: xpc56el.h:8076
SPP_MCM_PREAR_32B_tag
Definition: xpc56el.h:14112
DSPI_PUSHR_32B_tag
Definition: xpc56el.h:16788
CMU_IMR_32B_tag
Definition: xpc56el.h:4700
FCCU_CF_CFG_32B_tag
Definition: xpc56el.h:12009
FCCU_NFFS_32B_tag
Definition: xpc56el.h:11917
SSCM_DEBUGPORT_16B_tag
Definition: xpc56el.h:3589
ADC_CIMR0_32B_tag
Definition: xpc56el.h:5839
ADC_AWORR_32B_tag
Definition: xpc56el.h:6736
FR_PCR3_16B_tag
Definition: xpc56el.h:19441
ADC_STSR1_32B_tag
Definition: xpc56el.h:6831
FCCU_NCFE0_32B_tag
Definition: xpc56el.h:11564
FR_CIFR_16B_tag
Definition: xpc56el.h:18933
PMUCTRL_IRQS_32B_tag
Definition: xpc56el.h:5313
mcPWM_CNT_16B_tag
Definition: xpc56el.h:8905
CFLASH_BIU_32B_tag
Definition: xpc56el.h:440
CTU_tag
Definition: xpc560bc.h:899
CTU_TGSISR_32B_tag
Definition: xpc56el.h:7368
CTU_EXPECTED_B_16B_tag
Definition: xpc56el.h:8069
CMU_HFREFR_A_32B_tag
Definition: xpc56el.h:4673
FR_PCR20_16B_tag
Definition: xpc56el.h:19610
ME_RESET_MC_32B_tag
Definition: xpc56el.h:3875
FR_NMVR1_16B_tag
Definition: xpc56el.h:19059
FLEXCAN_RX14MASK_32B_tag
Definition: xpc56el.h:17126
ADC_DMAR1_32B_tag
Definition: xpc56el.h:6030
FLEXCAN_RX15MASK_32B_tag
Definition: xpc56el.h:17135
DIR
Definition: ff.h:178
CTU_FRA_32B_tag
Definition: xpc56el.h:8087
FCCU_NCFS_CFG5_32B_tag
Definition: xpc56el.h:11186
ADC_CWENR_32B_tag
Definition: xpc56el.h:6710
ADC_STBRR_32B_tag
Definition: xpc56el.h:6821
CGM_AUXCLK_struct_tag
Definition: xpc56el.h:4837
FCCU_CF_CFG3_32B_tag
Definition: xpc56el.h:10710
FR_PIER0_16B_tag
Definition: xpc56el.h:18566
CFLASH_LML_32B_tag
Definition: xpc56el.h:272
ADC_CIMR1_32B_tag
Definition: xpc56el.h:5877
STM_CCR_32B_tag
Definition: xpc56el.h:13836
mcPWM_VAL_2_16B_tag
Definition: xpc56el.h:8985
PMUCTRL_CTRL_32B_tag
Definition: xpc56el.h:5282
FCCU_EINOUT_32B_tag
Definition: xpc56el.h:11880
FR_PEDRAR_16B_tag
Definition: xpc56el.h:18355
FR_struct_tag
Definition: xpc56el.h:19945
FR_PCR10_16B_tag
Definition: xpc56el.h:19510
SPP_DMA2_DMACEEI_8B_tag
Definition: xpc56el.h:14378
INTC_EOIR_PRC0_32B_tag
Definition: xpc56el.h:15830
LINFLEX_LINESR_32B_tag
Definition: xpc56el.h:10101
STM_CHANNEL_struct_tag
Definition: xpc56el.h:13863
PMUCTRL_struct_tag
Definition: xpc56el.h:5351
mcPWM_FFILT_16B_tag
Definition: xpc56el.h:9527
SPP_MCM_MWCR_8B_tag
Definition: xpc56el.h:13975
FCCU_NCFS_32B_tag
Definition: xpc56el.h:12044
AIPS_PACR0_7_32B_tag
Definition: xpc56el.h:12337
FR_POCR_16B_tag
Definition: xpc56el.h:18371
FR_SSCR2_16B_tag
Definition: xpc56el.h:19247
CGM_SC_DC_8B_tag
Definition: xpc56el.h:4796
ME_IS_32B_tag
Definition: xpc56el.h:3782
FCCU_NCFS_CFG0_32B_tag
Definition: xpc56el.h:11076
mcPWM_TCTRL_16B_tag
Definition: xpc56el.h:9115
MPU_tag
Definition: xpc560bc.h:2731
mcPWM_CVAL0CYC_16B_tag
Definition: xpc56el.h:9266
CFLASH_SHADOW_NVHBL_32B_tag
Definition: xpc56el.h:149
ADC_CEOCFR1_32B_tag
Definition: xpc56el.h:5749
CTU_CLR_DCM_16B_tag
Definition: xpc56el.h:7558
FR_SYMBADHR_16B_tag
Definition: xpc56el.h:18307
vuint32_t
volatile uint32_t vuint32_t
Definition: chtypes.h:51
PS
Definition: lpc214x.h:110
FCCU_CTRL_32B_tag
Definition: xpc56el.h:10565
ADC_STAW1AR_32B_tag
Definition: xpc56el.h:6918
CFLASH_HBL_32B_tag
Definition: xpc56el.h:293
mcPWM_FCTRL_16B_tag
Definition: xpc56el.h:9506
CMU_MDR_32B_tag
Definition: xpc56el.h:4704
FR_PCR22_16B_tag
Definition: xpc56el.h:19634
SIUL_IREER_32B_tag
Definition: xpc56el.h:762
CFLASH_PFCR1_32B_tag
Definition: xpc56el.h:444
SIUL_GPDI_32B_tag
Definition: xpc56el.h:976
SIUL_MIDR1_32B_tag
Definition: xpc56el.h:646
CRC_tag
Definition: xpc560p.h:7722
DSPI_RXFR_32B_tag
Definition: xpc56el.h:16838
CFLASH_PFCR_32B_tag
Definition: xpc56el.h:546
FR_NMVR5_16B_tag
Definition: xpc56el.h:19091
FCCU_struct_tag
Definition: xpc56el.h:12064
ME_STOP0_MC_32B_tag
Definition: xpc56el.h:4048
SIUL_GPDO_32B_tag
Definition: xpc56el.h:948
AIPS_PACR8_15_32B_tag
Definition: xpc56el.h:12375
WKPU_NCR_32B_tag
Definition: xpc56el.h:3429
FR_MTCTR_16B_tag
Definition: xpc56el.h:18886
mcTIMER_CAPT1_16B_tag
Definition: xpc56el.h:8315
INTC_PSR_8B_tag
Definition: xpc56el.h:15889
LINFLEX_DMARXE_32B_tag
Definition: xpc56el.h:10367
FR_EEIFER_16B_tag
Definition: xpc56el.h:19765
FCCU_CFS_CFG4_32B_tag
Definition: xpc56el.h:10988
mcPWM_SWCOUT_16B_tag
Definition: xpc56el.h:9399
SPP_DMA2_TCDWORD4__32B_tag
Definition: xpc56el.h:14493
MAX_ASGPCR_32B_tag
Definition: xpc56el.h:13054
ME_HALT0_MC_32B_tag
Definition: xpc56el.h:4010
INTC_CPR_PRC1_32B_tag
Definition: xpc56el.h:15796
FR_PSR0_16B_tag
Definition: xpc56el.h:18809
FCCU_NCF_CFG1_32B_tag
Definition: xpc56el.h:10786
FR_STBSCR_16B_tag
Definition: xpc56el.h:18322
FR_CYCTR_16B_tag
Definition: xpc56el.h:18894
CRC_CFG_32B_tag
Definition: xpc56el.h:10461
mcPWM_CAPTCMPA_16B_tag
Definition: xpc56el.h:9179
FR_PCR2_16B_tag
Definition: xpc56el.h:19433
ADC_STSR2_32B_tag
Definition: xpc56el.h:6853
CFLASH_MCR_32B_tag
Definition: xpc56el.h:247
mcTIMER_INTDMA_16B_tag
Definition: xpc56el.h:8437
LINFLEX_LINCR1_32B_tag
Definition: xpc56el.h:10016
FLEXCAN_TIMER_32B_tag
Definition: xpc56el.h:17113
mcPWM_CVAL1_16B_tag
Definition: xpc56el.h:9277
mcPWM_OCTRL_16B_tag
Definition: xpc56el.h:9037
mcPWM_VAL_4_16B_tag
Definition: xpc56el.h:8999
mcPWM_MCTRL_16B_tag
Definition: xpc56el.h:9492
FR_EEIAR_16B_tag
Definition: xpc56el.h:19822
CTU_CTUIR_16B_tag
Definition: xpc56el.h:7903
FR_PCR12_16B_tag
Definition: xpc56el.h:19528
FR_RFMIDAFVR_16B_tag
Definition: xpc56el.h:19344
CGM_OCDS_SC_32B_tag
Definition: xpc56el.h:4755
FCCU_CFS_32B_tag
Definition: xpc56el.h:12037
FLEXCAN_RXIMR_32B_tag
Definition: xpc56el.h:17523
PCU_struct_tag
Definition: xpc56el.h:5185
LINFLEX_LINTCSR_32B_tag
Definition: xpc56el.h:10178
FR_MBIDXR_16B_tag
Definition: xpc56el.h:19906
ADC_THRHLR5_32B_tag
Definition: xpc56el.h:6580
ME_DRUN_MC_32B_tag
Definition: xpc56el.h:3951
SPP_DMA2_DMACR_32B_tag
Definition: xpc56el.h:14285
FR_tag
Definition: xpc560p.h:6989
FR_NMVR4_16B_tag
Definition: xpc56el.h:19083
CFLASH_UT1_32B_tag
Definition: xpc56el.h:514
SEMA4_GATE_8B_tag
Definition: xpc56el.h:13601
FLEXCAN_MSG_CS_32B_tag
Definition: xpc56el.h:17476
ADC_DMAR2_32B_tag
Definition: xpc56el.h:6068
SWT_WN_32B_tag
Definition: xpc56el.h:13758
FR_MCR_16B_tag
Definition: xpc56el.h:18279
PLLD_MR_32B_tag
Definition: xpc56el.h:4617
mcTIMER_DREQ0_16B_tag
Definition: xpc56el.h:8575
SSCM_TF_INFO0_32B_tag
Definition: xpc56el.h:3644
ME_struct_tag
Definition: xpc56el.h:4232
mcTIMER_CTRL3_16B_tag
Definition: xpc56el.h:8401
FCCU_CFS_CFG1_32B_tag
Definition: xpc56el.h:10922
DSPI_struct_tag
Definition: xpc56el.h:16913
AIPS_OPACR80_87_32B_tag
Definition: xpc56el.h:12869
SSCM_TF_INFO2_32B_tag
Definition: xpc56el.h:3658
PIT_RTI_CHANNEL_struct_tag
Definition: xpc56el.h:5442
SIUL_GPDO_8B_tag
Definition: xpc56el.h:937
RGM_FERD_16B_tag
Definition: xpc56el.h:4986
SEMA4_RSTNTF_16B_tag
Definition: xpc56el.h:13648
CRC_INP_32B_tag
Definition: xpc56el.h:10477
FR_OFCORVR_16B_tag
Definition: xpc56el.h:18925
mcPWM_DMAEN_16B_tag
Definition: xpc56el.h:9096
ADC_CIMR2_32B_tag
Definition: xpc56el.h:5915
FR_PCR5_16B_tag
Definition: xpc56el.h:19462
ADC_PDEDR_32B_tag
Definition: xpc56el.h:6547
DMA_CH_MUX_CHCONFIG_8B_tag
Definition: xpc56el.h:18221
mcPWM_CVAL4_16B_tag
Definition: xpc56el.h:9340
FR_EERCR_16B_tag
Definition: xpc56el.h:19814
SPP_DMA2_struct_tag
Definition: xpc56el.h:14603
mcTIMER_CHANNEL_struct_tag
Definition: xpc56el.h:8615
FR_PCR26_16B_tag
Definition: xpc56el.h:19686
CGM_struct_tag
Definition: xpc56el.h:4847
SPP_DMA2_CHANNEL_struct_tag
Definition: xpc56el.h:14581
LINFLEX_UARTSR_32B_tag
Definition: xpc56el.h:10150
INTC_struct_tag
Definition: xpc56el.h:15921
SPP_DMA2_TCDWORD16__32B_tag
Definition: xpc56el.h:14530
SGENDIG_CTRL_32B_tag
Definition: xpc56el.h:12254
ME_PS0_32B_tag
Definition: xpc56el.h:4124
SPP_MCM_PREDRH_32B_tag
Definition: xpc56el.h:14153
DSPI_TXFR_32B_tag
Definition: xpc56el.h:16819
WKPU_struct_tag
Definition: xpc56el.h:3514
SEMA4_CP1NTF_16B_tag
Definition: xpc56el.h:13630
SSCM_TF_INFO3_32B_tag
Definition: xpc56el.h:3665
FCCU_NCFS_CFG7_32B_tag
Definition: xpc56el.h:11230
MAX_MASTER_PORT_struct_tag
Definition: xpc56el.h:13104
ADC_DMAE_32B_tag
Definition: xpc56el.h:5983
AIPS_OPACR32_39_32B_tag
Definition: xpc56el.h:12641
FCCU_NCF_TOE1_32B_tag
Definition: xpc56el.h:11754
SSCM_DPMBOOT_32B_tag
Definition: xpc56el.h:3611
LINFLEX_BDRM_32B_tag
Definition: xpc56el.h:10281
mcPWM_VAL_0_16B_tag
Definition: xpc56el.h:8971
CTU_CLCR1_32B_tag
Definition: xpc56el.h:7451
INTC_SSCIR_8B_tag
Definition: xpc56el.h:15841
LINFLEX_LINIER_32B_tag
Definition: xpc56el.h:10048
FR_PCR16_16B_tag
Definition: xpc56el.h:19567
ADC_STDR1_32B_tag
Definition: xpc56el.h:6884
FR_TI2CR1_16B_tag
Definition: xpc56el.h:19174
FLEXCAN_IMASK2_32B_tag
Definition: xpc56el.h:17241
mcTIMER_CMPLD1_16B_tag
Definition: xpc56el.h:8461
FR_PCR29_16B_tag
Definition: xpc56el.h:19718
FR_NMVLR_16B_tag
Definition: xpc56el.h:19099
LINFLEX_LINSR_32B_tag
Definition: xpc56el.h:10074
SPP_MCM_PREDR_32B_tag
Definition: xpc56el.h:14157
mcTIMER_FCTRL_16B_tag
Definition: xpc56el.h:8529
FR_GIFER_16B_tag
Definition: xpc56el.h:18384
FR_PIFR0_16B_tag
Definition: xpc56el.h:18422
WKPU_WIREER_32B_tag
Definition: xpc56el.h:3484
FR_SSSR_16B_tag
Definition: xpc56el.h:19181
CFLASH_SLL_32B_tag
Definition: xpc56el.h:302
SSCM_ERROR_16B_tag
Definition: xpc56el.h:3580
CTU_TGSCR_16B_tag
Definition: xpc56el.h:7406
ADC_OFFWR_32B_tag
Definition: xpc56el.h:6525
FR_LDTXSLAR_16B_tag
Definition: xpc56el.h:19401
FR_PCR1_16B_tag
Definition: xpc56el.h:19425
RGM_DERD_16B_tag
Definition: xpc56el.h:5012
FR_RFPTR_16B_tag
Definition: xpc56el.h:19749
SSCM_PWCMPL_32B_tag
Definition: xpc56el.h:3604
FR_SFIDRFR_16B_tag
Definition: xpc56el.h:19027
WKPU_WRER_32B_tag
Definition: xpc56el.h:3477
PMUCTRL_MASKF_32B_tag
Definition: xpc56el.h:5290
FR_PCR19_16B_tag
Definition: xpc56el.h:19602
mcTIMER_FILT_16B_tag
Definition: xpc56el.h:8498
FR_EERICR_16B_tag
Definition: xpc56el.h:19784
FR_RFMIDAFMR_16B_tag
Definition: xpc56el.h:19351
AIPS_OPACR88_95_32B_tag
Definition: xpc56el.h:12907
FR_PCR18_16B_tag
Definition: xpc56el.h:19594
CRC_CSTAT_32B_tag
Definition: xpc56el.h:10487
LINFLEX_LINIBRR_32B_tag
Definition: xpc56el.h:10224
FR_RFBRIR_16B_tag
Definition: xpc56el.h:19336
SEMA4_RSTGT_16B_tag
Definition: xpc56el.h:13637
AIPS_OPACR8_15_32B_tag
Definition: xpc56el.h:12527
mcTIMER_STS_16B_tag
Definition: xpc56el.h:8417
SIUL_IFEER_32B_tag
Definition: xpc56el.h:800
DSPI_SDR_32B_tag
Definition: xpc56el.h:16875
FR_SLTCTAR_16B_tag
Definition: xpc56el.h:18902
UART
Definition: lpc214x.h:261
SPP_DMA2_DCHPRI_8B_tag
Definition: xpc56el.h:14470
CGM_AC_DC0_3_32B_tag
Definition: xpc56el.h:4823
CMU_ISR_32B_tag
Definition: xpc56el.h:4689
SPP_DMA2_DMAINTH_32B_tag
Definition: xpc56el.h:14418
CGM_OC_EN_32B_tag
Definition: xpc56el.h:4744
FR_RFFIDRFMR_16B_tag
Definition: xpc56el.h:19366
ADC_THRHLR13_32B_tag
Definition: xpc56el.h:6660
mcPWM_MASK_16B_tag
Definition: xpc56el.h:9389
PIT_RTI_TCTRL_32B_tag
Definition: xpc56el.h:5421
SPP_DMA2_DMAERRL_32B_tag
Definition: xpc56el.h:14439
FCCU_NCFS1_32B_tag
Definition: xpc56el.h:11446
SPP_DMA2_DMAHRSL_32B_tag
Definition: xpc56el.h:14453
ADC_STSR4_32B_tag
Definition: xpc56el.h:6874
INTC_BCR_32B_tag
Definition: xpc56el.h:15766
FLEXCAN_MSG_ID_32B_tag
Definition: xpc56el.h:17493
AIPS_OPACR0_7_32B_tag
Definition: xpc56el.h:12489
MPU_struct_tag
Definition: xpc56el.h:13394
CFLASH_PFCR0_32B_tag
Definition: xpc56el.h:351
FCCU_CFS1_32B_tag
Definition: xpc56el.h:11290
ADC_WTISR_32B_tag
Definition: xpc56el.h:5953
CTU_FLA_32B_tag
Definition: xpc56el.h:8094
SIUL_GPDI_8B_tag
Definition: xpc56el.h:965
Generated by   doxygen 1.8.18